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Merge git://git.kernel.org/pub/scm/linux/kernel/git/sam/kbuild
[deliverable/linux.git] / drivers / char / drm / radeon_drv.h
1 /* radeon_drv.h -- Private header for radeon driver -*- linux-c -*-
2 *
3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All rights reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31 #ifndef __RADEON_DRV_H__
32 #define __RADEON_DRV_H__
33
34 /* General customization:
35 */
36
37 #define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."
38
39 #define DRIVER_NAME "radeon"
40 #define DRIVER_DESC "ATI Radeon"
41 #define DRIVER_DATE "20060524"
42
43 /* Interface history:
44 *
45 * 1.1 - ??
46 * 1.2 - Add vertex2 ioctl (keith)
47 * - Add stencil capability to clear ioctl (gareth, keith)
48 * - Increase MAX_TEXTURE_LEVELS (brian)
49 * 1.3 - Add cmdbuf ioctl (keith)
50 * - Add support for new radeon packets (keith)
51 * - Add getparam ioctl (keith)
52 * - Add flip-buffers ioctl, deprecate fullscreen foo (keith).
53 * 1.4 - Add scratch registers to get_param ioctl.
54 * 1.5 - Add r200 packets to cmdbuf ioctl
55 * - Add r200 function to init ioctl
56 * - Add 'scalar2' instruction to cmdbuf
57 * 1.6 - Add static GART memory manager
58 * Add irq handler (won't be turned on unless X server knows to)
59 * Add irq ioctls and irq_active getparam.
60 * Add wait command for cmdbuf ioctl
61 * Add GART offset query for getparam
62 * 1.7 - Add support for cube map registers: R200_PP_CUBIC_FACES_[0..5]
63 * and R200_PP_CUBIC_OFFSET_F1_[0..5].
64 * Added packets R200_EMIT_PP_CUBIC_FACES_[0..5] and
65 * R200_EMIT_PP_CUBIC_OFFSETS_[0..5]. (brian)
66 * 1.8 - Remove need to call cleanup ioctls on last client exit (keith)
67 * Add 'GET' queries for starting additional clients on different VT's.
68 * 1.9 - Add DRM_IOCTL_RADEON_CP_RESUME ioctl.
69 * Add texture rectangle support for r100.
70 * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
71 * clients use to tell the DRM where they think the framebuffer is
72 * located in the card's address space
73 * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
74 * and GL_EXT_blend_[func|equation]_separate on r200
75 * 1.12- Add R300 CP microcode support - this just loads the CP on r300
76 * (No 3D support yet - just microcode loading).
77 * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
78 * - Add hyperz support, add hyperz flags to clear ioctl.
79 * 1.14- Add support for color tiling
80 * - Add R100/R200 surface allocation/free support
81 * 1.15- Add support for texture micro tiling
82 * - Add support for r100 cube maps
83 * 1.16- Add R200_EMIT_PP_TRI_PERF_CNTL packet to support brilinear
84 * texture filtering on r200
85 * 1.17- Add initial support for R300 (3D).
86 * 1.18- Add support for GL_ATI_fragment_shader, new packets
87 * R200_EMIT_PP_AFS_0/1, R200_EMIT_PP_TXCTLALL_0-5 (replaces
88 * R200_EMIT_PP_TXFILTER_0-5, 2 more regs) and R200_EMIT_ATF_TFACTOR
89 * (replaces R200_EMIT_TFACTOR_0 (8 consts instead of 6)
90 * 1.19- Add support for gart table in FB memory and PCIE r300
91 * 1.20- Add support for r300 texrect
92 * 1.21- Add support for card type getparam
93 * 1.22- Add support for texture cache flushes (R300_TX_CNTL)
94 * 1.23- Add new radeon memory map work from benh
95 * 1.24- Add general-purpose packet for manipulating scratch registers (r300)
96 * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL,
97 * new packet type)
98 */
99 #define DRIVER_MAJOR 1
100 #define DRIVER_MINOR 25
101 #define DRIVER_PATCHLEVEL 0
102
103 /*
104 * Radeon chip families
105 */
106 enum radeon_family {
107 CHIP_R100,
108 CHIP_RV100,
109 CHIP_RS100,
110 CHIP_RV200,
111 CHIP_RS200,
112 CHIP_R200,
113 CHIP_RV250,
114 CHIP_RS300,
115 CHIP_RV280,
116 CHIP_R300,
117 CHIP_R350,
118 CHIP_RV350,
119 CHIP_RV380,
120 CHIP_R420,
121 CHIP_RV410,
122 CHIP_RS400,
123 CHIP_LAST,
124 };
125
126 enum radeon_cp_microcode_version {
127 UCODE_R100,
128 UCODE_R200,
129 UCODE_R300,
130 };
131
132 /*
133 * Chip flags
134 */
135 enum radeon_chip_flags {
136 RADEON_FAMILY_MASK = 0x0000ffffUL,
137 RADEON_FLAGS_MASK = 0xffff0000UL,
138 RADEON_IS_MOBILITY = 0x00010000UL,
139 RADEON_IS_IGP = 0x00020000UL,
140 RADEON_SINGLE_CRTC = 0x00040000UL,
141 RADEON_IS_AGP = 0x00080000UL,
142 RADEON_HAS_HIERZ = 0x00100000UL,
143 RADEON_IS_PCIE = 0x00200000UL,
144 RADEON_NEW_MEMMAP = 0x00400000UL,
145 RADEON_IS_PCI = 0x00800000UL,
146 };
147
148 #define GET_RING_HEAD(dev_priv) (dev_priv->writeback_works ? \
149 DRM_READ32( (dev_priv)->ring_rptr, 0 ) : RADEON_READ(RADEON_CP_RB_RPTR))
150 #define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) )
151
152 typedef struct drm_radeon_freelist {
153 unsigned int age;
154 drm_buf_t *buf;
155 struct drm_radeon_freelist *next;
156 struct drm_radeon_freelist *prev;
157 } drm_radeon_freelist_t;
158
159 typedef struct drm_radeon_ring_buffer {
160 u32 *start;
161 u32 *end;
162 int size;
163 int size_l2qw;
164
165 u32 tail;
166 u32 tail_mask;
167 int space;
168
169 int high_mark;
170 } drm_radeon_ring_buffer_t;
171
172 typedef struct drm_radeon_depth_clear_t {
173 u32 rb3d_cntl;
174 u32 rb3d_zstencilcntl;
175 u32 se_cntl;
176 } drm_radeon_depth_clear_t;
177
178 struct drm_radeon_driver_file_fields {
179 int64_t radeon_fb_delta;
180 };
181
182 struct mem_block {
183 struct mem_block *next;
184 struct mem_block *prev;
185 int start;
186 int size;
187 DRMFILE filp; /* 0: free, -1: heap, other: real files */
188 };
189
190 struct radeon_surface {
191 int refcount;
192 u32 lower;
193 u32 upper;
194 u32 flags;
195 };
196
197 struct radeon_virt_surface {
198 int surface_index;
199 u32 lower;
200 u32 upper;
201 u32 flags;
202 DRMFILE filp;
203 };
204
205 typedef struct drm_radeon_private {
206 drm_radeon_ring_buffer_t ring;
207 drm_radeon_sarea_t *sarea_priv;
208
209 u32 fb_location;
210 u32 fb_size;
211 int new_memmap;
212
213 int gart_size;
214 u32 gart_vm_start;
215 unsigned long gart_buffers_offset;
216
217 int cp_mode;
218 int cp_running;
219
220 drm_radeon_freelist_t *head;
221 drm_radeon_freelist_t *tail;
222 int last_buf;
223 volatile u32 *scratch;
224 int writeback_works;
225
226 int usec_timeout;
227
228 int microcode_version;
229
230 struct {
231 u32 boxes;
232 int freelist_timeouts;
233 int freelist_loops;
234 int requested_bufs;
235 int last_frame_reads;
236 int last_clear_reads;
237 int clears;
238 int texture_uploads;
239 } stats;
240
241 int do_boxes;
242 int page_flipping;
243 int current_page;
244
245 u32 color_fmt;
246 unsigned int front_offset;
247 unsigned int front_pitch;
248 unsigned int back_offset;
249 unsigned int back_pitch;
250
251 u32 depth_fmt;
252 unsigned int depth_offset;
253 unsigned int depth_pitch;
254
255 u32 front_pitch_offset;
256 u32 back_pitch_offset;
257 u32 depth_pitch_offset;
258
259 drm_radeon_depth_clear_t depth_clear;
260
261 unsigned long ring_offset;
262 unsigned long ring_rptr_offset;
263 unsigned long buffers_offset;
264 unsigned long gart_textures_offset;
265
266 drm_local_map_t *sarea;
267 drm_local_map_t *mmio;
268 drm_local_map_t *cp_ring;
269 drm_local_map_t *ring_rptr;
270 drm_local_map_t *gart_textures;
271
272 struct mem_block *gart_heap;
273 struct mem_block *fb_heap;
274
275 /* SW interrupt */
276 wait_queue_head_t swi_queue;
277 atomic_t swi_emitted;
278
279 struct radeon_surface surfaces[RADEON_MAX_SURFACES];
280 struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
281
282 unsigned long pcigart_offset;
283 drm_ati_pcigart_info gart_info;
284
285 u32 scratch_ages[5];
286
287 /* starting from here on, data is preserved accross an open */
288 uint32_t flags; /* see radeon_chip_flags */
289 } drm_radeon_private_t;
290
291 typedef struct drm_radeon_buf_priv {
292 u32 age;
293 } drm_radeon_buf_priv_t;
294
295 typedef struct drm_radeon_kcmd_buffer {
296 int bufsz;
297 char *buf;
298 int nbox;
299 drm_clip_rect_t __user *boxes;
300 } drm_radeon_kcmd_buffer_t;
301
302 extern int radeon_no_wb;
303 extern drm_ioctl_desc_t radeon_ioctls[];
304 extern int radeon_max_ioctl;
305
306 /* radeon_cp.c */
307 extern int radeon_cp_init(DRM_IOCTL_ARGS);
308 extern int radeon_cp_start(DRM_IOCTL_ARGS);
309 extern int radeon_cp_stop(DRM_IOCTL_ARGS);
310 extern int radeon_cp_reset(DRM_IOCTL_ARGS);
311 extern int radeon_cp_idle(DRM_IOCTL_ARGS);
312 extern int radeon_cp_resume(DRM_IOCTL_ARGS);
313 extern int radeon_engine_reset(DRM_IOCTL_ARGS);
314 extern int radeon_fullscreen(DRM_IOCTL_ARGS);
315 extern int radeon_cp_buffers(DRM_IOCTL_ARGS);
316
317 extern void radeon_freelist_reset(drm_device_t * dev);
318 extern drm_buf_t *radeon_freelist_get(drm_device_t * dev);
319
320 extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
321
322 extern int radeon_do_cp_idle(drm_radeon_private_t * dev_priv);
323
324 extern int radeon_driver_preinit(struct drm_device *dev, unsigned long flags);
325 extern int radeon_presetup(struct drm_device *dev);
326 extern int radeon_driver_postcleanup(struct drm_device *dev);
327
328 extern int radeon_mem_alloc(DRM_IOCTL_ARGS);
329 extern int radeon_mem_free(DRM_IOCTL_ARGS);
330 extern int radeon_mem_init_heap(DRM_IOCTL_ARGS);
331 extern void radeon_mem_takedown(struct mem_block **heap);
332 extern void radeon_mem_release(DRMFILE filp, struct mem_block *heap);
333
334 /* radeon_irq.c */
335 extern int radeon_irq_emit(DRM_IOCTL_ARGS);
336 extern int radeon_irq_wait(DRM_IOCTL_ARGS);
337
338 extern void radeon_do_release(drm_device_t * dev);
339 extern int radeon_driver_vblank_wait(drm_device_t * dev,
340 unsigned int *sequence);
341 extern irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS);
342 extern void radeon_driver_irq_preinstall(drm_device_t * dev);
343 extern void radeon_driver_irq_postinstall(drm_device_t * dev);
344 extern void radeon_driver_irq_uninstall(drm_device_t * dev);
345
346 extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
347 extern int radeon_driver_unload(struct drm_device *dev);
348 extern int radeon_driver_firstopen(struct drm_device *dev);
349 extern void radeon_driver_preclose(drm_device_t * dev, DRMFILE filp);
350 extern void radeon_driver_postclose(drm_device_t * dev, drm_file_t * filp);
351 extern void radeon_driver_lastclose(drm_device_t * dev);
352 extern int radeon_driver_open(drm_device_t * dev, drm_file_t * filp_priv);
353 extern long radeon_compat_ioctl(struct file *filp, unsigned int cmd,
354 unsigned long arg);
355
356 /* r300_cmdbuf.c */
357 extern void r300_init_reg_flags(void);
358
359 extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp,
360 drm_file_t * filp_priv,
361 drm_radeon_kcmd_buffer_t * cmdbuf);
362
363 /* Flags for stats.boxes
364 */
365 #define RADEON_BOX_DMA_IDLE 0x1
366 #define RADEON_BOX_RING_FULL 0x2
367 #define RADEON_BOX_FLIP 0x4
368 #define RADEON_BOX_WAIT_IDLE 0x8
369 #define RADEON_BOX_TEXTURE_LOAD 0x10
370
371 /* Register definitions, register access macros and drmAddMap constants
372 * for Radeon kernel driver.
373 */
374
375 #define RADEON_AGP_COMMAND 0x0f60
376 #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
377 # define RADEON_AGP_ENABLE (1<<8)
378 #define RADEON_AUX_SCISSOR_CNTL 0x26f0
379 # define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)
380 # define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)
381 # define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)
382 # define RADEON_SCISSOR_0_ENABLE (1 << 28)
383 # define RADEON_SCISSOR_1_ENABLE (1 << 29)
384 # define RADEON_SCISSOR_2_ENABLE (1 << 30)
385
386 #define RADEON_BUS_CNTL 0x0030
387 # define RADEON_BUS_MASTER_DIS (1 << 6)
388
389 #define RADEON_CLOCK_CNTL_DATA 0x000c
390 # define RADEON_PLL_WR_EN (1 << 7)
391 #define RADEON_CLOCK_CNTL_INDEX 0x0008
392 #define RADEON_CONFIG_APER_SIZE 0x0108
393 #define RADEON_CONFIG_MEMSIZE 0x00f8
394 #define RADEON_CRTC_OFFSET 0x0224
395 #define RADEON_CRTC_OFFSET_CNTL 0x0228
396 # define RADEON_CRTC_TILE_EN (1 << 15)
397 # define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)
398 #define RADEON_CRTC2_OFFSET 0x0324
399 #define RADEON_CRTC2_OFFSET_CNTL 0x0328
400
401 #define RADEON_PCIE_INDEX 0x0030
402 #define RADEON_PCIE_DATA 0x0034
403 #define RADEON_PCIE_TX_GART_CNTL 0x10
404 # define RADEON_PCIE_TX_GART_EN (1 << 0)
405 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0<<1)
406 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1<<1)
407 # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3<<1)
408 # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0<<3)
409 # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1<<3)
410 # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1<<5)
411 # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1<<8)
412 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11
413 #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12
414 #define RADEON_PCIE_TX_GART_BASE 0x13
415 #define RADEON_PCIE_TX_GART_START_LO 0x14
416 #define RADEON_PCIE_TX_GART_START_HI 0x15
417 #define RADEON_PCIE_TX_GART_END_LO 0x16
418 #define RADEON_PCIE_TX_GART_END_HI 0x17
419
420 #define RADEON_MPP_TB_CONFIG 0x01c0
421 #define RADEON_MEM_CNTL 0x0140
422 #define RADEON_MEM_SDRAM_MODE_REG 0x0158
423 #define RADEON_AGP_BASE 0x0170
424
425 #define RADEON_RB3D_COLOROFFSET 0x1c40
426 #define RADEON_RB3D_COLORPITCH 0x1c48
427
428 #define RADEON_SRC_X_Y 0x1590
429
430 #define RADEON_DP_GUI_MASTER_CNTL 0x146c
431 # define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
432 # define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
433 # define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)
434 # define RADEON_GMC_BRUSH_NONE (15 << 4)
435 # define RADEON_GMC_DST_16BPP (4 << 8)
436 # define RADEON_GMC_DST_24BPP (5 << 8)
437 # define RADEON_GMC_DST_32BPP (6 << 8)
438 # define RADEON_GMC_DST_DATATYPE_SHIFT 8
439 # define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)
440 # define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)
441 # define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)
442 # define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)
443 # define RADEON_GMC_WR_MSK_DIS (1 << 30)
444 # define RADEON_ROP3_S 0x00cc0000
445 # define RADEON_ROP3_P 0x00f00000
446 #define RADEON_DP_WRITE_MASK 0x16cc
447 #define RADEON_SRC_PITCH_OFFSET 0x1428
448 #define RADEON_DST_PITCH_OFFSET 0x142c
449 #define RADEON_DST_PITCH_OFFSET_C 0x1c80
450 # define RADEON_DST_TILE_LINEAR (0 << 30)
451 # define RADEON_DST_TILE_MACRO (1 << 30)
452 # define RADEON_DST_TILE_MICRO (2 << 30)
453 # define RADEON_DST_TILE_BOTH (3 << 30)
454
455 #define RADEON_SCRATCH_REG0 0x15e0
456 #define RADEON_SCRATCH_REG1 0x15e4
457 #define RADEON_SCRATCH_REG2 0x15e8
458 #define RADEON_SCRATCH_REG3 0x15ec
459 #define RADEON_SCRATCH_REG4 0x15f0
460 #define RADEON_SCRATCH_REG5 0x15f4
461 #define RADEON_SCRATCH_UMSK 0x0770
462 #define RADEON_SCRATCH_ADDR 0x0774
463
464 #define RADEON_SCRATCHOFF( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))
465
466 #define GET_SCRATCH( x ) (dev_priv->writeback_works \
467 ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
468 : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
469
470 #define RADEON_GEN_INT_CNTL 0x0040
471 # define RADEON_CRTC_VBLANK_MASK (1 << 0)
472 # define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)
473 # define RADEON_SW_INT_ENABLE (1 << 25)
474
475 #define RADEON_GEN_INT_STATUS 0x0044
476 # define RADEON_CRTC_VBLANK_STAT (1 << 0)
477 # define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
478 # define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)
479 # define RADEON_SW_INT_TEST (1 << 25)
480 # define RADEON_SW_INT_TEST_ACK (1 << 25)
481 # define RADEON_SW_INT_FIRE (1 << 26)
482
483 #define RADEON_HOST_PATH_CNTL 0x0130
484 # define RADEON_HDP_SOFT_RESET (1 << 26)
485 # define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)
486 # define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)
487
488 #define RADEON_ISYNC_CNTL 0x1724
489 # define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
490 # define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)
491 # define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)
492 # define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)
493 # define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)
494 # define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)
495
496 #define RADEON_RBBM_GUICNTL 0x172c
497 # define RADEON_HOST_DATA_SWAP_NONE (0 << 0)
498 # define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)
499 # define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)
500 # define RADEON_HOST_DATA_SWAP_HDW (3 << 0)
501
502 #define RADEON_MC_AGP_LOCATION 0x014c
503 #define RADEON_MC_FB_LOCATION 0x0148
504 #define RADEON_MCLK_CNTL 0x0012
505 # define RADEON_FORCEON_MCLKA (1 << 16)
506 # define RADEON_FORCEON_MCLKB (1 << 17)
507 # define RADEON_FORCEON_YCLKA (1 << 18)
508 # define RADEON_FORCEON_YCLKB (1 << 19)
509 # define RADEON_FORCEON_MC (1 << 20)
510 # define RADEON_FORCEON_AIC (1 << 21)
511
512 #define RADEON_PP_BORDER_COLOR_0 0x1d40
513 #define RADEON_PP_BORDER_COLOR_1 0x1d44
514 #define RADEON_PP_BORDER_COLOR_2 0x1d48
515 #define RADEON_PP_CNTL 0x1c38
516 # define RADEON_SCISSOR_ENABLE (1 << 1)
517 #define RADEON_PP_LUM_MATRIX 0x1d00
518 #define RADEON_PP_MISC 0x1c14
519 #define RADEON_PP_ROT_MATRIX_0 0x1d58
520 #define RADEON_PP_TXFILTER_0 0x1c54
521 #define RADEON_PP_TXOFFSET_0 0x1c5c
522 #define RADEON_PP_TXFILTER_1 0x1c6c
523 #define RADEON_PP_TXFILTER_2 0x1c84
524
525 #define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
526 # define RADEON_RB2D_DC_FLUSH (3 << 0)
527 # define RADEON_RB2D_DC_FREE (3 << 2)
528 # define RADEON_RB2D_DC_FLUSH_ALL 0xf
529 # define RADEON_RB2D_DC_BUSY (1 << 31)
530 #define RADEON_RB3D_CNTL 0x1c3c
531 # define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
532 # define RADEON_PLANE_MASK_ENABLE (1 << 1)
533 # define RADEON_DITHER_ENABLE (1 << 2)
534 # define RADEON_ROUND_ENABLE (1 << 3)
535 # define RADEON_SCALE_DITHER_ENABLE (1 << 4)
536 # define RADEON_DITHER_INIT (1 << 5)
537 # define RADEON_ROP_ENABLE (1 << 6)
538 # define RADEON_STENCIL_ENABLE (1 << 7)
539 # define RADEON_Z_ENABLE (1 << 8)
540 # define RADEON_ZBLOCK16 (1 << 15)
541 #define RADEON_RB3D_DEPTHOFFSET 0x1c24
542 #define RADEON_RB3D_DEPTHCLEARVALUE 0x3230
543 #define RADEON_RB3D_DEPTHPITCH 0x1c28
544 #define RADEON_RB3D_PLANEMASK 0x1d84
545 #define RADEON_RB3D_STENCILREFMASK 0x1d7c
546 #define RADEON_RB3D_ZCACHE_MODE 0x3250
547 #define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254
548 # define RADEON_RB3D_ZC_FLUSH (1 << 0)
549 # define RADEON_RB3D_ZC_FREE (1 << 2)
550 # define RADEON_RB3D_ZC_FLUSH_ALL 0x5
551 # define RADEON_RB3D_ZC_BUSY (1 << 31)
552 #define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
553 # define RADEON_RB3D_DC_FLUSH (3 << 0)
554 # define RADEON_RB3D_DC_FREE (3 << 2)
555 # define RADEON_RB3D_DC_FLUSH_ALL 0xf
556 # define RADEON_RB3D_DC_BUSY (1 << 31)
557 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
558 # define RADEON_Z_TEST_MASK (7 << 4)
559 # define RADEON_Z_TEST_ALWAYS (7 << 4)
560 # define RADEON_Z_HIERARCHY_ENABLE (1 << 8)
561 # define RADEON_STENCIL_TEST_ALWAYS (7 << 12)
562 # define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)
563 # define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)
564 # define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)
565 # define RADEON_Z_COMPRESSION_ENABLE (1 << 28)
566 # define RADEON_FORCE_Z_DIRTY (1 << 29)
567 # define RADEON_Z_WRITE_ENABLE (1 << 30)
568 # define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)
569 #define RADEON_RBBM_SOFT_RESET 0x00f0
570 # define RADEON_SOFT_RESET_CP (1 << 0)
571 # define RADEON_SOFT_RESET_HI (1 << 1)
572 # define RADEON_SOFT_RESET_SE (1 << 2)
573 # define RADEON_SOFT_RESET_RE (1 << 3)
574 # define RADEON_SOFT_RESET_PP (1 << 4)
575 # define RADEON_SOFT_RESET_E2 (1 << 5)
576 # define RADEON_SOFT_RESET_RB (1 << 6)
577 # define RADEON_SOFT_RESET_HDP (1 << 7)
578 #define RADEON_RBBM_STATUS 0x0e40
579 # define RADEON_RBBM_FIFOCNT_MASK 0x007f
580 # define RADEON_RBBM_ACTIVE (1 << 31)
581 #define RADEON_RE_LINE_PATTERN 0x1cd0
582 #define RADEON_RE_MISC 0x26c4
583 #define RADEON_RE_TOP_LEFT 0x26c0
584 #define RADEON_RE_WIDTH_HEIGHT 0x1c44
585 #define RADEON_RE_STIPPLE_ADDR 0x1cc8
586 #define RADEON_RE_STIPPLE_DATA 0x1ccc
587
588 #define RADEON_SCISSOR_TL_0 0x1cd8
589 #define RADEON_SCISSOR_BR_0 0x1cdc
590 #define RADEON_SCISSOR_TL_1 0x1ce0
591 #define RADEON_SCISSOR_BR_1 0x1ce4
592 #define RADEON_SCISSOR_TL_2 0x1ce8
593 #define RADEON_SCISSOR_BR_2 0x1cec
594 #define RADEON_SE_COORD_FMT 0x1c50
595 #define RADEON_SE_CNTL 0x1c4c
596 # define RADEON_FFACE_CULL_CW (0 << 0)
597 # define RADEON_BFACE_SOLID (3 << 1)
598 # define RADEON_FFACE_SOLID (3 << 3)
599 # define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)
600 # define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)
601 # define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)
602 # define RADEON_ALPHA_SHADE_FLAT (1 << 10)
603 # define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)
604 # define RADEON_SPECULAR_SHADE_FLAT (1 << 12)
605 # define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)
606 # define RADEON_FOG_SHADE_FLAT (1 << 14)
607 # define RADEON_FOG_SHADE_GOURAUD (2 << 14)
608 # define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)
609 # define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)
610 # define RADEON_VTX_PIX_CENTER_OGL (1 << 27)
611 # define RADEON_ROUND_MODE_TRUNC (0 << 28)
612 # define RADEON_ROUND_PREC_8TH_PIX (1 << 30)
613 #define RADEON_SE_CNTL_STATUS 0x2140
614 #define RADEON_SE_LINE_WIDTH 0x1db8
615 #define RADEON_SE_VPORT_XSCALE 0x1d98
616 #define RADEON_SE_ZBIAS_FACTOR 0x1db0
617 #define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210
618 #define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254
619 #define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200
620 # define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16
621 # define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28
622 #define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204
623 #define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208
624 # define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16
625 #define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C
626 #define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8
627 #define RADEON_SURFACE_ACCESS_CLR 0x0bfc
628 #define RADEON_SURFACE_CNTL 0x0b00
629 # define RADEON_SURF_TRANSLATION_DIS (1 << 8)
630 # define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)
631 # define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)
632 # define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)
633 # define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)
634 # define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)
635 # define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)
636 # define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)
637 # define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)
638 #define RADEON_SURFACE0_INFO 0x0b0c
639 # define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)
640 # define RADEON_SURF_TILE_MODE_MASK (3 << 16)
641 # define RADEON_SURF_TILE_MODE_MACRO (0 << 16)
642 # define RADEON_SURF_TILE_MODE_MICRO (1 << 16)
643 # define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)
644 # define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)
645 #define RADEON_SURFACE0_LOWER_BOUND 0x0b04
646 #define RADEON_SURFACE0_UPPER_BOUND 0x0b08
647 # define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)
648 #define RADEON_SURFACE1_INFO 0x0b1c
649 #define RADEON_SURFACE1_LOWER_BOUND 0x0b14
650 #define RADEON_SURFACE1_UPPER_BOUND 0x0b18
651 #define RADEON_SURFACE2_INFO 0x0b2c
652 #define RADEON_SURFACE2_LOWER_BOUND 0x0b24
653 #define RADEON_SURFACE2_UPPER_BOUND 0x0b28
654 #define RADEON_SURFACE3_INFO 0x0b3c
655 #define RADEON_SURFACE3_LOWER_BOUND 0x0b34
656 #define RADEON_SURFACE3_UPPER_BOUND 0x0b38
657 #define RADEON_SURFACE4_INFO 0x0b4c
658 #define RADEON_SURFACE4_LOWER_BOUND 0x0b44
659 #define RADEON_SURFACE4_UPPER_BOUND 0x0b48
660 #define RADEON_SURFACE5_INFO 0x0b5c
661 #define RADEON_SURFACE5_LOWER_BOUND 0x0b54
662 #define RADEON_SURFACE5_UPPER_BOUND 0x0b58
663 #define RADEON_SURFACE6_INFO 0x0b6c
664 #define RADEON_SURFACE6_LOWER_BOUND 0x0b64
665 #define RADEON_SURFACE6_UPPER_BOUND 0x0b68
666 #define RADEON_SURFACE7_INFO 0x0b7c
667 #define RADEON_SURFACE7_LOWER_BOUND 0x0b74
668 #define RADEON_SURFACE7_UPPER_BOUND 0x0b78
669 #define RADEON_SW_SEMAPHORE 0x013c
670
671 #define RADEON_WAIT_UNTIL 0x1720
672 # define RADEON_WAIT_CRTC_PFLIP (1 << 0)
673 # define RADEON_WAIT_2D_IDLE (1 << 14)
674 # define RADEON_WAIT_3D_IDLE (1 << 15)
675 # define RADEON_WAIT_2D_IDLECLEAN (1 << 16)
676 # define RADEON_WAIT_3D_IDLECLEAN (1 << 17)
677 # define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)
678
679 #define RADEON_RB3D_ZMASKOFFSET 0x3234
680 #define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
681 # define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)
682 # define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)
683
684 /* CP registers */
685 #define RADEON_CP_ME_RAM_ADDR 0x07d4
686 #define RADEON_CP_ME_RAM_RADDR 0x07d8
687 #define RADEON_CP_ME_RAM_DATAH 0x07dc
688 #define RADEON_CP_ME_RAM_DATAL 0x07e0
689
690 #define RADEON_CP_RB_BASE 0x0700
691 #define RADEON_CP_RB_CNTL 0x0704
692 # define RADEON_BUF_SWAP_32BIT (2 << 16)
693 # define RADEON_RB_NO_UPDATE (1 << 27)
694 #define RADEON_CP_RB_RPTR_ADDR 0x070c
695 #define RADEON_CP_RB_RPTR 0x0710
696 #define RADEON_CP_RB_WPTR 0x0714
697
698 #define RADEON_CP_RB_WPTR_DELAY 0x0718
699 # define RADEON_PRE_WRITE_TIMER_SHIFT 0
700 # define RADEON_PRE_WRITE_LIMIT_SHIFT 23
701
702 #define RADEON_CP_IB_BASE 0x0738
703
704 #define RADEON_CP_CSQ_CNTL 0x0740
705 # define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)
706 # define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)
707 # define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)
708 # define RADEON_CSQ_PRIBM_INDDIS (2 << 28)
709 # define RADEON_CSQ_PRIPIO_INDBM (3 << 28)
710 # define RADEON_CSQ_PRIBM_INDBM (4 << 28)
711 # define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)
712
713 #define RADEON_AIC_CNTL 0x01d0
714 # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
715 #define RADEON_AIC_STAT 0x01d4
716 #define RADEON_AIC_PT_BASE 0x01d8
717 #define RADEON_AIC_LO_ADDR 0x01dc
718 #define RADEON_AIC_HI_ADDR 0x01e0
719 #define RADEON_AIC_TLB_ADDR 0x01e4
720 #define RADEON_AIC_TLB_DATA 0x01e8
721
722 /* CP command packets */
723 #define RADEON_CP_PACKET0 0x00000000
724 # define RADEON_ONE_REG_WR (1 << 15)
725 #define RADEON_CP_PACKET1 0x40000000
726 #define RADEON_CP_PACKET2 0x80000000
727 #define RADEON_CP_PACKET3 0xC0000000
728 # define RADEON_CP_NOP 0x00001000
729 # define RADEON_CP_NEXT_CHAR 0x00001900
730 # define RADEON_CP_PLY_NEXTSCAN 0x00001D00
731 # define RADEON_CP_SET_SCISSORS 0x00001E00
732 /* GEN_INDX_PRIM is unsupported starting with R300 */
733 # define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300
734 # define RADEON_WAIT_FOR_IDLE 0x00002600
735 # define RADEON_3D_DRAW_VBUF 0x00002800
736 # define RADEON_3D_DRAW_IMMD 0x00002900
737 # define RADEON_3D_DRAW_INDX 0x00002A00
738 # define RADEON_CP_LOAD_PALETTE 0x00002C00
739 # define RADEON_3D_LOAD_VBPNTR 0x00002F00
740 # define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000
741 # define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100
742 # define RADEON_3D_CLEAR_ZMASK 0x00003200
743 # define RADEON_CP_INDX_BUFFER 0x00003300
744 # define RADEON_CP_3D_DRAW_VBUF_2 0x00003400
745 # define RADEON_CP_3D_DRAW_IMMD_2 0x00003500
746 # define RADEON_CP_3D_DRAW_INDX_2 0x00003600
747 # define RADEON_3D_CLEAR_HIZ 0x00003700
748 # define RADEON_CP_3D_CLEAR_CMASK 0x00003802
749 # define RADEON_CNTL_HOSTDATA_BLT 0x00009400
750 # define RADEON_CNTL_PAINT_MULTI 0x00009A00
751 # define RADEON_CNTL_BITBLT_MULTI 0x00009B00
752 # define RADEON_CNTL_SET_SCISSORS 0xC0001E00
753
754 #define RADEON_CP_PACKET_MASK 0xC0000000
755 #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000
756 #define RADEON_CP_PACKET0_REG_MASK 0x000007ff
757 #define RADEON_CP_PACKET1_REG0_MASK 0x000007ff
758 #define RADEON_CP_PACKET1_REG1_MASK 0x003ff800
759
760 #define RADEON_VTX_Z_PRESENT (1 << 31)
761 #define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)
762
763 #define RADEON_PRIM_TYPE_NONE (0 << 0)
764 #define RADEON_PRIM_TYPE_POINT (1 << 0)
765 #define RADEON_PRIM_TYPE_LINE (2 << 0)
766 #define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)
767 #define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)
768 #define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)
769 #define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)
770 #define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)
771 #define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)
772 #define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)
773 #define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)
774 #define RADEON_PRIM_TYPE_MASK 0xf
775 #define RADEON_PRIM_WALK_IND (1 << 4)
776 #define RADEON_PRIM_WALK_LIST (2 << 4)
777 #define RADEON_PRIM_WALK_RING (3 << 4)
778 #define RADEON_COLOR_ORDER_BGRA (0 << 6)
779 #define RADEON_COLOR_ORDER_RGBA (1 << 6)
780 #define RADEON_MAOS_ENABLE (1 << 7)
781 #define RADEON_VTX_FMT_R128_MODE (0 << 8)
782 #define RADEON_VTX_FMT_RADEON_MODE (1 << 8)
783 #define RADEON_NUM_VERTICES_SHIFT 16
784
785 #define RADEON_COLOR_FORMAT_CI8 2
786 #define RADEON_COLOR_FORMAT_ARGB1555 3
787 #define RADEON_COLOR_FORMAT_RGB565 4
788 #define RADEON_COLOR_FORMAT_ARGB8888 6
789 #define RADEON_COLOR_FORMAT_RGB332 7
790 #define RADEON_COLOR_FORMAT_RGB8 9
791 #define RADEON_COLOR_FORMAT_ARGB4444 15
792
793 #define RADEON_TXFORMAT_I8 0
794 #define RADEON_TXFORMAT_AI88 1
795 #define RADEON_TXFORMAT_RGB332 2
796 #define RADEON_TXFORMAT_ARGB1555 3
797 #define RADEON_TXFORMAT_RGB565 4
798 #define RADEON_TXFORMAT_ARGB4444 5
799 #define RADEON_TXFORMAT_ARGB8888 6
800 #define RADEON_TXFORMAT_RGBA8888 7
801 #define RADEON_TXFORMAT_Y8 8
802 #define RADEON_TXFORMAT_VYUY422 10
803 #define RADEON_TXFORMAT_YVYU422 11
804 #define RADEON_TXFORMAT_DXT1 12
805 #define RADEON_TXFORMAT_DXT23 14
806 #define RADEON_TXFORMAT_DXT45 15
807
808 #define R200_PP_TXCBLEND_0 0x2f00
809 #define R200_PP_TXCBLEND_1 0x2f10
810 #define R200_PP_TXCBLEND_2 0x2f20
811 #define R200_PP_TXCBLEND_3 0x2f30
812 #define R200_PP_TXCBLEND_4 0x2f40
813 #define R200_PP_TXCBLEND_5 0x2f50
814 #define R200_PP_TXCBLEND_6 0x2f60
815 #define R200_PP_TXCBLEND_7 0x2f70
816 #define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268
817 #define R200_PP_TFACTOR_0 0x2ee0
818 #define R200_SE_VTX_FMT_0 0x2088
819 #define R200_SE_VAP_CNTL 0x2080
820 #define R200_SE_TCL_MATRIX_SEL_0 0x2230
821 #define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8
822 #define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0
823 #define R200_PP_TXFILTER_5 0x2ca0
824 #define R200_PP_TXFILTER_4 0x2c80
825 #define R200_PP_TXFILTER_3 0x2c60
826 #define R200_PP_TXFILTER_2 0x2c40
827 #define R200_PP_TXFILTER_1 0x2c20
828 #define R200_PP_TXFILTER_0 0x2c00
829 #define R200_PP_TXOFFSET_5 0x2d78
830 #define R200_PP_TXOFFSET_4 0x2d60
831 #define R200_PP_TXOFFSET_3 0x2d48
832 #define R200_PP_TXOFFSET_2 0x2d30
833 #define R200_PP_TXOFFSET_1 0x2d18
834 #define R200_PP_TXOFFSET_0 0x2d00
835
836 #define R200_PP_CUBIC_FACES_0 0x2c18
837 #define R200_PP_CUBIC_FACES_1 0x2c38
838 #define R200_PP_CUBIC_FACES_2 0x2c58
839 #define R200_PP_CUBIC_FACES_3 0x2c78
840 #define R200_PP_CUBIC_FACES_4 0x2c98
841 #define R200_PP_CUBIC_FACES_5 0x2cb8
842 #define R200_PP_CUBIC_OFFSET_F1_0 0x2d04
843 #define R200_PP_CUBIC_OFFSET_F2_0 0x2d08
844 #define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c
845 #define R200_PP_CUBIC_OFFSET_F4_0 0x2d10
846 #define R200_PP_CUBIC_OFFSET_F5_0 0x2d14
847 #define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c
848 #define R200_PP_CUBIC_OFFSET_F2_1 0x2d20
849 #define R200_PP_CUBIC_OFFSET_F3_1 0x2d24
850 #define R200_PP_CUBIC_OFFSET_F4_1 0x2d28
851 #define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c
852 #define R200_PP_CUBIC_OFFSET_F1_2 0x2d34
853 #define R200_PP_CUBIC_OFFSET_F2_2 0x2d38
854 #define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c
855 #define R200_PP_CUBIC_OFFSET_F4_2 0x2d40
856 #define R200_PP_CUBIC_OFFSET_F5_2 0x2d44
857 #define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c
858 #define R200_PP_CUBIC_OFFSET_F2_3 0x2d50
859 #define R200_PP_CUBIC_OFFSET_F3_3 0x2d54
860 #define R200_PP_CUBIC_OFFSET_F4_3 0x2d58
861 #define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c
862 #define R200_PP_CUBIC_OFFSET_F1_4 0x2d64
863 #define R200_PP_CUBIC_OFFSET_F2_4 0x2d68
864 #define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c
865 #define R200_PP_CUBIC_OFFSET_F4_4 0x2d70
866 #define R200_PP_CUBIC_OFFSET_F5_4 0x2d74
867 #define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c
868 #define R200_PP_CUBIC_OFFSET_F2_5 0x2d80
869 #define R200_PP_CUBIC_OFFSET_F3_5 0x2d84
870 #define R200_PP_CUBIC_OFFSET_F4_5 0x2d88
871 #define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c
872
873 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
874 #define R200_SE_VTE_CNTL 0x20b0
875 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250
876 #define R200_PP_TAM_DEBUG3 0x2d9c
877 #define R200_PP_CNTL_X 0x2cc4
878 #define R200_SE_VAP_CNTL_STATUS 0x2140
879 #define R200_RE_SCISSOR_TL_0 0x1cd8
880 #define R200_RE_SCISSOR_TL_1 0x1ce0
881 #define R200_RE_SCISSOR_TL_2 0x1ce8
882 #define R200_RB3D_DEPTHXY_OFFSET 0x1d60
883 #define R200_RE_AUX_SCISSOR_CNTL 0x26f0
884 #define R200_SE_VTX_STATE_CNTL 0x2180
885 #define R200_RE_POINTSIZE 0x2648
886 #define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254
887
888 #define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */
889 #define RADEON_PP_TEX_SIZE_1 0x1d0c
890 #define RADEON_PP_TEX_SIZE_2 0x1d14
891
892 #define RADEON_PP_CUBIC_FACES_0 0x1d24
893 #define RADEON_PP_CUBIC_FACES_1 0x1d28
894 #define RADEON_PP_CUBIC_FACES_2 0x1d2c
895 #define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */
896 #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00
897 #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14
898
899 #define RADEON_SE_TCL_STATE_FLUSH 0x2284
900
901 #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001
902 #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000
903 #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012
904 #define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100
905 #define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200
906 #define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001
907 #define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002
908 #define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b
909 #define R200_3D_DRAW_IMMD_2 0xC0003500
910 #define R200_SE_VTX_FMT_1 0x208c
911 #define R200_RE_CNTL 0x1c50
912
913 #define R200_RB3D_BLENDCOLOR 0x3218
914
915 #define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
916
917 #define R200_PP_TRI_PERF 0x2cf8
918
919 #define R200_PP_AFS_0 0x2f80
920 #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */
921
922 #define R200_VAP_PVS_CNTL_1 0x22D0
923
924 /* Constants */
925 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
926
927 #define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0
928 #define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1
929 #define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2
930 #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3
931 #define RADEON_LAST_DISPATCH 1
932
933 #define RADEON_MAX_VB_AGE 0x7fffffff
934 #define RADEON_MAX_VB_VERTS (0xffff)
935
936 #define RADEON_RING_HIGH_MARK 128
937
938 #define RADEON_PCIGART_TABLE_SIZE (32*1024)
939
940 #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
941 #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
942 #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
943 #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
944
945 #define RADEON_WRITE_PLL( addr, val ) \
946 do { \
947 RADEON_WRITE8( RADEON_CLOCK_CNTL_INDEX, \
948 ((addr) & 0x1f) | RADEON_PLL_WR_EN ); \
949 RADEON_WRITE( RADEON_CLOCK_CNTL_DATA, (val) ); \
950 } while (0)
951
952 #define RADEON_WRITE_PCIE( addr, val ) \
953 do { \
954 RADEON_WRITE8( RADEON_PCIE_INDEX, \
955 ((addr) & 0xff)); \
956 RADEON_WRITE( RADEON_PCIE_DATA, (val) ); \
957 } while (0)
958
959 #define CP_PACKET0( reg, n ) \
960 (RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
961 #define CP_PACKET0_TABLE( reg, n ) \
962 (RADEON_CP_PACKET0 | RADEON_ONE_REG_WR | ((n) << 16) | ((reg) >> 2))
963 #define CP_PACKET1( reg0, reg1 ) \
964 (RADEON_CP_PACKET1 | (((reg1) >> 2) << 15) | ((reg0) >> 2))
965 #define CP_PACKET2() \
966 (RADEON_CP_PACKET2)
967 #define CP_PACKET3( pkt, n ) \
968 (RADEON_CP_PACKET3 | (pkt) | ((n) << 16))
969
970 /* ================================================================
971 * Engine control helper macros
972 */
973
974 #define RADEON_WAIT_UNTIL_2D_IDLE() do { \
975 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
976 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
977 RADEON_WAIT_HOST_IDLECLEAN) ); \
978 } while (0)
979
980 #define RADEON_WAIT_UNTIL_3D_IDLE() do { \
981 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
982 OUT_RING( (RADEON_WAIT_3D_IDLECLEAN | \
983 RADEON_WAIT_HOST_IDLECLEAN) ); \
984 } while (0)
985
986 #define RADEON_WAIT_UNTIL_IDLE() do { \
987 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
988 OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
989 RADEON_WAIT_3D_IDLECLEAN | \
990 RADEON_WAIT_HOST_IDLECLEAN) ); \
991 } while (0)
992
993 #define RADEON_WAIT_UNTIL_PAGE_FLIPPED() do { \
994 OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
995 OUT_RING( RADEON_WAIT_CRTC_PFLIP ); \
996 } while (0)
997
998 #define RADEON_FLUSH_CACHE() do { \
999 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
1000 OUT_RING( RADEON_RB3D_DC_FLUSH ); \
1001 } while (0)
1002
1003 #define RADEON_PURGE_CACHE() do { \
1004 OUT_RING( CP_PACKET0( RADEON_RB3D_DSTCACHE_CTLSTAT, 0 ) ); \
1005 OUT_RING( RADEON_RB3D_DC_FLUSH_ALL ); \
1006 } while (0)
1007
1008 #define RADEON_FLUSH_ZCACHE() do { \
1009 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1010 OUT_RING( RADEON_RB3D_ZC_FLUSH ); \
1011 } while (0)
1012
1013 #define RADEON_PURGE_ZCACHE() do { \
1014 OUT_RING( CP_PACKET0( RADEON_RB3D_ZCACHE_CTLSTAT, 0 ) ); \
1015 OUT_RING( RADEON_RB3D_ZC_FLUSH_ALL ); \
1016 } while (0)
1017
1018 /* ================================================================
1019 * Misc helper macros
1020 */
1021
1022 /* Perfbox functionality only.
1023 */
1024 #define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
1025 do { \
1026 if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) { \
1027 u32 head = GET_RING_HEAD( dev_priv ); \
1028 if (head == dev_priv->ring.tail) \
1029 dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE; \
1030 } \
1031 } while (0)
1032
1033 #define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
1034 do { \
1035 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv; \
1036 if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
1037 int __ret = radeon_do_cp_idle( dev_priv ); \
1038 if ( __ret ) return __ret; \
1039 sarea_priv->last_dispatch = 0; \
1040 radeon_freelist_reset( dev ); \
1041 } \
1042 } while (0)
1043
1044 #define RADEON_DISPATCH_AGE( age ) do { \
1045 OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) ); \
1046 OUT_RING( age ); \
1047 } while (0)
1048
1049 #define RADEON_FRAME_AGE( age ) do { \
1050 OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) ); \
1051 OUT_RING( age ); \
1052 } while (0)
1053
1054 #define RADEON_CLEAR_AGE( age ) do { \
1055 OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) ); \
1056 OUT_RING( age ); \
1057 } while (0)
1058
1059 /* ================================================================
1060 * Ring control
1061 */
1062
1063 #define RADEON_VERBOSE 0
1064
1065 #define RING_LOCALS int write, _nr; unsigned int mask; u32 *ring;
1066
1067 #define BEGIN_RING( n ) do { \
1068 if ( RADEON_VERBOSE ) { \
1069 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
1070 n, __FUNCTION__ ); \
1071 } \
1072 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
1073 COMMIT_RING(); \
1074 radeon_wait_ring( dev_priv, (n) * sizeof(u32) ); \
1075 } \
1076 _nr = n; dev_priv->ring.space -= (n) * sizeof(u32); \
1077 ring = dev_priv->ring.start; \
1078 write = dev_priv->ring.tail; \
1079 mask = dev_priv->ring.tail_mask; \
1080 } while (0)
1081
1082 #define ADVANCE_RING() do { \
1083 if ( RADEON_VERBOSE ) { \
1084 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
1085 write, dev_priv->ring.tail ); \
1086 } \
1087 if (((dev_priv->ring.tail + _nr) & mask) != write) { \
1088 DRM_ERROR( \
1089 "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n", \
1090 ((dev_priv->ring.tail + _nr) & mask), \
1091 write, __LINE__); \
1092 } else \
1093 dev_priv->ring.tail = write; \
1094 } while (0)
1095
1096 #define COMMIT_RING() do { \
1097 /* Flush writes to ring */ \
1098 DRM_MEMORYBARRIER(); \
1099 GET_RING_HEAD( dev_priv ); \
1100 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \
1101 /* read from PCI bus to ensure correct posting */ \
1102 RADEON_READ( RADEON_CP_RB_RPTR ); \
1103 } while (0)
1104
1105 #define OUT_RING( x ) do { \
1106 if ( RADEON_VERBOSE ) { \
1107 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
1108 (unsigned int)(x), write ); \
1109 } \
1110 ring[write++] = (x); \
1111 write &= mask; \
1112 } while (0)
1113
1114 #define OUT_RING_REG( reg, val ) do { \
1115 OUT_RING( CP_PACKET0( reg, 0 ) ); \
1116 OUT_RING( val ); \
1117 } while (0)
1118
1119 #define OUT_RING_TABLE( tab, sz ) do { \
1120 int _size = (sz); \
1121 int *_tab = (int *)(tab); \
1122 \
1123 if (write + _size > mask) { \
1124 int _i = (mask+1) - write; \
1125 _size -= _i; \
1126 while (_i > 0 ) { \
1127 *(int *)(ring + write) = *_tab++; \
1128 write++; \
1129 _i--; \
1130 } \
1131 write = 0; \
1132 _tab += _i; \
1133 } \
1134 while (_size > 0) { \
1135 *(ring + write) = *_tab++; \
1136 write++; \
1137 _size--; \
1138 } \
1139 write &= mask; \
1140 } while (0)
1141
1142 #endif /* __RADEON_DRV_H__ */
Linux kernel - Deliverables
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