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drm: move ioctl flags to a bit field of flags
[deliverable/linux.git] / drivers / char / drm / savage_bci.c
1 /* savage_bci.c -- BCI support for Savage
2 *
3 * Copyright 2004 Felix Kuehling
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sub license,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
22 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #include "drmP.h"
26 #include "savage_drm.h"
27 #include "savage_drv.h"
28
29 /* Need a long timeout for shadow status updates can take a while
30 * and so can waiting for events when the queue is full. */
31 #define SAVAGE_DEFAULT_USEC_TIMEOUT 1000000 /* 1s */
32 #define SAVAGE_EVENT_USEC_TIMEOUT 5000000 /* 5s */
33 #define SAVAGE_FREELIST_DEBUG 0
34
35 static int
36 savage_bci_wait_fifo_shadow(drm_savage_private_t * dev_priv, unsigned int n)
37 {
38 uint32_t mask = dev_priv->status_used_mask;
39 uint32_t threshold = dev_priv->bci_threshold_hi;
40 uint32_t status;
41 int i;
42
43 #if SAVAGE_BCI_DEBUG
44 if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold)
45 DRM_ERROR("Trying to emit %d words "
46 "(more than guaranteed space in COB)\n", n);
47 #endif
48
49 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
50 DRM_MEMORYBARRIER();
51 status = dev_priv->status_ptr[0];
52 if ((status & mask) < threshold)
53 return 0;
54 DRM_UDELAY(1);
55 }
56
57 #if SAVAGE_BCI_DEBUG
58 DRM_ERROR("failed!\n");
59 DRM_INFO(" status=0x%08x, threshold=0x%08x\n", status, threshold);
60 #endif
61 return DRM_ERR(EBUSY);
62 }
63
64 static int
65 savage_bci_wait_fifo_s3d(drm_savage_private_t * dev_priv, unsigned int n)
66 {
67 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n;
68 uint32_t status;
69 int i;
70
71 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
72 status = SAVAGE_READ(SAVAGE_STATUS_WORD0);
73 if ((status & SAVAGE_FIFO_USED_MASK_S3D) <= maxUsed)
74 return 0;
75 DRM_UDELAY(1);
76 }
77
78 #if SAVAGE_BCI_DEBUG
79 DRM_ERROR("failed!\n");
80 DRM_INFO(" status=0x%08x\n", status);
81 #endif
82 return DRM_ERR(EBUSY);
83 }
84
85 static int
86 savage_bci_wait_fifo_s4(drm_savage_private_t * dev_priv, unsigned int n)
87 {
88 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n;
89 uint32_t status;
90 int i;
91
92 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
93 status = SAVAGE_READ(SAVAGE_ALT_STATUS_WORD0);
94 if ((status & SAVAGE_FIFO_USED_MASK_S4) <= maxUsed)
95 return 0;
96 DRM_UDELAY(1);
97 }
98
99 #if SAVAGE_BCI_DEBUG
100 DRM_ERROR("failed!\n");
101 DRM_INFO(" status=0x%08x\n", status);
102 #endif
103 return DRM_ERR(EBUSY);
104 }
105
106 /*
107 * Waiting for events.
108 *
109 * The BIOSresets the event tag to 0 on mode changes. Therefore we
110 * never emit 0 to the event tag. If we find a 0 event tag we know the
111 * BIOS stomped on it and return success assuming that the BIOS waited
112 * for engine idle.
113 *
114 * Note: if the Xserver uses the event tag it has to follow the same
115 * rule. Otherwise there may be glitches every 2^16 events.
116 */
117 static int
118 savage_bci_wait_event_shadow(drm_savage_private_t * dev_priv, uint16_t e)
119 {
120 uint32_t status;
121 int i;
122
123 for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) {
124 DRM_MEMORYBARRIER();
125 status = dev_priv->status_ptr[1];
126 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff ||
127 (status & 0xffff) == 0)
128 return 0;
129 DRM_UDELAY(1);
130 }
131
132 #if SAVAGE_BCI_DEBUG
133 DRM_ERROR("failed!\n");
134 DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e);
135 #endif
136
137 return DRM_ERR(EBUSY);
138 }
139
140 static int
141 savage_bci_wait_event_reg(drm_savage_private_t * dev_priv, uint16_t e)
142 {
143 uint32_t status;
144 int i;
145
146 for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) {
147 status = SAVAGE_READ(SAVAGE_STATUS_WORD1);
148 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff ||
149 (status & 0xffff) == 0)
150 return 0;
151 DRM_UDELAY(1);
152 }
153
154 #if SAVAGE_BCI_DEBUG
155 DRM_ERROR("failed!\n");
156 DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e);
157 #endif
158
159 return DRM_ERR(EBUSY);
160 }
161
162 uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv,
163 unsigned int flags)
164 {
165 uint16_t count;
166 BCI_LOCALS;
167
168 if (dev_priv->status_ptr) {
169 /* coordinate with Xserver */
170 count = dev_priv->status_ptr[1023];
171 if (count < dev_priv->event_counter)
172 dev_priv->event_wrap++;
173 } else {
174 count = dev_priv->event_counter;
175 }
176 count = (count + 1) & 0xffff;
177 if (count == 0) {
178 count++; /* See the comment above savage_wait_event_*. */
179 dev_priv->event_wrap++;
180 }
181 dev_priv->event_counter = count;
182 if (dev_priv->status_ptr)
183 dev_priv->status_ptr[1023] = (uint32_t) count;
184
185 if ((flags & (SAVAGE_WAIT_2D | SAVAGE_WAIT_3D))) {
186 unsigned int wait_cmd = BCI_CMD_WAIT;
187 if ((flags & SAVAGE_WAIT_2D))
188 wait_cmd |= BCI_CMD_WAIT_2D;
189 if ((flags & SAVAGE_WAIT_3D))
190 wait_cmd |= BCI_CMD_WAIT_3D;
191 BEGIN_BCI(2);
192 BCI_WRITE(wait_cmd);
193 } else {
194 BEGIN_BCI(1);
195 }
196 BCI_WRITE(BCI_CMD_UPDATE_EVENT_TAG | (uint32_t) count);
197
198 return count;
199 }
200
201 /*
202 * Freelist management
203 */
204 static int savage_freelist_init(drm_device_t * dev)
205 {
206 drm_savage_private_t *dev_priv = dev->dev_private;
207 drm_device_dma_t *dma = dev->dma;
208 drm_buf_t *buf;
209 drm_savage_buf_priv_t *entry;
210 int i;
211 DRM_DEBUG("count=%d\n", dma->buf_count);
212
213 dev_priv->head.next = &dev_priv->tail;
214 dev_priv->head.prev = NULL;
215 dev_priv->head.buf = NULL;
216
217 dev_priv->tail.next = NULL;
218 dev_priv->tail.prev = &dev_priv->head;
219 dev_priv->tail.buf = NULL;
220
221 for (i = 0; i < dma->buf_count; i++) {
222 buf = dma->buflist[i];
223 entry = buf->dev_private;
224
225 SET_AGE(&entry->age, 0, 0);
226 entry->buf = buf;
227
228 entry->next = dev_priv->head.next;
229 entry->prev = &dev_priv->head;
230 dev_priv->head.next->prev = entry;
231 dev_priv->head.next = entry;
232 }
233
234 return 0;
235 }
236
237 static drm_buf_t *savage_freelist_get(drm_device_t * dev)
238 {
239 drm_savage_private_t *dev_priv = dev->dev_private;
240 drm_savage_buf_priv_t *tail = dev_priv->tail.prev;
241 uint16_t event;
242 unsigned int wrap;
243 DRM_DEBUG("\n");
244
245 UPDATE_EVENT_COUNTER();
246 if (dev_priv->status_ptr)
247 event = dev_priv->status_ptr[1] & 0xffff;
248 else
249 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
250 wrap = dev_priv->event_wrap;
251 if (event > dev_priv->event_counter)
252 wrap--; /* hardware hasn't passed the last wrap yet */
253
254 DRM_DEBUG(" tail=0x%04x %d\n", tail->age.event, tail->age.wrap);
255 DRM_DEBUG(" head=0x%04x %d\n", event, wrap);
256
257 if (tail->buf && (TEST_AGE(&tail->age, event, wrap) || event == 0)) {
258 drm_savage_buf_priv_t *next = tail->next;
259 drm_savage_buf_priv_t *prev = tail->prev;
260 prev->next = next;
261 next->prev = prev;
262 tail->next = tail->prev = NULL;
263 return tail->buf;
264 }
265
266 DRM_DEBUG("returning NULL, tail->buf=%p!\n", tail->buf);
267 return NULL;
268 }
269
270 void savage_freelist_put(drm_device_t * dev, drm_buf_t * buf)
271 {
272 drm_savage_private_t *dev_priv = dev->dev_private;
273 drm_savage_buf_priv_t *entry = buf->dev_private, *prev, *next;
274
275 DRM_DEBUG("age=0x%04x wrap=%d\n", entry->age.event, entry->age.wrap);
276
277 if (entry->next != NULL || entry->prev != NULL) {
278 DRM_ERROR("entry already on freelist.\n");
279 return;
280 }
281
282 prev = &dev_priv->head;
283 next = prev->next;
284 prev->next = entry;
285 next->prev = entry;
286 entry->prev = prev;
287 entry->next = next;
288 }
289
290 /*
291 * Command DMA
292 */
293 static int savage_dma_init(drm_savage_private_t * dev_priv)
294 {
295 unsigned int i;
296
297 dev_priv->nr_dma_pages = dev_priv->cmd_dma->size /
298 (SAVAGE_DMA_PAGE_SIZE * 4);
299 dev_priv->dma_pages = drm_alloc(sizeof(drm_savage_dma_page_t) *
300 dev_priv->nr_dma_pages, DRM_MEM_DRIVER);
301 if (dev_priv->dma_pages == NULL)
302 return DRM_ERR(ENOMEM);
303
304 for (i = 0; i < dev_priv->nr_dma_pages; ++i) {
305 SET_AGE(&dev_priv->dma_pages[i].age, 0, 0);
306 dev_priv->dma_pages[i].used = 0;
307 dev_priv->dma_pages[i].flushed = 0;
308 }
309 SET_AGE(&dev_priv->last_dma_age, 0, 0);
310
311 dev_priv->first_dma_page = 0;
312 dev_priv->current_dma_page = 0;
313
314 return 0;
315 }
316
317 void savage_dma_reset(drm_savage_private_t * dev_priv)
318 {
319 uint16_t event;
320 unsigned int wrap, i;
321 event = savage_bci_emit_event(dev_priv, 0);
322 wrap = dev_priv->event_wrap;
323 for (i = 0; i < dev_priv->nr_dma_pages; ++i) {
324 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap);
325 dev_priv->dma_pages[i].used = 0;
326 dev_priv->dma_pages[i].flushed = 0;
327 }
328 SET_AGE(&dev_priv->last_dma_age, event, wrap);
329 dev_priv->first_dma_page = dev_priv->current_dma_page = 0;
330 }
331
332 void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page)
333 {
334 uint16_t event;
335 unsigned int wrap;
336
337 /* Faked DMA buffer pages don't age. */
338 if (dev_priv->cmd_dma == &dev_priv->fake_dma)
339 return;
340
341 UPDATE_EVENT_COUNTER();
342 if (dev_priv->status_ptr)
343 event = dev_priv->status_ptr[1] & 0xffff;
344 else
345 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
346 wrap = dev_priv->event_wrap;
347 if (event > dev_priv->event_counter)
348 wrap--; /* hardware hasn't passed the last wrap yet */
349
350 if (dev_priv->dma_pages[page].age.wrap > wrap ||
351 (dev_priv->dma_pages[page].age.wrap == wrap &&
352 dev_priv->dma_pages[page].age.event > event)) {
353 if (dev_priv->wait_evnt(dev_priv,
354 dev_priv->dma_pages[page].age.event)
355 < 0)
356 DRM_ERROR("wait_evnt failed!\n");
357 }
358 }
359
360 uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, unsigned int n)
361 {
362 unsigned int cur = dev_priv->current_dma_page;
363 unsigned int rest = SAVAGE_DMA_PAGE_SIZE -
364 dev_priv->dma_pages[cur].used;
365 unsigned int nr_pages = (n - rest + SAVAGE_DMA_PAGE_SIZE - 1) /
366 SAVAGE_DMA_PAGE_SIZE;
367 uint32_t *dma_ptr;
368 unsigned int i;
369
370 DRM_DEBUG("cur=%u, cur->used=%u, n=%u, rest=%u, nr_pages=%u\n",
371 cur, dev_priv->dma_pages[cur].used, n, rest, nr_pages);
372
373 if (cur + nr_pages < dev_priv->nr_dma_pages) {
374 dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle +
375 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used;
376 if (n < rest)
377 rest = n;
378 dev_priv->dma_pages[cur].used += rest;
379 n -= rest;
380 cur++;
381 } else {
382 dev_priv->dma_flush(dev_priv);
383 nr_pages =
384 (n + SAVAGE_DMA_PAGE_SIZE - 1) / SAVAGE_DMA_PAGE_SIZE;
385 for (i = cur; i < dev_priv->nr_dma_pages; ++i) {
386 dev_priv->dma_pages[i].age = dev_priv->last_dma_age;
387 dev_priv->dma_pages[i].used = 0;
388 dev_priv->dma_pages[i].flushed = 0;
389 }
390 dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle;
391 dev_priv->first_dma_page = cur = 0;
392 }
393 for (i = cur; nr_pages > 0; ++i, --nr_pages) {
394 #if SAVAGE_DMA_DEBUG
395 if (dev_priv->dma_pages[i].used) {
396 DRM_ERROR("unflushed page %u: used=%u\n",
397 i, dev_priv->dma_pages[i].used);
398 }
399 #endif
400 if (n > SAVAGE_DMA_PAGE_SIZE)
401 dev_priv->dma_pages[i].used = SAVAGE_DMA_PAGE_SIZE;
402 else
403 dev_priv->dma_pages[i].used = n;
404 n -= SAVAGE_DMA_PAGE_SIZE;
405 }
406 dev_priv->current_dma_page = --i;
407
408 DRM_DEBUG("cur=%u, cur->used=%u, n=%u\n",
409 i, dev_priv->dma_pages[i].used, n);
410
411 savage_dma_wait(dev_priv, dev_priv->current_dma_page);
412
413 return dma_ptr;
414 }
415
416 static void savage_dma_flush(drm_savage_private_t * dev_priv)
417 {
418 unsigned int first = dev_priv->first_dma_page;
419 unsigned int cur = dev_priv->current_dma_page;
420 uint16_t event;
421 unsigned int wrap, pad, align, len, i;
422 unsigned long phys_addr;
423 BCI_LOCALS;
424
425 if (first == cur &&
426 dev_priv->dma_pages[cur].used == dev_priv->dma_pages[cur].flushed)
427 return;
428
429 /* pad length to multiples of 2 entries
430 * align start of next DMA block to multiles of 8 entries */
431 pad = -dev_priv->dma_pages[cur].used & 1;
432 align = -(dev_priv->dma_pages[cur].used + pad) & 7;
433
434 DRM_DEBUG("first=%u, cur=%u, first->flushed=%u, cur->used=%u, "
435 "pad=%u, align=%u\n",
436 first, cur, dev_priv->dma_pages[first].flushed,
437 dev_priv->dma_pages[cur].used, pad, align);
438
439 /* pad with noops */
440 if (pad) {
441 uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle +
442 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used;
443 dev_priv->dma_pages[cur].used += pad;
444 while (pad != 0) {
445 *dma_ptr++ = BCI_CMD_WAIT;
446 pad--;
447 }
448 }
449
450 DRM_MEMORYBARRIER();
451
452 /* do flush ... */
453 phys_addr = dev_priv->cmd_dma->offset +
454 (first * SAVAGE_DMA_PAGE_SIZE +
455 dev_priv->dma_pages[first].flushed) * 4;
456 len = (cur - first) * SAVAGE_DMA_PAGE_SIZE +
457 dev_priv->dma_pages[cur].used - dev_priv->dma_pages[first].flushed;
458
459 DRM_DEBUG("phys_addr=%lx, len=%u\n",
460 phys_addr | dev_priv->dma_type, len);
461
462 BEGIN_BCI(3);
463 BCI_SET_REGISTERS(SAVAGE_DMABUFADDR, 1);
464 BCI_WRITE(phys_addr | dev_priv->dma_type);
465 BCI_DMA(len);
466
467 /* fix alignment of the start of the next block */
468 dev_priv->dma_pages[cur].used += align;
469
470 /* age DMA pages */
471 event = savage_bci_emit_event(dev_priv, 0);
472 wrap = dev_priv->event_wrap;
473 for (i = first; i < cur; ++i) {
474 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap);
475 dev_priv->dma_pages[i].used = 0;
476 dev_priv->dma_pages[i].flushed = 0;
477 }
478 /* age the current page only when it's full */
479 if (dev_priv->dma_pages[cur].used == SAVAGE_DMA_PAGE_SIZE) {
480 SET_AGE(&dev_priv->dma_pages[cur].age, event, wrap);
481 dev_priv->dma_pages[cur].used = 0;
482 dev_priv->dma_pages[cur].flushed = 0;
483 /* advance to next page */
484 cur++;
485 if (cur == dev_priv->nr_dma_pages)
486 cur = 0;
487 dev_priv->first_dma_page = dev_priv->current_dma_page = cur;
488 } else {
489 dev_priv->first_dma_page = cur;
490 dev_priv->dma_pages[cur].flushed = dev_priv->dma_pages[i].used;
491 }
492 SET_AGE(&dev_priv->last_dma_age, event, wrap);
493
494 DRM_DEBUG("first=cur=%u, cur->used=%u, cur->flushed=%u\n", cur,
495 dev_priv->dma_pages[cur].used,
496 dev_priv->dma_pages[cur].flushed);
497 }
498
499 static void savage_fake_dma_flush(drm_savage_private_t * dev_priv)
500 {
501 unsigned int i, j;
502 BCI_LOCALS;
503
504 if (dev_priv->first_dma_page == dev_priv->current_dma_page &&
505 dev_priv->dma_pages[dev_priv->current_dma_page].used == 0)
506 return;
507
508 DRM_DEBUG("first=%u, cur=%u, cur->used=%u\n",
509 dev_priv->first_dma_page, dev_priv->current_dma_page,
510 dev_priv->dma_pages[dev_priv->current_dma_page].used);
511
512 for (i = dev_priv->first_dma_page;
513 i <= dev_priv->current_dma_page && dev_priv->dma_pages[i].used;
514 ++i) {
515 uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle +
516 i * SAVAGE_DMA_PAGE_SIZE;
517 #if SAVAGE_DMA_DEBUG
518 /* Sanity check: all pages except the last one must be full. */
519 if (i < dev_priv->current_dma_page &&
520 dev_priv->dma_pages[i].used != SAVAGE_DMA_PAGE_SIZE) {
521 DRM_ERROR("partial DMA page %u: used=%u",
522 i, dev_priv->dma_pages[i].used);
523 }
524 #endif
525 BEGIN_BCI(dev_priv->dma_pages[i].used);
526 for (j = 0; j < dev_priv->dma_pages[i].used; ++j) {
527 BCI_WRITE(dma_ptr[j]);
528 }
529 dev_priv->dma_pages[i].used = 0;
530 }
531
532 /* reset to first page */
533 dev_priv->first_dma_page = dev_priv->current_dma_page = 0;
534 }
535
536 int savage_driver_load(drm_device_t *dev, unsigned long chipset)
537 {
538 drm_savage_private_t *dev_priv;
539
540 dev_priv = drm_alloc(sizeof(drm_savage_private_t), DRM_MEM_DRIVER);
541 if (dev_priv == NULL)
542 return DRM_ERR(ENOMEM);
543
544 memset(dev_priv, 0, sizeof(drm_savage_private_t));
545 dev->dev_private = (void *)dev_priv;
546
547 dev_priv->chipset = (enum savage_family)chipset;
548
549 return 0;
550 }
551
552
553 /*
554 * Initalize mappings. On Savage4 and SavageIX the alignment
555 * and size of the aperture is not suitable for automatic MTRR setup
556 * in drm_addmap. Therefore we add them manually before the maps are
557 * initialized, and tear them down on last close.
558 */
559 int savage_driver_firstopen(drm_device_t *dev)
560 {
561 drm_savage_private_t *dev_priv = dev->dev_private;
562 unsigned long mmio_base, fb_base, fb_size, aperture_base;
563 /* fb_rsrc and aper_rsrc aren't really used currently, but still exist
564 * in case we decide we need information on the BAR for BSD in the
565 * future.
566 */
567 unsigned int fb_rsrc, aper_rsrc;
568 int ret = 0;
569
570 dev_priv->mtrr[0].handle = -1;
571 dev_priv->mtrr[1].handle = -1;
572 dev_priv->mtrr[2].handle = -1;
573 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
574 fb_rsrc = 0;
575 fb_base = drm_get_resource_start(dev, 0);
576 fb_size = SAVAGE_FB_SIZE_S3;
577 mmio_base = fb_base + SAVAGE_FB_SIZE_S3;
578 aper_rsrc = 0;
579 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
580 /* this should always be true */
581 if (drm_get_resource_len(dev, 0) == 0x08000000) {
582 /* Don't make MMIO write-cobining! We need 3
583 * MTRRs. */
584 dev_priv->mtrr[0].base = fb_base;
585 dev_priv->mtrr[0].size = 0x01000000;
586 dev_priv->mtrr[0].handle =
587 mtrr_add(dev_priv->mtrr[0].base,
588 dev_priv->mtrr[0].size, MTRR_TYPE_WRCOMB,
589 1);
590 dev_priv->mtrr[1].base = fb_base + 0x02000000;
591 dev_priv->mtrr[1].size = 0x02000000;
592 dev_priv->mtrr[1].handle =
593 mtrr_add(dev_priv->mtrr[1].base,
594 dev_priv->mtrr[1].size, MTRR_TYPE_WRCOMB,
595 1);
596 dev_priv->mtrr[2].base = fb_base + 0x04000000;
597 dev_priv->mtrr[2].size = 0x04000000;
598 dev_priv->mtrr[2].handle =
599 mtrr_add(dev_priv->mtrr[2].base,
600 dev_priv->mtrr[2].size, MTRR_TYPE_WRCOMB,
601 1);
602 } else {
603 DRM_ERROR("strange pci_resource_len %08lx\n",
604 drm_get_resource_len(dev, 0));
605 }
606 } else if (dev_priv->chipset != S3_SUPERSAVAGE &&
607 dev_priv->chipset != S3_SAVAGE2000) {
608 mmio_base = drm_get_resource_start(dev, 0);
609 fb_rsrc = 1;
610 fb_base = drm_get_resource_start(dev, 1);
611 fb_size = SAVAGE_FB_SIZE_S4;
612 aper_rsrc = 1;
613 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
614 /* this should always be true */
615 if (drm_get_resource_len(dev, 1) == 0x08000000) {
616 /* Can use one MTRR to cover both fb and
617 * aperture. */
618 dev_priv->mtrr[0].base = fb_base;
619 dev_priv->mtrr[0].size = 0x08000000;
620 dev_priv->mtrr[0].handle =
621 mtrr_add(dev_priv->mtrr[0].base,
622 dev_priv->mtrr[0].size, MTRR_TYPE_WRCOMB,
623 1);
624 } else {
625 DRM_ERROR("strange pci_resource_len %08lx\n",
626 drm_get_resource_len(dev, 1));
627 }
628 } else {
629 mmio_base = drm_get_resource_start(dev, 0);
630 fb_rsrc = 1;
631 fb_base = drm_get_resource_start(dev, 1);
632 fb_size = drm_get_resource_len(dev, 1);
633 aper_rsrc = 2;
634 aperture_base = drm_get_resource_start(dev, 2);
635 /* Automatic MTRR setup will do the right thing. */
636 }
637
638 ret = drm_addmap(dev, mmio_base, SAVAGE_MMIO_SIZE, _DRM_REGISTERS,
639 _DRM_READ_ONLY, &dev_priv->mmio);
640 if (ret)
641 return ret;
642
643 ret = drm_addmap(dev, fb_base, fb_size, _DRM_FRAME_BUFFER,
644 _DRM_WRITE_COMBINING, &dev_priv->fb);
645 if (ret)
646 return ret;
647
648 ret = drm_addmap(dev, aperture_base, SAVAGE_APERTURE_SIZE,
649 _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING,
650 &dev_priv->aperture);
651 if (ret)
652 return ret;
653
654 return ret;
655 }
656
657 /*
658 * Delete MTRRs and free device-private data.
659 */
660 void savage_driver_lastclose(drm_device_t *dev)
661 {
662 drm_savage_private_t *dev_priv = dev->dev_private;
663 int i;
664
665 for (i = 0; i < 3; ++i)
666 if (dev_priv->mtrr[i].handle >= 0)
667 mtrr_del(dev_priv->mtrr[i].handle,
668 dev_priv->mtrr[i].base,
669 dev_priv->mtrr[i].size);
670 }
671
672 int savage_driver_unload(drm_device_t *dev)
673 {
674 drm_savage_private_t *dev_priv = dev->dev_private;
675
676 drm_free(dev_priv, sizeof(drm_savage_private_t), DRM_MEM_DRIVER);
677
678 return 0;
679 }
680
681 static int savage_do_init_bci(drm_device_t * dev, drm_savage_init_t * init)
682 {
683 drm_savage_private_t *dev_priv = dev->dev_private;
684
685 if (init->fb_bpp != 16 && init->fb_bpp != 32) {
686 DRM_ERROR("invalid frame buffer bpp %d!\n", init->fb_bpp);
687 return DRM_ERR(EINVAL);
688 }
689 if (init->depth_bpp != 16 && init->depth_bpp != 32) {
690 DRM_ERROR("invalid depth buffer bpp %d!\n", init->fb_bpp);
691 return DRM_ERR(EINVAL);
692 }
693 if (init->dma_type != SAVAGE_DMA_AGP &&
694 init->dma_type != SAVAGE_DMA_PCI) {
695 DRM_ERROR("invalid dma memory type %d!\n", init->dma_type);
696 return DRM_ERR(EINVAL);
697 }
698
699 dev_priv->cob_size = init->cob_size;
700 dev_priv->bci_threshold_lo = init->bci_threshold_lo;
701 dev_priv->bci_threshold_hi = init->bci_threshold_hi;
702 dev_priv->dma_type = init->dma_type;
703
704 dev_priv->fb_bpp = init->fb_bpp;
705 dev_priv->front_offset = init->front_offset;
706 dev_priv->front_pitch = init->front_pitch;
707 dev_priv->back_offset = init->back_offset;
708 dev_priv->back_pitch = init->back_pitch;
709 dev_priv->depth_bpp = init->depth_bpp;
710 dev_priv->depth_offset = init->depth_offset;
711 dev_priv->depth_pitch = init->depth_pitch;
712
713 dev_priv->texture_offset = init->texture_offset;
714 dev_priv->texture_size = init->texture_size;
715
716 DRM_GETSAREA();
717 if (!dev_priv->sarea) {
718 DRM_ERROR("could not find sarea!\n");
719 savage_do_cleanup_bci(dev);
720 return DRM_ERR(EINVAL);
721 }
722 if (init->status_offset != 0) {
723 dev_priv->status = drm_core_findmap(dev, init->status_offset);
724 if (!dev_priv->status) {
725 DRM_ERROR("could not find shadow status region!\n");
726 savage_do_cleanup_bci(dev);
727 return DRM_ERR(EINVAL);
728 }
729 } else {
730 dev_priv->status = NULL;
731 }
732 if (dev_priv->dma_type == SAVAGE_DMA_AGP && init->buffers_offset) {
733 dev->agp_buffer_map = drm_core_findmap(dev,
734 init->buffers_offset);
735 if (!dev->agp_buffer_map) {
736 DRM_ERROR("could not find DMA buffer region!\n");
737 savage_do_cleanup_bci(dev);
738 return DRM_ERR(EINVAL);
739 }
740 drm_core_ioremap(dev->agp_buffer_map, dev);
741 if (!dev->agp_buffer_map) {
742 DRM_ERROR("failed to ioremap DMA buffer region!\n");
743 savage_do_cleanup_bci(dev);
744 return DRM_ERR(ENOMEM);
745 }
746 }
747 if (init->agp_textures_offset) {
748 dev_priv->agp_textures =
749 drm_core_findmap(dev, init->agp_textures_offset);
750 if (!dev_priv->agp_textures) {
751 DRM_ERROR("could not find agp texture region!\n");
752 savage_do_cleanup_bci(dev);
753 return DRM_ERR(EINVAL);
754 }
755 } else {
756 dev_priv->agp_textures = NULL;
757 }
758
759 if (init->cmd_dma_offset) {
760 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
761 DRM_ERROR("command DMA not supported on "
762 "Savage3D/MX/IX.\n");
763 savage_do_cleanup_bci(dev);
764 return DRM_ERR(EINVAL);
765 }
766 if (dev->dma && dev->dma->buflist) {
767 DRM_ERROR("command and vertex DMA not supported "
768 "at the same time.\n");
769 savage_do_cleanup_bci(dev);
770 return DRM_ERR(EINVAL);
771 }
772 dev_priv->cmd_dma = drm_core_findmap(dev, init->cmd_dma_offset);
773 if (!dev_priv->cmd_dma) {
774 DRM_ERROR("could not find command DMA region!\n");
775 savage_do_cleanup_bci(dev);
776 return DRM_ERR(EINVAL);
777 }
778 if (dev_priv->dma_type == SAVAGE_DMA_AGP) {
779 if (dev_priv->cmd_dma->type != _DRM_AGP) {
780 DRM_ERROR("AGP command DMA region is not a "
781 "_DRM_AGP map!\n");
782 savage_do_cleanup_bci(dev);
783 return DRM_ERR(EINVAL);
784 }
785 drm_core_ioremap(dev_priv->cmd_dma, dev);
786 if (!dev_priv->cmd_dma->handle) {
787 DRM_ERROR("failed to ioremap command "
788 "DMA region!\n");
789 savage_do_cleanup_bci(dev);
790 return DRM_ERR(ENOMEM);
791 }
792 } else if (dev_priv->cmd_dma->type != _DRM_CONSISTENT) {
793 DRM_ERROR("PCI command DMA region is not a "
794 "_DRM_CONSISTENT map!\n");
795 savage_do_cleanup_bci(dev);
796 return DRM_ERR(EINVAL);
797 }
798 } else {
799 dev_priv->cmd_dma = NULL;
800 }
801
802 dev_priv->dma_flush = savage_dma_flush;
803 if (!dev_priv->cmd_dma) {
804 DRM_DEBUG("falling back to faked command DMA.\n");
805 dev_priv->fake_dma.offset = 0;
806 dev_priv->fake_dma.size = SAVAGE_FAKE_DMA_SIZE;
807 dev_priv->fake_dma.type = _DRM_SHM;
808 dev_priv->fake_dma.handle = drm_alloc(SAVAGE_FAKE_DMA_SIZE,
809 DRM_MEM_DRIVER);
810 if (!dev_priv->fake_dma.handle) {
811 DRM_ERROR("could not allocate faked DMA buffer!\n");
812 savage_do_cleanup_bci(dev);
813 return DRM_ERR(ENOMEM);
814 }
815 dev_priv->cmd_dma = &dev_priv->fake_dma;
816 dev_priv->dma_flush = savage_fake_dma_flush;
817 }
818
819 dev_priv->sarea_priv =
820 (drm_savage_sarea_t *) ((uint8_t *) dev_priv->sarea->handle +
821 init->sarea_priv_offset);
822
823 /* setup bitmap descriptors */
824 {
825 unsigned int color_tile_format;
826 unsigned int depth_tile_format;
827 unsigned int front_stride, back_stride, depth_stride;
828 if (dev_priv->chipset <= S3_SAVAGE4) {
829 color_tile_format = dev_priv->fb_bpp == 16 ?
830 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP;
831 depth_tile_format = dev_priv->depth_bpp == 16 ?
832 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP;
833 } else {
834 color_tile_format = SAVAGE_BD_TILE_DEST;
835 depth_tile_format = SAVAGE_BD_TILE_DEST;
836 }
837 front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp / 8);
838 back_stride = dev_priv->back_pitch / (dev_priv->fb_bpp / 8);
839 depth_stride =
840 dev_priv->depth_pitch / (dev_priv->depth_bpp / 8);
841
842 dev_priv->front_bd = front_stride | SAVAGE_BD_BW_DISABLE |
843 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) |
844 (color_tile_format << SAVAGE_BD_TILE_SHIFT);
845
846 dev_priv->back_bd = back_stride | SAVAGE_BD_BW_DISABLE |
847 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) |
848 (color_tile_format << SAVAGE_BD_TILE_SHIFT);
849
850 dev_priv->depth_bd = depth_stride | SAVAGE_BD_BW_DISABLE |
851 (dev_priv->depth_bpp << SAVAGE_BD_BPP_SHIFT) |
852 (depth_tile_format << SAVAGE_BD_TILE_SHIFT);
853 }
854
855 /* setup status and bci ptr */
856 dev_priv->event_counter = 0;
857 dev_priv->event_wrap = 0;
858 dev_priv->bci_ptr = (volatile uint32_t *)
859 ((uint8_t *) dev_priv->mmio->handle + SAVAGE_BCI_OFFSET);
860 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
861 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S3D;
862 } else {
863 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S4;
864 }
865 if (dev_priv->status != NULL) {
866 dev_priv->status_ptr =
867 (volatile uint32_t *)dev_priv->status->handle;
868 dev_priv->wait_fifo = savage_bci_wait_fifo_shadow;
869 dev_priv->wait_evnt = savage_bci_wait_event_shadow;
870 dev_priv->status_ptr[1023] = dev_priv->event_counter;
871 } else {
872 dev_priv->status_ptr = NULL;
873 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
874 dev_priv->wait_fifo = savage_bci_wait_fifo_s3d;
875 } else {
876 dev_priv->wait_fifo = savage_bci_wait_fifo_s4;
877 }
878 dev_priv->wait_evnt = savage_bci_wait_event_reg;
879 }
880
881 /* cliprect functions */
882 if (S3_SAVAGE3D_SERIES(dev_priv->chipset))
883 dev_priv->emit_clip_rect = savage_emit_clip_rect_s3d;
884 else
885 dev_priv->emit_clip_rect = savage_emit_clip_rect_s4;
886
887 if (savage_freelist_init(dev) < 0) {
888 DRM_ERROR("could not initialize freelist\n");
889 savage_do_cleanup_bci(dev);
890 return DRM_ERR(ENOMEM);
891 }
892
893 if (savage_dma_init(dev_priv) < 0) {
894 DRM_ERROR("could not initialize command DMA\n");
895 savage_do_cleanup_bci(dev);
896 return DRM_ERR(ENOMEM);
897 }
898
899 return 0;
900 }
901
902 int savage_do_cleanup_bci(drm_device_t * dev)
903 {
904 drm_savage_private_t *dev_priv = dev->dev_private;
905
906 if (dev_priv->cmd_dma == &dev_priv->fake_dma) {
907 if (dev_priv->fake_dma.handle)
908 drm_free(dev_priv->fake_dma.handle,
909 SAVAGE_FAKE_DMA_SIZE, DRM_MEM_DRIVER);
910 } else if (dev_priv->cmd_dma && dev_priv->cmd_dma->handle &&
911 dev_priv->cmd_dma->type == _DRM_AGP &&
912 dev_priv->dma_type == SAVAGE_DMA_AGP)
913 drm_core_ioremapfree(dev_priv->cmd_dma, dev);
914
915 if (dev_priv->dma_type == SAVAGE_DMA_AGP &&
916 dev->agp_buffer_map && dev->agp_buffer_map->handle) {
917 drm_core_ioremapfree(dev->agp_buffer_map, dev);
918 /* make sure the next instance (which may be running
919 * in PCI mode) doesn't try to use an old
920 * agp_buffer_map. */
921 dev->agp_buffer_map = NULL;
922 }
923
924 if (dev_priv->dma_pages)
925 drm_free(dev_priv->dma_pages,
926 sizeof(drm_savage_dma_page_t) * dev_priv->nr_dma_pages,
927 DRM_MEM_DRIVER);
928
929 return 0;
930 }
931
932 static int savage_bci_init(DRM_IOCTL_ARGS)
933 {
934 DRM_DEVICE;
935 drm_savage_init_t init;
936
937 LOCK_TEST_WITH_RETURN(dev, filp);
938
939 DRM_COPY_FROM_USER_IOCTL(init, (drm_savage_init_t __user *) data,
940 sizeof(init));
941
942 switch (init.func) {
943 case SAVAGE_INIT_BCI:
944 return savage_do_init_bci(dev, &init);
945 case SAVAGE_CLEANUP_BCI:
946 return savage_do_cleanup_bci(dev);
947 }
948
949 return DRM_ERR(EINVAL);
950 }
951
952 static int savage_bci_event_emit(DRM_IOCTL_ARGS)
953 {
954 DRM_DEVICE;
955 drm_savage_private_t *dev_priv = dev->dev_private;
956 drm_savage_event_emit_t event;
957
958 DRM_DEBUG("\n");
959
960 LOCK_TEST_WITH_RETURN(dev, filp);
961
962 DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_emit_t __user *) data,
963 sizeof(event));
964
965 event.count = savage_bci_emit_event(dev_priv, event.flags);
966 event.count |= dev_priv->event_wrap << 16;
967 DRM_COPY_TO_USER_IOCTL(&((drm_savage_event_emit_t __user *) data)->
968 count, event.count, sizeof(event.count));
969 return 0;
970 }
971
972 static int savage_bci_event_wait(DRM_IOCTL_ARGS)
973 {
974 DRM_DEVICE;
975 drm_savage_private_t *dev_priv = dev->dev_private;
976 drm_savage_event_wait_t event;
977 unsigned int event_e, hw_e;
978 unsigned int event_w, hw_w;
979
980 DRM_DEBUG("\n");
981
982 DRM_COPY_FROM_USER_IOCTL(event, (drm_savage_event_wait_t __user *) data,
983 sizeof(event));
984
985 UPDATE_EVENT_COUNTER();
986 if (dev_priv->status_ptr)
987 hw_e = dev_priv->status_ptr[1] & 0xffff;
988 else
989 hw_e = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
990 hw_w = dev_priv->event_wrap;
991 if (hw_e > dev_priv->event_counter)
992 hw_w--; /* hardware hasn't passed the last wrap yet */
993
994 event_e = event.count & 0xffff;
995 event_w = event.count >> 16;
996
997 /* Don't need to wait if
998 * - event counter wrapped since the event was emitted or
999 * - the hardware has advanced up to or over the event to wait for.
1000 */
1001 if (event_w < hw_w || (event_w == hw_w && event_e <= hw_e))
1002 return 0;
1003 else
1004 return dev_priv->wait_evnt(dev_priv, event_e);
1005 }
1006
1007 /*
1008 * DMA buffer management
1009 */
1010
1011 static int savage_bci_get_buffers(DRMFILE filp, drm_device_t * dev,
1012 drm_dma_t * d)
1013 {
1014 drm_buf_t *buf;
1015 int i;
1016
1017 for (i = d->granted_count; i < d->request_count; i++) {
1018 buf = savage_freelist_get(dev);
1019 if (!buf)
1020 return DRM_ERR(EAGAIN);
1021
1022 buf->filp = filp;
1023
1024 if (DRM_COPY_TO_USER(&d->request_indices[i],
1025 &buf->idx, sizeof(buf->idx)))
1026 return DRM_ERR(EFAULT);
1027 if (DRM_COPY_TO_USER(&d->request_sizes[i],
1028 &buf->total, sizeof(buf->total)))
1029 return DRM_ERR(EFAULT);
1030
1031 d->granted_count++;
1032 }
1033 return 0;
1034 }
1035
1036 int savage_bci_buffers(DRM_IOCTL_ARGS)
1037 {
1038 DRM_DEVICE;
1039 drm_device_dma_t *dma = dev->dma;
1040 drm_dma_t d;
1041 int ret = 0;
1042
1043 LOCK_TEST_WITH_RETURN(dev, filp);
1044
1045 DRM_COPY_FROM_USER_IOCTL(d, (drm_dma_t __user *) data, sizeof(d));
1046
1047 /* Please don't send us buffers.
1048 */
1049 if (d.send_count != 0) {
1050 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1051 DRM_CURRENTPID, d.send_count);
1052 return DRM_ERR(EINVAL);
1053 }
1054
1055 /* We'll send you buffers.
1056 */
1057 if (d.request_count < 0 || d.request_count > dma->buf_count) {
1058 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1059 DRM_CURRENTPID, d.request_count, dma->buf_count);
1060 return DRM_ERR(EINVAL);
1061 }
1062
1063 d.granted_count = 0;
1064
1065 if (d.request_count) {
1066 ret = savage_bci_get_buffers(filp, dev, &d);
1067 }
1068
1069 DRM_COPY_TO_USER_IOCTL((drm_dma_t __user *) data, d, sizeof(d));
1070
1071 return ret;
1072 }
1073
1074 void savage_reclaim_buffers(drm_device_t * dev, DRMFILE filp)
1075 {
1076 drm_device_dma_t *dma = dev->dma;
1077 drm_savage_private_t *dev_priv = dev->dev_private;
1078 int i;
1079
1080 if (!dma)
1081 return;
1082 if (!dev_priv)
1083 return;
1084 if (!dma->buflist)
1085 return;
1086
1087 /*i830_flush_queue(dev); */
1088
1089 for (i = 0; i < dma->buf_count; i++) {
1090 drm_buf_t *buf = dma->buflist[i];
1091 drm_savage_buf_priv_t *buf_priv = buf->dev_private;
1092
1093 if (buf->filp == filp && buf_priv &&
1094 buf_priv->next == NULL && buf_priv->prev == NULL) {
1095 uint16_t event;
1096 DRM_DEBUG("reclaimed from client\n");
1097 event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D);
1098 SET_AGE(&buf_priv->age, event, dev_priv->event_wrap);
1099 savage_freelist_put(dev, buf);
1100 }
1101 }
1102
1103 drm_core_reclaim_buffers(dev, filp);
1104 }
1105
1106 drm_ioctl_desc_t savage_ioctls[] = {
1107 [DRM_IOCTL_NR(DRM_SAVAGE_BCI_INIT)] = {savage_bci_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
1108 [DRM_IOCTL_NR(DRM_SAVAGE_BCI_CMDBUF)] = {savage_bci_cmdbuf, DRM_AUTH},
1109 [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_EMIT)] = {savage_bci_event_emit, DRM_AUTH},
1110 [DRM_IOCTL_NR(DRM_SAVAGE_BCI_EVENT_WAIT)] = {savage_bci_event_wait, DRM_AUTH},
1111 };
1112
1113 int savage_max_ioctl = DRM_ARRAY_SIZE(savage_ioctls);
Linux kernel - Deliverables
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