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tty: Add carrier processing on close to the tty_port core
[deliverable/linux.git] / drivers / char / synclink_gt.c
1 /*
2 * Device driver for Microgate SyncLink GT serial adapters.
3 *
4 * written by Paul Fulghum for Microgate Corporation
5 * paulkf@microgate.com
6 *
7 * Microgate and SyncLink are trademarks of Microgate Corporation
8 *
9 * This code is released under the GNU General Public License (GPL)
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
13 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
14 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
15 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
16 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
17 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
18 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
19 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
20 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
21 * OF THE POSSIBILITY OF SUCH DAMAGE.
22 */
23
24 /*
25 * DEBUG OUTPUT DEFINITIONS
26 *
27 * uncomment lines below to enable specific types of debug output
28 *
29 * DBGINFO information - most verbose output
30 * DBGERR serious errors
31 * DBGBH bottom half service routine debugging
32 * DBGISR interrupt service routine debugging
33 * DBGDATA output receive and transmit data
34 * DBGTBUF output transmit DMA buffers and registers
35 * DBGRBUF output receive DMA buffers and registers
36 */
37
38 #define DBGINFO(fmt) if (debug_level >= DEBUG_LEVEL_INFO) printk fmt
39 #define DBGERR(fmt) if (debug_level >= DEBUG_LEVEL_ERROR) printk fmt
40 #define DBGBH(fmt) if (debug_level >= DEBUG_LEVEL_BH) printk fmt
41 #define DBGISR(fmt) if (debug_level >= DEBUG_LEVEL_ISR) printk fmt
42 #define DBGDATA(info, buf, size, label) if (debug_level >= DEBUG_LEVEL_DATA) trace_block((info), (buf), (size), (label))
43 //#define DBGTBUF(info) dump_tbufs(info)
44 //#define DBGRBUF(info) dump_rbufs(info)
45
46
47 #include <linux/module.h>
48 #include <linux/errno.h>
49 #include <linux/signal.h>
50 #include <linux/sched.h>
51 #include <linux/timer.h>
52 #include <linux/interrupt.h>
53 #include <linux/pci.h>
54 #include <linux/tty.h>
55 #include <linux/tty_flip.h>
56 #include <linux/serial.h>
57 #include <linux/major.h>
58 #include <linux/string.h>
59 #include <linux/fcntl.h>
60 #include <linux/ptrace.h>
61 #include <linux/ioport.h>
62 #include <linux/mm.h>
63 #include <linux/seq_file.h>
64 #include <linux/slab.h>
65 #include <linux/netdevice.h>
66 #include <linux/vmalloc.h>
67 #include <linux/init.h>
68 #include <linux/delay.h>
69 #include <linux/ioctl.h>
70 #include <linux/termios.h>
71 #include <linux/bitops.h>
72 #include <linux/workqueue.h>
73 #include <linux/hdlc.h>
74 #include <linux/synclink.h>
75
76 #include <asm/system.h>
77 #include <asm/io.h>
78 #include <asm/irq.h>
79 #include <asm/dma.h>
80 #include <asm/types.h>
81 #include <asm/uaccess.h>
82
83 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINK_GT_MODULE))
84 #define SYNCLINK_GENERIC_HDLC 1
85 #else
86 #define SYNCLINK_GENERIC_HDLC 0
87 #endif
88
89 /*
90 * module identification
91 */
92 static char *driver_name = "SyncLink GT";
93 static char *tty_driver_name = "synclink_gt";
94 static char *tty_dev_prefix = "ttySLG";
95 MODULE_LICENSE("GPL");
96 #define MGSL_MAGIC 0x5401
97 #define MAX_DEVICES 32
98
99 static struct pci_device_id pci_table[] = {
100 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
101 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT2_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
102 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_GT4_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
103 {PCI_VENDOR_ID_MICROGATE, SYNCLINK_AC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
104 {0,}, /* terminate list */
105 };
106 MODULE_DEVICE_TABLE(pci, pci_table);
107
108 static int init_one(struct pci_dev *dev,const struct pci_device_id *ent);
109 static void remove_one(struct pci_dev *dev);
110 static struct pci_driver pci_driver = {
111 .name = "synclink_gt",
112 .id_table = pci_table,
113 .probe = init_one,
114 .remove = __devexit_p(remove_one),
115 };
116
117 static bool pci_registered;
118
119 /*
120 * module configuration and status
121 */
122 static struct slgt_info *slgt_device_list;
123 static int slgt_device_count;
124
125 static int ttymajor;
126 static int debug_level;
127 static int maxframe[MAX_DEVICES];
128
129 module_param(ttymajor, int, 0);
130 module_param(debug_level, int, 0);
131 module_param_array(maxframe, int, NULL, 0);
132
133 MODULE_PARM_DESC(ttymajor, "TTY major device number override: 0=auto assigned");
134 MODULE_PARM_DESC(debug_level, "Debug syslog output: 0=disabled, 1 to 5=increasing detail");
135 MODULE_PARM_DESC(maxframe, "Maximum frame size used by device (4096 to 65535)");
136
137 /*
138 * tty support and callbacks
139 */
140 static struct tty_driver *serial_driver;
141
142 static int open(struct tty_struct *tty, struct file * filp);
143 static void close(struct tty_struct *tty, struct file * filp);
144 static void hangup(struct tty_struct *tty);
145 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
146
147 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
148 static int put_char(struct tty_struct *tty, unsigned char ch);
149 static void send_xchar(struct tty_struct *tty, char ch);
150 static void wait_until_sent(struct tty_struct *tty, int timeout);
151 static int write_room(struct tty_struct *tty);
152 static void flush_chars(struct tty_struct *tty);
153 static void flush_buffer(struct tty_struct *tty);
154 static void tx_hold(struct tty_struct *tty);
155 static void tx_release(struct tty_struct *tty);
156
157 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
158 static int chars_in_buffer(struct tty_struct *tty);
159 static void throttle(struct tty_struct * tty);
160 static void unthrottle(struct tty_struct * tty);
161 static int set_break(struct tty_struct *tty, int break_state);
162
163 /*
164 * generic HDLC support and callbacks
165 */
166 #if SYNCLINK_GENERIC_HDLC
167 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
168 static void hdlcdev_tx_done(struct slgt_info *info);
169 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size);
170 static int hdlcdev_init(struct slgt_info *info);
171 static void hdlcdev_exit(struct slgt_info *info);
172 #endif
173
174
175 /*
176 * device specific structures, macros and functions
177 */
178
179 #define SLGT_MAX_PORTS 4
180 #define SLGT_REG_SIZE 256
181
182 /*
183 * conditional wait facility
184 */
185 struct cond_wait {
186 struct cond_wait *next;
187 wait_queue_head_t q;
188 wait_queue_t wait;
189 unsigned int data;
190 };
191 static void init_cond_wait(struct cond_wait *w, unsigned int data);
192 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w);
193 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *w);
194 static void flush_cond_wait(struct cond_wait **head);
195
196 /*
197 * DMA buffer descriptor and access macros
198 */
199 struct slgt_desc
200 {
201 __le16 count;
202 __le16 status;
203 __le32 pbuf; /* physical address of data buffer */
204 __le32 next; /* physical address of next descriptor */
205
206 /* driver book keeping */
207 char *buf; /* virtual address of data buffer */
208 unsigned int pdesc; /* physical address of this descriptor */
209 dma_addr_t buf_dma_addr;
210 unsigned short buf_count;
211 };
212
213 #define set_desc_buffer(a,b) (a).pbuf = cpu_to_le32((unsigned int)(b))
214 #define set_desc_next(a,b) (a).next = cpu_to_le32((unsigned int)(b))
215 #define set_desc_count(a,b)(a).count = cpu_to_le16((unsigned short)(b))
216 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
217 #define desc_count(a) (le16_to_cpu((a).count))
218 #define desc_status(a) (le16_to_cpu((a).status))
219 #define desc_complete(a) (le16_to_cpu((a).status) & BIT15)
220 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2)
221 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
222 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
223 #define desc_residue(a) ((le16_to_cpu((a).status) & 0x38) >> 3)
224
225 struct _input_signal_events {
226 int ri_up;
227 int ri_down;
228 int dsr_up;
229 int dsr_down;
230 int dcd_up;
231 int dcd_down;
232 int cts_up;
233 int cts_down;
234 };
235
236 /*
237 * device instance data structure
238 */
239 struct slgt_info {
240 void *if_ptr; /* General purpose pointer (used by SPPP) */
241 struct tty_port port;
242
243 struct slgt_info *next_device; /* device list link */
244
245 int magic;
246
247 char device_name[25];
248 struct pci_dev *pdev;
249
250 int port_count; /* count of ports on adapter */
251 int adapter_num; /* adapter instance number */
252 int port_num; /* port instance number */
253
254 /* array of pointers to port contexts on this adapter */
255 struct slgt_info *port_array[SLGT_MAX_PORTS];
256
257 int line; /* tty line instance number */
258
259 struct mgsl_icount icount;
260
261 int timeout;
262 int x_char; /* xon/xoff character */
263 unsigned int read_status_mask;
264 unsigned int ignore_status_mask;
265
266 wait_queue_head_t status_event_wait_q;
267 wait_queue_head_t event_wait_q;
268 struct timer_list tx_timer;
269 struct timer_list rx_timer;
270
271 unsigned int gpio_present;
272 struct cond_wait *gpio_wait_q;
273
274 spinlock_t lock; /* spinlock for synchronizing with ISR */
275
276 struct work_struct task;
277 u32 pending_bh;
278 bool bh_requested;
279 bool bh_running;
280
281 int isr_overflow;
282 bool irq_requested; /* true if IRQ requested */
283 bool irq_occurred; /* for diagnostics use */
284
285 /* device configuration */
286
287 unsigned int bus_type;
288 unsigned int irq_level;
289 unsigned long irq_flags;
290
291 unsigned char __iomem * reg_addr; /* memory mapped registers address */
292 u32 phys_reg_addr;
293 bool reg_addr_requested;
294
295 MGSL_PARAMS params; /* communications parameters */
296 u32 idle_mode;
297 u32 max_frame_size; /* as set by device config */
298
299 unsigned int rbuf_fill_level;
300 unsigned int if_mode;
301 unsigned int base_clock;
302
303 /* device status */
304
305 bool rx_enabled;
306 bool rx_restart;
307
308 bool tx_enabled;
309 bool tx_active;
310
311 unsigned char signals; /* serial signal states */
312 int init_error; /* initialization error */
313
314 unsigned char *tx_buf;
315 int tx_count;
316
317 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
318 char char_buf[MAX_ASYNC_BUFFER_SIZE];
319 bool drop_rts_on_tx_done;
320 struct _input_signal_events input_signal_events;
321
322 int dcd_chkcount; /* check counts to prevent */
323 int cts_chkcount; /* too many IRQs if a signal */
324 int dsr_chkcount; /* is floating */
325 int ri_chkcount;
326
327 char *bufs; /* virtual address of DMA buffer lists */
328 dma_addr_t bufs_dma_addr; /* physical address of buffer descriptors */
329
330 unsigned int rbuf_count;
331 struct slgt_desc *rbufs;
332 unsigned int rbuf_current;
333 unsigned int rbuf_index;
334
335 unsigned int tbuf_count;
336 struct slgt_desc *tbufs;
337 unsigned int tbuf_current;
338 unsigned int tbuf_start;
339
340 unsigned char *tmp_rbuf;
341 unsigned int tmp_rbuf_count;
342
343 /* SPPP/Cisco HDLC device parts */
344
345 int netcount;
346 spinlock_t netlock;
347 #if SYNCLINK_GENERIC_HDLC
348 struct net_device *netdev;
349 #endif
350
351 };
352
353 static MGSL_PARAMS default_params = {
354 .mode = MGSL_MODE_HDLC,
355 .loopback = 0,
356 .flags = HDLC_FLAG_UNDERRUN_ABORT15,
357 .encoding = HDLC_ENCODING_NRZI_SPACE,
358 .clock_speed = 0,
359 .addr_filter = 0xff,
360 .crc_type = HDLC_CRC_16_CCITT,
361 .preamble_length = HDLC_PREAMBLE_LENGTH_8BITS,
362 .preamble = HDLC_PREAMBLE_PATTERN_NONE,
363 .data_rate = 9600,
364 .data_bits = 8,
365 .stop_bits = 1,
366 .parity = ASYNC_PARITY_NONE
367 };
368
369
370 #define BH_RECEIVE 1
371 #define BH_TRANSMIT 2
372 #define BH_STATUS 4
373 #define IO_PIN_SHUTDOWN_LIMIT 100
374
375 #define DMABUFSIZE 256
376 #define DESC_LIST_SIZE 4096
377
378 #define MASK_PARITY BIT1
379 #define MASK_FRAMING BIT0
380 #define MASK_BREAK BIT14
381 #define MASK_OVERRUN BIT4
382
383 #define GSR 0x00 /* global status */
384 #define JCR 0x04 /* JTAG control */
385 #define IODR 0x08 /* GPIO direction */
386 #define IOER 0x0c /* GPIO interrupt enable */
387 #define IOVR 0x10 /* GPIO value */
388 #define IOSR 0x14 /* GPIO interrupt status */
389 #define TDR 0x80 /* tx data */
390 #define RDR 0x80 /* rx data */
391 #define TCR 0x82 /* tx control */
392 #define TIR 0x84 /* tx idle */
393 #define TPR 0x85 /* tx preamble */
394 #define RCR 0x86 /* rx control */
395 #define VCR 0x88 /* V.24 control */
396 #define CCR 0x89 /* clock control */
397 #define BDR 0x8a /* baud divisor */
398 #define SCR 0x8c /* serial control */
399 #define SSR 0x8e /* serial status */
400 #define RDCSR 0x90 /* rx DMA control/status */
401 #define TDCSR 0x94 /* tx DMA control/status */
402 #define RDDAR 0x98 /* rx DMA descriptor address */
403 #define TDDAR 0x9c /* tx DMA descriptor address */
404
405 #define RXIDLE BIT14
406 #define RXBREAK BIT14
407 #define IRQ_TXDATA BIT13
408 #define IRQ_TXIDLE BIT12
409 #define IRQ_TXUNDER BIT11 /* HDLC */
410 #define IRQ_RXDATA BIT10
411 #define IRQ_RXIDLE BIT9 /* HDLC */
412 #define IRQ_RXBREAK BIT9 /* async */
413 #define IRQ_RXOVER BIT8
414 #define IRQ_DSR BIT7
415 #define IRQ_CTS BIT6
416 #define IRQ_DCD BIT5
417 #define IRQ_RI BIT4
418 #define IRQ_ALL 0x3ff0
419 #define IRQ_MASTER BIT0
420
421 #define slgt_irq_on(info, mask) \
422 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) | (mask)))
423 #define slgt_irq_off(info, mask) \
424 wr_reg16((info), SCR, (unsigned short)(rd_reg16((info), SCR) & ~(mask)))
425
426 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr);
427 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value);
428 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr);
429 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value);
430 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr);
431 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value);
432
433 static void msc_set_vcr(struct slgt_info *info);
434
435 static int startup(struct slgt_info *info);
436 static int block_til_ready(struct tty_struct *tty, struct file * filp,struct slgt_info *info);
437 static void shutdown(struct slgt_info *info);
438 static void program_hw(struct slgt_info *info);
439 static void change_params(struct slgt_info *info);
440
441 static int register_test(struct slgt_info *info);
442 static int irq_test(struct slgt_info *info);
443 static int loopback_test(struct slgt_info *info);
444 static int adapter_test(struct slgt_info *info);
445
446 static void reset_adapter(struct slgt_info *info);
447 static void reset_port(struct slgt_info *info);
448 static void async_mode(struct slgt_info *info);
449 static void sync_mode(struct slgt_info *info);
450
451 static void rx_stop(struct slgt_info *info);
452 static void rx_start(struct slgt_info *info);
453 static void reset_rbufs(struct slgt_info *info);
454 static void free_rbufs(struct slgt_info *info, unsigned int first, unsigned int last);
455 static void rdma_reset(struct slgt_info *info);
456 static bool rx_get_frame(struct slgt_info *info);
457 static bool rx_get_buf(struct slgt_info *info);
458
459 static void tx_start(struct slgt_info *info);
460 static void tx_stop(struct slgt_info *info);
461 static void tx_set_idle(struct slgt_info *info);
462 static unsigned int free_tbuf_count(struct slgt_info *info);
463 static unsigned int tbuf_bytes(struct slgt_info *info);
464 static void reset_tbufs(struct slgt_info *info);
465 static void tdma_reset(struct slgt_info *info);
466 static void tdma_start(struct slgt_info *info);
467 static void tx_load(struct slgt_info *info, const char *buf, unsigned int count);
468
469 static void get_signals(struct slgt_info *info);
470 static void set_signals(struct slgt_info *info);
471 static void enable_loopback(struct slgt_info *info);
472 static void set_rate(struct slgt_info *info, u32 data_rate);
473
474 static int bh_action(struct slgt_info *info);
475 static void bh_handler(struct work_struct *work);
476 static void bh_transmit(struct slgt_info *info);
477 static void isr_serial(struct slgt_info *info);
478 static void isr_rdma(struct slgt_info *info);
479 static void isr_txeom(struct slgt_info *info, unsigned short status);
480 static void isr_tdma(struct slgt_info *info);
481
482 static int alloc_dma_bufs(struct slgt_info *info);
483 static void free_dma_bufs(struct slgt_info *info);
484 static int alloc_desc(struct slgt_info *info);
485 static void free_desc(struct slgt_info *info);
486 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
487 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count);
488
489 static int alloc_tmp_rbuf(struct slgt_info *info);
490 static void free_tmp_rbuf(struct slgt_info *info);
491
492 static void tx_timeout(unsigned long context);
493 static void rx_timeout(unsigned long context);
494
495 /*
496 * ioctl handlers
497 */
498 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount);
499 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *params);
500 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *params);
501 static int get_txidle(struct slgt_info *info, int __user *idle_mode);
502 static int set_txidle(struct slgt_info *info, int idle_mode);
503 static int tx_enable(struct slgt_info *info, int enable);
504 static int tx_abort(struct slgt_info *info);
505 static int rx_enable(struct slgt_info *info, int enable);
506 static int modem_input_wait(struct slgt_info *info,int arg);
507 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr);
508 static int tiocmget(struct tty_struct *tty, struct file *file);
509 static int tiocmset(struct tty_struct *tty, struct file *file,
510 unsigned int set, unsigned int clear);
511 static int set_break(struct tty_struct *tty, int break_state);
512 static int get_interface(struct slgt_info *info, int __user *if_mode);
513 static int set_interface(struct slgt_info *info, int if_mode);
514 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
515 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
516 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *gpio);
517
518 /*
519 * driver functions
520 */
521 static void add_device(struct slgt_info *info);
522 static void device_init(int adapter_num, struct pci_dev *pdev);
523 static int claim_resources(struct slgt_info *info);
524 static void release_resources(struct slgt_info *info);
525
526 /*
527 * DEBUG OUTPUT CODE
528 */
529 #ifndef DBGINFO
530 #define DBGINFO(fmt)
531 #endif
532 #ifndef DBGERR
533 #define DBGERR(fmt)
534 #endif
535 #ifndef DBGBH
536 #define DBGBH(fmt)
537 #endif
538 #ifndef DBGISR
539 #define DBGISR(fmt)
540 #endif
541
542 #ifdef DBGDATA
543 static void trace_block(struct slgt_info *info, const char *data, int count, const char *label)
544 {
545 int i;
546 int linecount;
547 printk("%s %s data:\n",info->device_name, label);
548 while(count) {
549 linecount = (count > 16) ? 16 : count;
550 for(i=0; i < linecount; i++)
551 printk("%02X ",(unsigned char)data[i]);
552 for(;i<17;i++)
553 printk(" ");
554 for(i=0;i<linecount;i++) {
555 if (data[i]>=040 && data[i]<=0176)
556 printk("%c",data[i]);
557 else
558 printk(".");
559 }
560 printk("\n");
561 data += linecount;
562 count -= linecount;
563 }
564 }
565 #else
566 #define DBGDATA(info, buf, size, label)
567 #endif
568
569 #ifdef DBGTBUF
570 static void dump_tbufs(struct slgt_info *info)
571 {
572 int i;
573 printk("tbuf_current=%d\n", info->tbuf_current);
574 for (i=0 ; i < info->tbuf_count ; i++) {
575 printk("%d: count=%04X status=%04X\n",
576 i, le16_to_cpu(info->tbufs[i].count), le16_to_cpu(info->tbufs[i].status));
577 }
578 }
579 #else
580 #define DBGTBUF(info)
581 #endif
582
583 #ifdef DBGRBUF
584 static void dump_rbufs(struct slgt_info *info)
585 {
586 int i;
587 printk("rbuf_current=%d\n", info->rbuf_current);
588 for (i=0 ; i < info->rbuf_count ; i++) {
589 printk("%d: count=%04X status=%04X\n",
590 i, le16_to_cpu(info->rbufs[i].count), le16_to_cpu(info->rbufs[i].status));
591 }
592 }
593 #else
594 #define DBGRBUF(info)
595 #endif
596
597 static inline int sanity_check(struct slgt_info *info, char *devname, const char *name)
598 {
599 #ifdef SANITY_CHECK
600 if (!info) {
601 printk("null struct slgt_info for (%s) in %s\n", devname, name);
602 return 1;
603 }
604 if (info->magic != MGSL_MAGIC) {
605 printk("bad magic number struct slgt_info (%s) in %s\n", devname, name);
606 return 1;
607 }
608 #else
609 if (!info)
610 return 1;
611 #endif
612 return 0;
613 }
614
615 /**
616 * line discipline callback wrappers
617 *
618 * The wrappers maintain line discipline references
619 * while calling into the line discipline.
620 *
621 * ldisc_receive_buf - pass receive data to line discipline
622 */
623 static void ldisc_receive_buf(struct tty_struct *tty,
624 const __u8 *data, char *flags, int count)
625 {
626 struct tty_ldisc *ld;
627 if (!tty)
628 return;
629 ld = tty_ldisc_ref(tty);
630 if (ld) {
631 if (ld->ops->receive_buf)
632 ld->ops->receive_buf(tty, data, flags, count);
633 tty_ldisc_deref(ld);
634 }
635 }
636
637 /* tty callbacks */
638
639 static int open(struct tty_struct *tty, struct file *filp)
640 {
641 struct slgt_info *info;
642 int retval, line;
643 unsigned long flags;
644
645 line = tty->index;
646 if ((line < 0) || (line >= slgt_device_count)) {
647 DBGERR(("%s: open with invalid line #%d.\n", driver_name, line));
648 return -ENODEV;
649 }
650
651 info = slgt_device_list;
652 while(info && info->line != line)
653 info = info->next_device;
654 if (sanity_check(info, tty->name, "open"))
655 return -ENODEV;
656 if (info->init_error) {
657 DBGERR(("%s init error=%d\n", info->device_name, info->init_error));
658 return -ENODEV;
659 }
660
661 tty->driver_data = info;
662 info->port.tty = tty;
663
664 DBGINFO(("%s open, old ref count = %d\n", info->device_name, info->port.count));
665
666 /* If port is closing, signal caller to try again */
667 if (tty_hung_up_p(filp) || info->port.flags & ASYNC_CLOSING){
668 if (info->port.flags & ASYNC_CLOSING)
669 interruptible_sleep_on(&info->port.close_wait);
670 retval = ((info->port.flags & ASYNC_HUP_NOTIFY) ?
671 -EAGAIN : -ERESTARTSYS);
672 goto cleanup;
673 }
674
675 info->port.tty->low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
676
677 spin_lock_irqsave(&info->netlock, flags);
678 if (info->netcount) {
679 retval = -EBUSY;
680 spin_unlock_irqrestore(&info->netlock, flags);
681 goto cleanup;
682 }
683 info->port.count++;
684 spin_unlock_irqrestore(&info->netlock, flags);
685
686 if (info->port.count == 1) {
687 /* 1st open on this device, init hardware */
688 retval = startup(info);
689 if (retval < 0)
690 goto cleanup;
691 }
692
693 retval = block_til_ready(tty, filp, info);
694 if (retval) {
695 DBGINFO(("%s block_til_ready rc=%d\n", info->device_name, retval));
696 goto cleanup;
697 }
698
699 retval = 0;
700
701 cleanup:
702 if (retval) {
703 if (tty->count == 1)
704 info->port.tty = NULL; /* tty layer will release tty struct */
705 if(info->port.count)
706 info->port.count--;
707 }
708
709 DBGINFO(("%s open rc=%d\n", info->device_name, retval));
710 return retval;
711 }
712
713 static void close(struct tty_struct *tty, struct file *filp)
714 {
715 struct slgt_info *info = tty->driver_data;
716
717 if (sanity_check(info, tty->name, "close"))
718 return;
719 DBGINFO(("%s close entry, count=%d\n", info->device_name, info->port.count));
720
721 if (tty_port_close_start(&info->port, tty, filp) == 0)
722 goto cleanup;
723
724 if (info->port.flags & ASYNC_INITIALIZED)
725 wait_until_sent(tty, info->timeout);
726 flush_buffer(tty);
727 tty_ldisc_flush(tty);
728
729 shutdown(info);
730
731 tty_port_close_end(&info->port, tty);
732 info->port.tty = NULL;
733 cleanup:
734 DBGINFO(("%s close exit, count=%d\n", tty->driver->name, info->port.count));
735 }
736
737 static void hangup(struct tty_struct *tty)
738 {
739 struct slgt_info *info = tty->driver_data;
740
741 if (sanity_check(info, tty->name, "hangup"))
742 return;
743 DBGINFO(("%s hangup\n", info->device_name));
744
745 flush_buffer(tty);
746 shutdown(info);
747
748 info->port.count = 0;
749 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
750 info->port.tty = NULL;
751
752 wake_up_interruptible(&info->port.open_wait);
753 }
754
755 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
756 {
757 struct slgt_info *info = tty->driver_data;
758 unsigned long flags;
759
760 DBGINFO(("%s set_termios\n", tty->driver->name));
761
762 change_params(info);
763
764 /* Handle transition to B0 status */
765 if (old_termios->c_cflag & CBAUD &&
766 !(tty->termios->c_cflag & CBAUD)) {
767 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
768 spin_lock_irqsave(&info->lock,flags);
769 set_signals(info);
770 spin_unlock_irqrestore(&info->lock,flags);
771 }
772
773 /* Handle transition away from B0 status */
774 if (!(old_termios->c_cflag & CBAUD) &&
775 tty->termios->c_cflag & CBAUD) {
776 info->signals |= SerialSignal_DTR;
777 if (!(tty->termios->c_cflag & CRTSCTS) ||
778 !test_bit(TTY_THROTTLED, &tty->flags)) {
779 info->signals |= SerialSignal_RTS;
780 }
781 spin_lock_irqsave(&info->lock,flags);
782 set_signals(info);
783 spin_unlock_irqrestore(&info->lock,flags);
784 }
785
786 /* Handle turning off CRTSCTS */
787 if (old_termios->c_cflag & CRTSCTS &&
788 !(tty->termios->c_cflag & CRTSCTS)) {
789 tty->hw_stopped = 0;
790 tx_release(tty);
791 }
792 }
793
794 static int write(struct tty_struct *tty,
795 const unsigned char *buf, int count)
796 {
797 int ret = 0;
798 struct slgt_info *info = tty->driver_data;
799 unsigned long flags;
800 unsigned int bufs_needed;
801
802 if (sanity_check(info, tty->name, "write"))
803 goto cleanup;
804 DBGINFO(("%s write count=%d\n", info->device_name, count));
805
806 if (!info->tx_buf)
807 goto cleanup;
808
809 if (count > info->max_frame_size) {
810 ret = -EIO;
811 goto cleanup;
812 }
813
814 if (!count)
815 goto cleanup;
816
817 if (!info->tx_active && info->tx_count) {
818 /* send accumulated data from send_char() */
819 tx_load(info, info->tx_buf, info->tx_count);
820 goto start;
821 }
822 bufs_needed = (count/DMABUFSIZE);
823 if (count % DMABUFSIZE)
824 ++bufs_needed;
825 if (bufs_needed > free_tbuf_count(info))
826 goto cleanup;
827
828 ret = info->tx_count = count;
829 tx_load(info, buf, count);
830 goto start;
831
832 start:
833 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
834 spin_lock_irqsave(&info->lock,flags);
835 if (!info->tx_active)
836 tx_start(info);
837 else
838 tdma_start(info);
839 spin_unlock_irqrestore(&info->lock,flags);
840 }
841
842 cleanup:
843 DBGINFO(("%s write rc=%d\n", info->device_name, ret));
844 return ret;
845 }
846
847 static int put_char(struct tty_struct *tty, unsigned char ch)
848 {
849 struct slgt_info *info = tty->driver_data;
850 unsigned long flags;
851 int ret = 0;
852
853 if (sanity_check(info, tty->name, "put_char"))
854 return 0;
855 DBGINFO(("%s put_char(%d)\n", info->device_name, ch));
856 if (!info->tx_buf)
857 return 0;
858 spin_lock_irqsave(&info->lock,flags);
859 if (!info->tx_active && (info->tx_count < info->max_frame_size)) {
860 info->tx_buf[info->tx_count++] = ch;
861 ret = 1;
862 }
863 spin_unlock_irqrestore(&info->lock,flags);
864 return ret;
865 }
866
867 static void send_xchar(struct tty_struct *tty, char ch)
868 {
869 struct slgt_info *info = tty->driver_data;
870 unsigned long flags;
871
872 if (sanity_check(info, tty->name, "send_xchar"))
873 return;
874 DBGINFO(("%s send_xchar(%d)\n", info->device_name, ch));
875 info->x_char = ch;
876 if (ch) {
877 spin_lock_irqsave(&info->lock,flags);
878 if (!info->tx_enabled)
879 tx_start(info);
880 spin_unlock_irqrestore(&info->lock,flags);
881 }
882 }
883
884 static void wait_until_sent(struct tty_struct *tty, int timeout)
885 {
886 struct slgt_info *info = tty->driver_data;
887 unsigned long orig_jiffies, char_time;
888
889 if (!info )
890 return;
891 if (sanity_check(info, tty->name, "wait_until_sent"))
892 return;
893 DBGINFO(("%s wait_until_sent entry\n", info->device_name));
894 if (!(info->port.flags & ASYNC_INITIALIZED))
895 goto exit;
896
897 orig_jiffies = jiffies;
898
899 /* Set check interval to 1/5 of estimated time to
900 * send a character, and make it at least 1. The check
901 * interval should also be less than the timeout.
902 * Note: use tight timings here to satisfy the NIST-PCTS.
903 */
904
905 lock_kernel();
906
907 if (info->params.data_rate) {
908 char_time = info->timeout/(32 * 5);
909 if (!char_time)
910 char_time++;
911 } else
912 char_time = 1;
913
914 if (timeout)
915 char_time = min_t(unsigned long, char_time, timeout);
916
917 while (info->tx_active) {
918 msleep_interruptible(jiffies_to_msecs(char_time));
919 if (signal_pending(current))
920 break;
921 if (timeout && time_after(jiffies, orig_jiffies + timeout))
922 break;
923 }
924 unlock_kernel();
925
926 exit:
927 DBGINFO(("%s wait_until_sent exit\n", info->device_name));
928 }
929
930 static int write_room(struct tty_struct *tty)
931 {
932 struct slgt_info *info = tty->driver_data;
933 int ret;
934
935 if (sanity_check(info, tty->name, "write_room"))
936 return 0;
937 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
938 DBGINFO(("%s write_room=%d\n", info->device_name, ret));
939 return ret;
940 }
941
942 static void flush_chars(struct tty_struct *tty)
943 {
944 struct slgt_info *info = tty->driver_data;
945 unsigned long flags;
946
947 if (sanity_check(info, tty->name, "flush_chars"))
948 return;
949 DBGINFO(("%s flush_chars entry tx_count=%d\n", info->device_name, info->tx_count));
950
951 if (info->tx_count <= 0 || tty->stopped ||
952 tty->hw_stopped || !info->tx_buf)
953 return;
954
955 DBGINFO(("%s flush_chars start transmit\n", info->device_name));
956
957 spin_lock_irqsave(&info->lock,flags);
958 if (!info->tx_active && info->tx_count) {
959 tx_load(info, info->tx_buf,info->tx_count);
960 tx_start(info);
961 }
962 spin_unlock_irqrestore(&info->lock,flags);
963 }
964
965 static void flush_buffer(struct tty_struct *tty)
966 {
967 struct slgt_info *info = tty->driver_data;
968 unsigned long flags;
969
970 if (sanity_check(info, tty->name, "flush_buffer"))
971 return;
972 DBGINFO(("%s flush_buffer\n", info->device_name));
973
974 spin_lock_irqsave(&info->lock,flags);
975 if (!info->tx_active)
976 info->tx_count = 0;
977 spin_unlock_irqrestore(&info->lock,flags);
978
979 tty_wakeup(tty);
980 }
981
982 /*
983 * throttle (stop) transmitter
984 */
985 static void tx_hold(struct tty_struct *tty)
986 {
987 struct slgt_info *info = tty->driver_data;
988 unsigned long flags;
989
990 if (sanity_check(info, tty->name, "tx_hold"))
991 return;
992 DBGINFO(("%s tx_hold\n", info->device_name));
993 spin_lock_irqsave(&info->lock,flags);
994 if (info->tx_enabled && info->params.mode == MGSL_MODE_ASYNC)
995 tx_stop(info);
996 spin_unlock_irqrestore(&info->lock,flags);
997 }
998
999 /*
1000 * release (start) transmitter
1001 */
1002 static void tx_release(struct tty_struct *tty)
1003 {
1004 struct slgt_info *info = tty->driver_data;
1005 unsigned long flags;
1006
1007 if (sanity_check(info, tty->name, "tx_release"))
1008 return;
1009 DBGINFO(("%s tx_release\n", info->device_name));
1010 spin_lock_irqsave(&info->lock,flags);
1011 if (!info->tx_active && info->tx_count) {
1012 tx_load(info, info->tx_buf, info->tx_count);
1013 tx_start(info);
1014 }
1015 spin_unlock_irqrestore(&info->lock,flags);
1016 }
1017
1018 /*
1019 * Service an IOCTL request
1020 *
1021 * Arguments
1022 *
1023 * tty pointer to tty instance data
1024 * file pointer to associated file object for device
1025 * cmd IOCTL command code
1026 * arg command argument/context
1027 *
1028 * Return 0 if success, otherwise error code
1029 */
1030 static int ioctl(struct tty_struct *tty, struct file *file,
1031 unsigned int cmd, unsigned long arg)
1032 {
1033 struct slgt_info *info = tty->driver_data;
1034 struct mgsl_icount cnow; /* kernel counter temps */
1035 struct serial_icounter_struct __user *p_cuser; /* user space */
1036 unsigned long flags;
1037 void __user *argp = (void __user *)arg;
1038 int ret;
1039
1040 if (sanity_check(info, tty->name, "ioctl"))
1041 return -ENODEV;
1042 DBGINFO(("%s ioctl() cmd=%08X\n", info->device_name, cmd));
1043
1044 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1045 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1046 if (tty->flags & (1 << TTY_IO_ERROR))
1047 return -EIO;
1048 }
1049
1050 lock_kernel();
1051
1052 switch (cmd) {
1053 case MGSL_IOCGPARAMS:
1054 ret = get_params(info, argp);
1055 break;
1056 case MGSL_IOCSPARAMS:
1057 ret = set_params(info, argp);
1058 break;
1059 case MGSL_IOCGTXIDLE:
1060 ret = get_txidle(info, argp);
1061 break;
1062 case MGSL_IOCSTXIDLE:
1063 ret = set_txidle(info, (int)arg);
1064 break;
1065 case MGSL_IOCTXENABLE:
1066 ret = tx_enable(info, (int)arg);
1067 break;
1068 case MGSL_IOCRXENABLE:
1069 ret = rx_enable(info, (int)arg);
1070 break;
1071 case MGSL_IOCTXABORT:
1072 ret = tx_abort(info);
1073 break;
1074 case MGSL_IOCGSTATS:
1075 ret = get_stats(info, argp);
1076 break;
1077 case MGSL_IOCWAITEVENT:
1078 ret = wait_mgsl_event(info, argp);
1079 break;
1080 case TIOCMIWAIT:
1081 ret = modem_input_wait(info,(int)arg);
1082 break;
1083 case MGSL_IOCGIF:
1084 ret = get_interface(info, argp);
1085 break;
1086 case MGSL_IOCSIF:
1087 ret = set_interface(info,(int)arg);
1088 break;
1089 case MGSL_IOCSGPIO:
1090 ret = set_gpio(info, argp);
1091 break;
1092 case MGSL_IOCGGPIO:
1093 ret = get_gpio(info, argp);
1094 break;
1095 case MGSL_IOCWAITGPIO:
1096 ret = wait_gpio(info, argp);
1097 break;
1098 case TIOCGICOUNT:
1099 spin_lock_irqsave(&info->lock,flags);
1100 cnow = info->icount;
1101 spin_unlock_irqrestore(&info->lock,flags);
1102 p_cuser = argp;
1103 if (put_user(cnow.cts, &p_cuser->cts) ||
1104 put_user(cnow.dsr, &p_cuser->dsr) ||
1105 put_user(cnow.rng, &p_cuser->rng) ||
1106 put_user(cnow.dcd, &p_cuser->dcd) ||
1107 put_user(cnow.rx, &p_cuser->rx) ||
1108 put_user(cnow.tx, &p_cuser->tx) ||
1109 put_user(cnow.frame, &p_cuser->frame) ||
1110 put_user(cnow.overrun, &p_cuser->overrun) ||
1111 put_user(cnow.parity, &p_cuser->parity) ||
1112 put_user(cnow.brk, &p_cuser->brk) ||
1113 put_user(cnow.buf_overrun, &p_cuser->buf_overrun))
1114 ret = -EFAULT;
1115 ret = 0;
1116 break;
1117 default:
1118 ret = -ENOIOCTLCMD;
1119 }
1120 unlock_kernel();
1121 return ret;
1122 }
1123
1124 /*
1125 * support for 32 bit ioctl calls on 64 bit systems
1126 */
1127 #ifdef CONFIG_COMPAT
1128 static long get_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *user_params)
1129 {
1130 struct MGSL_PARAMS32 tmp_params;
1131
1132 DBGINFO(("%s get_params32\n", info->device_name));
1133 tmp_params.mode = (compat_ulong_t)info->params.mode;
1134 tmp_params.loopback = info->params.loopback;
1135 tmp_params.flags = info->params.flags;
1136 tmp_params.encoding = info->params.encoding;
1137 tmp_params.clock_speed = (compat_ulong_t)info->params.clock_speed;
1138 tmp_params.addr_filter = info->params.addr_filter;
1139 tmp_params.crc_type = info->params.crc_type;
1140 tmp_params.preamble_length = info->params.preamble_length;
1141 tmp_params.preamble = info->params.preamble;
1142 tmp_params.data_rate = (compat_ulong_t)info->params.data_rate;
1143 tmp_params.data_bits = info->params.data_bits;
1144 tmp_params.stop_bits = info->params.stop_bits;
1145 tmp_params.parity = info->params.parity;
1146 if (copy_to_user(user_params, &tmp_params, sizeof(struct MGSL_PARAMS32)))
1147 return -EFAULT;
1148 return 0;
1149 }
1150
1151 static long set_params32(struct slgt_info *info, struct MGSL_PARAMS32 __user *new_params)
1152 {
1153 struct MGSL_PARAMS32 tmp_params;
1154
1155 DBGINFO(("%s set_params32\n", info->device_name));
1156 if (copy_from_user(&tmp_params, new_params, sizeof(struct MGSL_PARAMS32)))
1157 return -EFAULT;
1158
1159 spin_lock(&info->lock);
1160 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK) {
1161 info->base_clock = tmp_params.clock_speed;
1162 } else {
1163 info->params.mode = tmp_params.mode;
1164 info->params.loopback = tmp_params.loopback;
1165 info->params.flags = tmp_params.flags;
1166 info->params.encoding = tmp_params.encoding;
1167 info->params.clock_speed = tmp_params.clock_speed;
1168 info->params.addr_filter = tmp_params.addr_filter;
1169 info->params.crc_type = tmp_params.crc_type;
1170 info->params.preamble_length = tmp_params.preamble_length;
1171 info->params.preamble = tmp_params.preamble;
1172 info->params.data_rate = tmp_params.data_rate;
1173 info->params.data_bits = tmp_params.data_bits;
1174 info->params.stop_bits = tmp_params.stop_bits;
1175 info->params.parity = tmp_params.parity;
1176 }
1177 spin_unlock(&info->lock);
1178
1179 program_hw(info);
1180
1181 return 0;
1182 }
1183
1184 static long slgt_compat_ioctl(struct tty_struct *tty, struct file *file,
1185 unsigned int cmd, unsigned long arg)
1186 {
1187 struct slgt_info *info = tty->driver_data;
1188 int rc = -ENOIOCTLCMD;
1189
1190 if (sanity_check(info, tty->name, "compat_ioctl"))
1191 return -ENODEV;
1192 DBGINFO(("%s compat_ioctl() cmd=%08X\n", info->device_name, cmd));
1193
1194 switch (cmd) {
1195
1196 case MGSL_IOCSPARAMS32:
1197 rc = set_params32(info, compat_ptr(arg));
1198 break;
1199
1200 case MGSL_IOCGPARAMS32:
1201 rc = get_params32(info, compat_ptr(arg));
1202 break;
1203
1204 case MGSL_IOCGPARAMS:
1205 case MGSL_IOCSPARAMS:
1206 case MGSL_IOCGTXIDLE:
1207 case MGSL_IOCGSTATS:
1208 case MGSL_IOCWAITEVENT:
1209 case MGSL_IOCGIF:
1210 case MGSL_IOCSGPIO:
1211 case MGSL_IOCGGPIO:
1212 case MGSL_IOCWAITGPIO:
1213 case TIOCGICOUNT:
1214 rc = ioctl(tty, file, cmd, (unsigned long)(compat_ptr(arg)));
1215 break;
1216
1217 case MGSL_IOCSTXIDLE:
1218 case MGSL_IOCTXENABLE:
1219 case MGSL_IOCRXENABLE:
1220 case MGSL_IOCTXABORT:
1221 case TIOCMIWAIT:
1222 case MGSL_IOCSIF:
1223 rc = ioctl(tty, file, cmd, arg);
1224 break;
1225 }
1226
1227 DBGINFO(("%s compat_ioctl() cmd=%08X rc=%d\n", info->device_name, cmd, rc));
1228 return rc;
1229 }
1230 #else
1231 #define slgt_compat_ioctl NULL
1232 #endif /* ifdef CONFIG_COMPAT */
1233
1234 /*
1235 * proc fs support
1236 */
1237 static inline void line_info(struct seq_file *m, struct slgt_info *info)
1238 {
1239 char stat_buf[30];
1240 unsigned long flags;
1241
1242 seq_printf(m, "%s: IO=%08X IRQ=%d MaxFrameSize=%u\n",
1243 info->device_name, info->phys_reg_addr,
1244 info->irq_level, info->max_frame_size);
1245
1246 /* output current serial signal states */
1247 spin_lock_irqsave(&info->lock,flags);
1248 get_signals(info);
1249 spin_unlock_irqrestore(&info->lock,flags);
1250
1251 stat_buf[0] = 0;
1252 stat_buf[1] = 0;
1253 if (info->signals & SerialSignal_RTS)
1254 strcat(stat_buf, "|RTS");
1255 if (info->signals & SerialSignal_CTS)
1256 strcat(stat_buf, "|CTS");
1257 if (info->signals & SerialSignal_DTR)
1258 strcat(stat_buf, "|DTR");
1259 if (info->signals & SerialSignal_DSR)
1260 strcat(stat_buf, "|DSR");
1261 if (info->signals & SerialSignal_DCD)
1262 strcat(stat_buf, "|CD");
1263 if (info->signals & SerialSignal_RI)
1264 strcat(stat_buf, "|RI");
1265
1266 if (info->params.mode != MGSL_MODE_ASYNC) {
1267 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1268 info->icount.txok, info->icount.rxok);
1269 if (info->icount.txunder)
1270 seq_printf(m, " txunder:%d", info->icount.txunder);
1271 if (info->icount.txabort)
1272 seq_printf(m, " txabort:%d", info->icount.txabort);
1273 if (info->icount.rxshort)
1274 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1275 if (info->icount.rxlong)
1276 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1277 if (info->icount.rxover)
1278 seq_printf(m, " rxover:%d", info->icount.rxover);
1279 if (info->icount.rxcrc)
1280 seq_printf(m, " rxcrc:%d", info->icount.rxcrc);
1281 } else {
1282 seq_printf(m, "\tASYNC tx:%d rx:%d",
1283 info->icount.tx, info->icount.rx);
1284 if (info->icount.frame)
1285 seq_printf(m, " fe:%d", info->icount.frame);
1286 if (info->icount.parity)
1287 seq_printf(m, " pe:%d", info->icount.parity);
1288 if (info->icount.brk)
1289 seq_printf(m, " brk:%d", info->icount.brk);
1290 if (info->icount.overrun)
1291 seq_printf(m, " oe:%d", info->icount.overrun);
1292 }
1293
1294 /* Append serial signal status to end */
1295 seq_printf(m, " %s\n", stat_buf+1);
1296
1297 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1298 info->tx_active,info->bh_requested,info->bh_running,
1299 info->pending_bh);
1300 }
1301
1302 /* Called to print information about devices
1303 */
1304 static int synclink_gt_proc_show(struct seq_file *m, void *v)
1305 {
1306 struct slgt_info *info;
1307
1308 seq_puts(m, "synclink_gt driver\n");
1309
1310 info = slgt_device_list;
1311 while( info ) {
1312 line_info(m, info);
1313 info = info->next_device;
1314 }
1315 return 0;
1316 }
1317
1318 static int synclink_gt_proc_open(struct inode *inode, struct file *file)
1319 {
1320 return single_open(file, synclink_gt_proc_show, NULL);
1321 }
1322
1323 static const struct file_operations synclink_gt_proc_fops = {
1324 .owner = THIS_MODULE,
1325 .open = synclink_gt_proc_open,
1326 .read = seq_read,
1327 .llseek = seq_lseek,
1328 .release = single_release,
1329 };
1330
1331 /*
1332 * return count of bytes in transmit buffer
1333 */
1334 static int chars_in_buffer(struct tty_struct *tty)
1335 {
1336 struct slgt_info *info = tty->driver_data;
1337 int count;
1338 if (sanity_check(info, tty->name, "chars_in_buffer"))
1339 return 0;
1340 count = tbuf_bytes(info);
1341 DBGINFO(("%s chars_in_buffer()=%d\n", info->device_name, count));
1342 return count;
1343 }
1344
1345 /*
1346 * signal remote device to throttle send data (our receive data)
1347 */
1348 static void throttle(struct tty_struct * tty)
1349 {
1350 struct slgt_info *info = tty->driver_data;
1351 unsigned long flags;
1352
1353 if (sanity_check(info, tty->name, "throttle"))
1354 return;
1355 DBGINFO(("%s throttle\n", info->device_name));
1356 if (I_IXOFF(tty))
1357 send_xchar(tty, STOP_CHAR(tty));
1358 if (tty->termios->c_cflag & CRTSCTS) {
1359 spin_lock_irqsave(&info->lock,flags);
1360 info->signals &= ~SerialSignal_RTS;
1361 set_signals(info);
1362 spin_unlock_irqrestore(&info->lock,flags);
1363 }
1364 }
1365
1366 /*
1367 * signal remote device to stop throttling send data (our receive data)
1368 */
1369 static void unthrottle(struct tty_struct * tty)
1370 {
1371 struct slgt_info *info = tty->driver_data;
1372 unsigned long flags;
1373
1374 if (sanity_check(info, tty->name, "unthrottle"))
1375 return;
1376 DBGINFO(("%s unthrottle\n", info->device_name));
1377 if (I_IXOFF(tty)) {
1378 if (info->x_char)
1379 info->x_char = 0;
1380 else
1381 send_xchar(tty, START_CHAR(tty));
1382 }
1383 if (tty->termios->c_cflag & CRTSCTS) {
1384 spin_lock_irqsave(&info->lock,flags);
1385 info->signals |= SerialSignal_RTS;
1386 set_signals(info);
1387 spin_unlock_irqrestore(&info->lock,flags);
1388 }
1389 }
1390
1391 /*
1392 * set or clear transmit break condition
1393 * break_state -1=set break condition, 0=clear
1394 */
1395 static int set_break(struct tty_struct *tty, int break_state)
1396 {
1397 struct slgt_info *info = tty->driver_data;
1398 unsigned short value;
1399 unsigned long flags;
1400
1401 if (sanity_check(info, tty->name, "set_break"))
1402 return -EINVAL;
1403 DBGINFO(("%s set_break(%d)\n", info->device_name, break_state));
1404
1405 spin_lock_irqsave(&info->lock,flags);
1406 value = rd_reg16(info, TCR);
1407 if (break_state == -1)
1408 value |= BIT6;
1409 else
1410 value &= ~BIT6;
1411 wr_reg16(info, TCR, value);
1412 spin_unlock_irqrestore(&info->lock,flags);
1413 return 0;
1414 }
1415
1416 #if SYNCLINK_GENERIC_HDLC
1417
1418 /**
1419 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1420 * set encoding and frame check sequence (FCS) options
1421 *
1422 * dev pointer to network device structure
1423 * encoding serial encoding setting
1424 * parity FCS setting
1425 *
1426 * returns 0 if success, otherwise error code
1427 */
1428 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1429 unsigned short parity)
1430 {
1431 struct slgt_info *info = dev_to_port(dev);
1432 unsigned char new_encoding;
1433 unsigned short new_crctype;
1434
1435 /* return error if TTY interface open */
1436 if (info->port.count)
1437 return -EBUSY;
1438
1439 DBGINFO(("%s hdlcdev_attach\n", info->device_name));
1440
1441 switch (encoding)
1442 {
1443 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1444 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1445 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1446 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1447 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1448 default: return -EINVAL;
1449 }
1450
1451 switch (parity)
1452 {
1453 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1454 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1455 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1456 default: return -EINVAL;
1457 }
1458
1459 info->params.encoding = new_encoding;
1460 info->params.crc_type = new_crctype;
1461
1462 /* if network interface up, reprogram hardware */
1463 if (info->netcount)
1464 program_hw(info);
1465
1466 return 0;
1467 }
1468
1469 /**
1470 * called by generic HDLC layer to send frame
1471 *
1472 * skb socket buffer containing HDLC frame
1473 * dev pointer to network device structure
1474 *
1475 * returns 0 if success, otherwise error code
1476 */
1477 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1478 {
1479 struct slgt_info *info = dev_to_port(dev);
1480 unsigned long flags;
1481
1482 DBGINFO(("%s hdlc_xmit\n", dev->name));
1483
1484 /* stop sending until this frame completes */
1485 netif_stop_queue(dev);
1486
1487 /* copy data to device buffers */
1488 info->tx_count = skb->len;
1489 tx_load(info, skb->data, skb->len);
1490
1491 /* update network statistics */
1492 dev->stats.tx_packets++;
1493 dev->stats.tx_bytes += skb->len;
1494
1495 /* done with socket buffer, so free it */
1496 dev_kfree_skb(skb);
1497
1498 /* save start time for transmit timeout detection */
1499 dev->trans_start = jiffies;
1500
1501 /* start hardware transmitter if necessary */
1502 spin_lock_irqsave(&info->lock,flags);
1503 if (!info->tx_active)
1504 tx_start(info);
1505 spin_unlock_irqrestore(&info->lock,flags);
1506
1507 return 0;
1508 }
1509
1510 /**
1511 * called by network layer when interface enabled
1512 * claim resources and initialize hardware
1513 *
1514 * dev pointer to network device structure
1515 *
1516 * returns 0 if success, otherwise error code
1517 */
1518 static int hdlcdev_open(struct net_device *dev)
1519 {
1520 struct slgt_info *info = dev_to_port(dev);
1521 int rc;
1522 unsigned long flags;
1523
1524 if (!try_module_get(THIS_MODULE))
1525 return -EBUSY;
1526
1527 DBGINFO(("%s hdlcdev_open\n", dev->name));
1528
1529 /* generic HDLC layer open processing */
1530 if ((rc = hdlc_open(dev)))
1531 return rc;
1532
1533 /* arbitrate between network and tty opens */
1534 spin_lock_irqsave(&info->netlock, flags);
1535 if (info->port.count != 0 || info->netcount != 0) {
1536 DBGINFO(("%s hdlc_open busy\n", dev->name));
1537 spin_unlock_irqrestore(&info->netlock, flags);
1538 return -EBUSY;
1539 }
1540 info->netcount=1;
1541 spin_unlock_irqrestore(&info->netlock, flags);
1542
1543 /* claim resources and init adapter */
1544 if ((rc = startup(info)) != 0) {
1545 spin_lock_irqsave(&info->netlock, flags);
1546 info->netcount=0;
1547 spin_unlock_irqrestore(&info->netlock, flags);
1548 return rc;
1549 }
1550
1551 /* assert DTR and RTS, apply hardware settings */
1552 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
1553 program_hw(info);
1554
1555 /* enable network layer transmit */
1556 dev->trans_start = jiffies;
1557 netif_start_queue(dev);
1558
1559 /* inform generic HDLC layer of current DCD status */
1560 spin_lock_irqsave(&info->lock, flags);
1561 get_signals(info);
1562 spin_unlock_irqrestore(&info->lock, flags);
1563 if (info->signals & SerialSignal_DCD)
1564 netif_carrier_on(dev);
1565 else
1566 netif_carrier_off(dev);
1567 return 0;
1568 }
1569
1570 /**
1571 * called by network layer when interface is disabled
1572 * shutdown hardware and release resources
1573 *
1574 * dev pointer to network device structure
1575 *
1576 * returns 0 if success, otherwise error code
1577 */
1578 static int hdlcdev_close(struct net_device *dev)
1579 {
1580 struct slgt_info *info = dev_to_port(dev);
1581 unsigned long flags;
1582
1583 DBGINFO(("%s hdlcdev_close\n", dev->name));
1584
1585 netif_stop_queue(dev);
1586
1587 /* shutdown adapter and release resources */
1588 shutdown(info);
1589
1590 hdlc_close(dev);
1591
1592 spin_lock_irqsave(&info->netlock, flags);
1593 info->netcount=0;
1594 spin_unlock_irqrestore(&info->netlock, flags);
1595
1596 module_put(THIS_MODULE);
1597 return 0;
1598 }
1599
1600 /**
1601 * called by network layer to process IOCTL call to network device
1602 *
1603 * dev pointer to network device structure
1604 * ifr pointer to network interface request structure
1605 * cmd IOCTL command code
1606 *
1607 * returns 0 if success, otherwise error code
1608 */
1609 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1610 {
1611 const size_t size = sizeof(sync_serial_settings);
1612 sync_serial_settings new_line;
1613 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1614 struct slgt_info *info = dev_to_port(dev);
1615 unsigned int flags;
1616
1617 DBGINFO(("%s hdlcdev_ioctl\n", dev->name));
1618
1619 /* return error if TTY interface open */
1620 if (info->port.count)
1621 return -EBUSY;
1622
1623 if (cmd != SIOCWANDEV)
1624 return hdlc_ioctl(dev, ifr, cmd);
1625
1626 switch(ifr->ifr_settings.type) {
1627 case IF_GET_IFACE: /* return current sync_serial_settings */
1628
1629 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1630 if (ifr->ifr_settings.size < size) {
1631 ifr->ifr_settings.size = size; /* data size wanted */
1632 return -ENOBUFS;
1633 }
1634
1635 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1636 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1637 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1638 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1639
1640 switch (flags){
1641 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1642 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1643 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1644 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1645 default: new_line.clock_type = CLOCK_DEFAULT;
1646 }
1647
1648 new_line.clock_rate = info->params.clock_speed;
1649 new_line.loopback = info->params.loopback ? 1:0;
1650
1651 if (copy_to_user(line, &new_line, size))
1652 return -EFAULT;
1653 return 0;
1654
1655 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1656
1657 if(!capable(CAP_NET_ADMIN))
1658 return -EPERM;
1659 if (copy_from_user(&new_line, line, size))
1660 return -EFAULT;
1661
1662 switch (new_line.clock_type)
1663 {
1664 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1665 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1666 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1667 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1668 case CLOCK_DEFAULT: flags = info->params.flags &
1669 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1670 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1671 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1672 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1673 default: return -EINVAL;
1674 }
1675
1676 if (new_line.loopback != 0 && new_line.loopback != 1)
1677 return -EINVAL;
1678
1679 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1680 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1681 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1682 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1683 info->params.flags |= flags;
1684
1685 info->params.loopback = new_line.loopback;
1686
1687 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1688 info->params.clock_speed = new_line.clock_rate;
1689 else
1690 info->params.clock_speed = 0;
1691
1692 /* if network interface up, reprogram hardware */
1693 if (info->netcount)
1694 program_hw(info);
1695 return 0;
1696
1697 default:
1698 return hdlc_ioctl(dev, ifr, cmd);
1699 }
1700 }
1701
1702 /**
1703 * called by network layer when transmit timeout is detected
1704 *
1705 * dev pointer to network device structure
1706 */
1707 static void hdlcdev_tx_timeout(struct net_device *dev)
1708 {
1709 struct slgt_info *info = dev_to_port(dev);
1710 unsigned long flags;
1711
1712 DBGINFO(("%s hdlcdev_tx_timeout\n", dev->name));
1713
1714 dev->stats.tx_errors++;
1715 dev->stats.tx_aborted_errors++;
1716
1717 spin_lock_irqsave(&info->lock,flags);
1718 tx_stop(info);
1719 spin_unlock_irqrestore(&info->lock,flags);
1720
1721 netif_wake_queue(dev);
1722 }
1723
1724 /**
1725 * called by device driver when transmit completes
1726 * reenable network layer transmit if stopped
1727 *
1728 * info pointer to device instance information
1729 */
1730 static void hdlcdev_tx_done(struct slgt_info *info)
1731 {
1732 if (netif_queue_stopped(info->netdev))
1733 netif_wake_queue(info->netdev);
1734 }
1735
1736 /**
1737 * called by device driver when frame received
1738 * pass frame to network layer
1739 *
1740 * info pointer to device instance information
1741 * buf pointer to buffer contianing frame data
1742 * size count of data bytes in buf
1743 */
1744 static void hdlcdev_rx(struct slgt_info *info, char *buf, int size)
1745 {
1746 struct sk_buff *skb = dev_alloc_skb(size);
1747 struct net_device *dev = info->netdev;
1748
1749 DBGINFO(("%s hdlcdev_rx\n", dev->name));
1750
1751 if (skb == NULL) {
1752 DBGERR(("%s: can't alloc skb, drop packet\n", dev->name));
1753 dev->stats.rx_dropped++;
1754 return;
1755 }
1756
1757 memcpy(skb_put(skb, size), buf, size);
1758
1759 skb->protocol = hdlc_type_trans(skb, dev);
1760
1761 dev->stats.rx_packets++;
1762 dev->stats.rx_bytes += size;
1763
1764 netif_rx(skb);
1765 }
1766
1767 static const struct net_device_ops hdlcdev_ops = {
1768 .ndo_open = hdlcdev_open,
1769 .ndo_stop = hdlcdev_close,
1770 .ndo_change_mtu = hdlc_change_mtu,
1771 .ndo_start_xmit = hdlc_start_xmit,
1772 .ndo_do_ioctl = hdlcdev_ioctl,
1773 .ndo_tx_timeout = hdlcdev_tx_timeout,
1774 };
1775
1776 /**
1777 * called by device driver when adding device instance
1778 * do generic HDLC initialization
1779 *
1780 * info pointer to device instance information
1781 *
1782 * returns 0 if success, otherwise error code
1783 */
1784 static int hdlcdev_init(struct slgt_info *info)
1785 {
1786 int rc;
1787 struct net_device *dev;
1788 hdlc_device *hdlc;
1789
1790 /* allocate and initialize network and HDLC layer objects */
1791
1792 if (!(dev = alloc_hdlcdev(info))) {
1793 printk(KERN_ERR "%s hdlc device alloc failure\n", info->device_name);
1794 return -ENOMEM;
1795 }
1796
1797 /* for network layer reporting purposes only */
1798 dev->mem_start = info->phys_reg_addr;
1799 dev->mem_end = info->phys_reg_addr + SLGT_REG_SIZE - 1;
1800 dev->irq = info->irq_level;
1801
1802 /* network layer callbacks and settings */
1803 dev->netdev_ops = &hdlcdev_ops;
1804 dev->watchdog_timeo = 10 * HZ;
1805 dev->tx_queue_len = 50;
1806
1807 /* generic HDLC layer callbacks and settings */
1808 hdlc = dev_to_hdlc(dev);
1809 hdlc->attach = hdlcdev_attach;
1810 hdlc->xmit = hdlcdev_xmit;
1811
1812 /* register objects with HDLC layer */
1813 if ((rc = register_hdlc_device(dev))) {
1814 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1815 free_netdev(dev);
1816 return rc;
1817 }
1818
1819 info->netdev = dev;
1820 return 0;
1821 }
1822
1823 /**
1824 * called by device driver when removing device instance
1825 * do generic HDLC cleanup
1826 *
1827 * info pointer to device instance information
1828 */
1829 static void hdlcdev_exit(struct slgt_info *info)
1830 {
1831 unregister_hdlc_device(info->netdev);
1832 free_netdev(info->netdev);
1833 info->netdev = NULL;
1834 }
1835
1836 #endif /* ifdef CONFIG_HDLC */
1837
1838 /*
1839 * get async data from rx DMA buffers
1840 */
1841 static void rx_async(struct slgt_info *info)
1842 {
1843 struct tty_struct *tty = info->port.tty;
1844 struct mgsl_icount *icount = &info->icount;
1845 unsigned int start, end;
1846 unsigned char *p;
1847 unsigned char status;
1848 struct slgt_desc *bufs = info->rbufs;
1849 int i, count;
1850 int chars = 0;
1851 int stat;
1852 unsigned char ch;
1853
1854 start = end = info->rbuf_current;
1855
1856 while(desc_complete(bufs[end])) {
1857 count = desc_count(bufs[end]) - info->rbuf_index;
1858 p = bufs[end].buf + info->rbuf_index;
1859
1860 DBGISR(("%s rx_async count=%d\n", info->device_name, count));
1861 DBGDATA(info, p, count, "rx");
1862
1863 for(i=0 ; i < count; i+=2, p+=2) {
1864 ch = *p;
1865 icount->rx++;
1866
1867 stat = 0;
1868
1869 if ((status = *(p+1) & (BIT1 + BIT0))) {
1870 if (status & BIT1)
1871 icount->parity++;
1872 else if (status & BIT0)
1873 icount->frame++;
1874 /* discard char if tty control flags say so */
1875 if (status & info->ignore_status_mask)
1876 continue;
1877 if (status & BIT1)
1878 stat = TTY_PARITY;
1879 else if (status & BIT0)
1880 stat = TTY_FRAME;
1881 }
1882 if (tty) {
1883 tty_insert_flip_char(tty, ch, stat);
1884 chars++;
1885 }
1886 }
1887
1888 if (i < count) {
1889 /* receive buffer not completed */
1890 info->rbuf_index += i;
1891 mod_timer(&info->rx_timer, jiffies + 1);
1892 break;
1893 }
1894
1895 info->rbuf_index = 0;
1896 free_rbufs(info, end, end);
1897
1898 if (++end == info->rbuf_count)
1899 end = 0;
1900
1901 /* if entire list searched then no frame available */
1902 if (end == start)
1903 break;
1904 }
1905
1906 if (tty && chars)
1907 tty_flip_buffer_push(tty);
1908 }
1909
1910 /*
1911 * return next bottom half action to perform
1912 */
1913 static int bh_action(struct slgt_info *info)
1914 {
1915 unsigned long flags;
1916 int rc;
1917
1918 spin_lock_irqsave(&info->lock,flags);
1919
1920 if (info->pending_bh & BH_RECEIVE) {
1921 info->pending_bh &= ~BH_RECEIVE;
1922 rc = BH_RECEIVE;
1923 } else if (info->pending_bh & BH_TRANSMIT) {
1924 info->pending_bh &= ~BH_TRANSMIT;
1925 rc = BH_TRANSMIT;
1926 } else if (info->pending_bh & BH_STATUS) {
1927 info->pending_bh &= ~BH_STATUS;
1928 rc = BH_STATUS;
1929 } else {
1930 /* Mark BH routine as complete */
1931 info->bh_running = false;
1932 info->bh_requested = false;
1933 rc = 0;
1934 }
1935
1936 spin_unlock_irqrestore(&info->lock,flags);
1937
1938 return rc;
1939 }
1940
1941 /*
1942 * perform bottom half processing
1943 */
1944 static void bh_handler(struct work_struct *work)
1945 {
1946 struct slgt_info *info = container_of(work, struct slgt_info, task);
1947 int action;
1948
1949 if (!info)
1950 return;
1951 info->bh_running = true;
1952
1953 while((action = bh_action(info))) {
1954 switch (action) {
1955 case BH_RECEIVE:
1956 DBGBH(("%s bh receive\n", info->device_name));
1957 switch(info->params.mode) {
1958 case MGSL_MODE_ASYNC:
1959 rx_async(info);
1960 break;
1961 case MGSL_MODE_HDLC:
1962 while(rx_get_frame(info));
1963 break;
1964 case MGSL_MODE_RAW:
1965 case MGSL_MODE_MONOSYNC:
1966 case MGSL_MODE_BISYNC:
1967 while(rx_get_buf(info));
1968 break;
1969 }
1970 /* restart receiver if rx DMA buffers exhausted */
1971 if (info->rx_restart)
1972 rx_start(info);
1973 break;
1974 case BH_TRANSMIT:
1975 bh_transmit(info);
1976 break;
1977 case BH_STATUS:
1978 DBGBH(("%s bh status\n", info->device_name));
1979 info->ri_chkcount = 0;
1980 info->dsr_chkcount = 0;
1981 info->dcd_chkcount = 0;
1982 info->cts_chkcount = 0;
1983 break;
1984 default:
1985 DBGBH(("%s unknown action\n", info->device_name));
1986 break;
1987 }
1988 }
1989 DBGBH(("%s bh_handler exit\n", info->device_name));
1990 }
1991
1992 static void bh_transmit(struct slgt_info *info)
1993 {
1994 struct tty_struct *tty = info->port.tty;
1995
1996 DBGBH(("%s bh_transmit\n", info->device_name));
1997 if (tty)
1998 tty_wakeup(tty);
1999 }
2000
2001 static void dsr_change(struct slgt_info *info, unsigned short status)
2002 {
2003 if (status & BIT3) {
2004 info->signals |= SerialSignal_DSR;
2005 info->input_signal_events.dsr_up++;
2006 } else {
2007 info->signals &= ~SerialSignal_DSR;
2008 info->input_signal_events.dsr_down++;
2009 }
2010 DBGISR(("dsr_change %s signals=%04X\n", info->device_name, info->signals));
2011 if ((info->dsr_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2012 slgt_irq_off(info, IRQ_DSR);
2013 return;
2014 }
2015 info->icount.dsr++;
2016 wake_up_interruptible(&info->status_event_wait_q);
2017 wake_up_interruptible(&info->event_wait_q);
2018 info->pending_bh |= BH_STATUS;
2019 }
2020
2021 static void cts_change(struct slgt_info *info, unsigned short status)
2022 {
2023 if (status & BIT2) {
2024 info->signals |= SerialSignal_CTS;
2025 info->input_signal_events.cts_up++;
2026 } else {
2027 info->signals &= ~SerialSignal_CTS;
2028 info->input_signal_events.cts_down++;
2029 }
2030 DBGISR(("cts_change %s signals=%04X\n", info->device_name, info->signals));
2031 if ((info->cts_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2032 slgt_irq_off(info, IRQ_CTS);
2033 return;
2034 }
2035 info->icount.cts++;
2036 wake_up_interruptible(&info->status_event_wait_q);
2037 wake_up_interruptible(&info->event_wait_q);
2038 info->pending_bh |= BH_STATUS;
2039
2040 if (info->port.flags & ASYNC_CTS_FLOW) {
2041 if (info->port.tty) {
2042 if (info->port.tty->hw_stopped) {
2043 if (info->signals & SerialSignal_CTS) {
2044 info->port.tty->hw_stopped = 0;
2045 info->pending_bh |= BH_TRANSMIT;
2046 return;
2047 }
2048 } else {
2049 if (!(info->signals & SerialSignal_CTS))
2050 info->port.tty->hw_stopped = 1;
2051 }
2052 }
2053 }
2054 }
2055
2056 static void dcd_change(struct slgt_info *info, unsigned short status)
2057 {
2058 if (status & BIT1) {
2059 info->signals |= SerialSignal_DCD;
2060 info->input_signal_events.dcd_up++;
2061 } else {
2062 info->signals &= ~SerialSignal_DCD;
2063 info->input_signal_events.dcd_down++;
2064 }
2065 DBGISR(("dcd_change %s signals=%04X\n", info->device_name, info->signals));
2066 if ((info->dcd_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2067 slgt_irq_off(info, IRQ_DCD);
2068 return;
2069 }
2070 info->icount.dcd++;
2071 #if SYNCLINK_GENERIC_HDLC
2072 if (info->netcount) {
2073 if (info->signals & SerialSignal_DCD)
2074 netif_carrier_on(info->netdev);
2075 else
2076 netif_carrier_off(info->netdev);
2077 }
2078 #endif
2079 wake_up_interruptible(&info->status_event_wait_q);
2080 wake_up_interruptible(&info->event_wait_q);
2081 info->pending_bh |= BH_STATUS;
2082
2083 if (info->port.flags & ASYNC_CHECK_CD) {
2084 if (info->signals & SerialSignal_DCD)
2085 wake_up_interruptible(&info->port.open_wait);
2086 else {
2087 if (info->port.tty)
2088 tty_hangup(info->port.tty);
2089 }
2090 }
2091 }
2092
2093 static void ri_change(struct slgt_info *info, unsigned short status)
2094 {
2095 if (status & BIT0) {
2096 info->signals |= SerialSignal_RI;
2097 info->input_signal_events.ri_up++;
2098 } else {
2099 info->signals &= ~SerialSignal_RI;
2100 info->input_signal_events.ri_down++;
2101 }
2102 DBGISR(("ri_change %s signals=%04X\n", info->device_name, info->signals));
2103 if ((info->ri_chkcount)++ == IO_PIN_SHUTDOWN_LIMIT) {
2104 slgt_irq_off(info, IRQ_RI);
2105 return;
2106 }
2107 info->icount.rng++;
2108 wake_up_interruptible(&info->status_event_wait_q);
2109 wake_up_interruptible(&info->event_wait_q);
2110 info->pending_bh |= BH_STATUS;
2111 }
2112
2113 static void isr_serial(struct slgt_info *info)
2114 {
2115 unsigned short status = rd_reg16(info, SSR);
2116
2117 DBGISR(("%s isr_serial status=%04X\n", info->device_name, status));
2118
2119 wr_reg16(info, SSR, status); /* clear pending */
2120
2121 info->irq_occurred = true;
2122
2123 if (info->params.mode == MGSL_MODE_ASYNC) {
2124 if (status & IRQ_TXIDLE) {
2125 if (info->tx_count)
2126 isr_txeom(info, status);
2127 }
2128 if ((status & IRQ_RXBREAK) && (status & RXBREAK)) {
2129 info->icount.brk++;
2130 /* process break detection if tty control allows */
2131 if (info->port.tty) {
2132 if (!(status & info->ignore_status_mask)) {
2133 if (info->read_status_mask & MASK_BREAK) {
2134 tty_insert_flip_char(info->port.tty, 0, TTY_BREAK);
2135 if (info->port.flags & ASYNC_SAK)
2136 do_SAK(info->port.tty);
2137 }
2138 }
2139 }
2140 }
2141 } else {
2142 if (status & (IRQ_TXIDLE + IRQ_TXUNDER))
2143 isr_txeom(info, status);
2144
2145 if (status & IRQ_RXIDLE) {
2146 if (status & RXIDLE)
2147 info->icount.rxidle++;
2148 else
2149 info->icount.exithunt++;
2150 wake_up_interruptible(&info->event_wait_q);
2151 }
2152
2153 if (status & IRQ_RXOVER)
2154 rx_start(info);
2155 }
2156
2157 if (status & IRQ_DSR)
2158 dsr_change(info, status);
2159 if (status & IRQ_CTS)
2160 cts_change(info, status);
2161 if (status & IRQ_DCD)
2162 dcd_change(info, status);
2163 if (status & IRQ_RI)
2164 ri_change(info, status);
2165 }
2166
2167 static void isr_rdma(struct slgt_info *info)
2168 {
2169 unsigned int status = rd_reg32(info, RDCSR);
2170
2171 DBGISR(("%s isr_rdma status=%08x\n", info->device_name, status));
2172
2173 /* RDCSR (rx DMA control/status)
2174 *
2175 * 31..07 reserved
2176 * 06 save status byte to DMA buffer
2177 * 05 error
2178 * 04 eol (end of list)
2179 * 03 eob (end of buffer)
2180 * 02 IRQ enable
2181 * 01 reset
2182 * 00 enable
2183 */
2184 wr_reg32(info, RDCSR, status); /* clear pending */
2185
2186 if (status & (BIT5 + BIT4)) {
2187 DBGISR(("%s isr_rdma rx_restart=1\n", info->device_name));
2188 info->rx_restart = true;
2189 }
2190 info->pending_bh |= BH_RECEIVE;
2191 }
2192
2193 static void isr_tdma(struct slgt_info *info)
2194 {
2195 unsigned int status = rd_reg32(info, TDCSR);
2196
2197 DBGISR(("%s isr_tdma status=%08x\n", info->device_name, status));
2198
2199 /* TDCSR (tx DMA control/status)
2200 *
2201 * 31..06 reserved
2202 * 05 error
2203 * 04 eol (end of list)
2204 * 03 eob (end of buffer)
2205 * 02 IRQ enable
2206 * 01 reset
2207 * 00 enable
2208 */
2209 wr_reg32(info, TDCSR, status); /* clear pending */
2210
2211 if (status & (BIT5 + BIT4 + BIT3)) {
2212 // another transmit buffer has completed
2213 // run bottom half to get more send data from user
2214 info->pending_bh |= BH_TRANSMIT;
2215 }
2216 }
2217
2218 static void isr_txeom(struct slgt_info *info, unsigned short status)
2219 {
2220 DBGISR(("%s txeom status=%04x\n", info->device_name, status));
2221
2222 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
2223 tdma_reset(info);
2224 reset_tbufs(info);
2225 if (status & IRQ_TXUNDER) {
2226 unsigned short val = rd_reg16(info, TCR);
2227 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
2228 wr_reg16(info, TCR, val); /* clear reset bit */
2229 }
2230
2231 if (info->tx_active) {
2232 if (info->params.mode != MGSL_MODE_ASYNC) {
2233 if (status & IRQ_TXUNDER)
2234 info->icount.txunder++;
2235 else if (status & IRQ_TXIDLE)
2236 info->icount.txok++;
2237 }
2238
2239 info->tx_active = false;
2240 info->tx_count = 0;
2241
2242 del_timer(&info->tx_timer);
2243
2244 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done) {
2245 info->signals &= ~SerialSignal_RTS;
2246 info->drop_rts_on_tx_done = false;
2247 set_signals(info);
2248 }
2249
2250 #if SYNCLINK_GENERIC_HDLC
2251 if (info->netcount)
2252 hdlcdev_tx_done(info);
2253 else
2254 #endif
2255 {
2256 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2257 tx_stop(info);
2258 return;
2259 }
2260 info->pending_bh |= BH_TRANSMIT;
2261 }
2262 }
2263 }
2264
2265 static void isr_gpio(struct slgt_info *info, unsigned int changed, unsigned int state)
2266 {
2267 struct cond_wait *w, *prev;
2268
2269 /* wake processes waiting for specific transitions */
2270 for (w = info->gpio_wait_q, prev = NULL ; w != NULL ; w = w->next) {
2271 if (w->data & changed) {
2272 w->data = state;
2273 wake_up_interruptible(&w->q);
2274 if (prev != NULL)
2275 prev->next = w->next;
2276 else
2277 info->gpio_wait_q = w->next;
2278 } else
2279 prev = w;
2280 }
2281 }
2282
2283 /* interrupt service routine
2284 *
2285 * irq interrupt number
2286 * dev_id device ID supplied during interrupt registration
2287 */
2288 static irqreturn_t slgt_interrupt(int dummy, void *dev_id)
2289 {
2290 struct slgt_info *info = dev_id;
2291 unsigned int gsr;
2292 unsigned int i;
2293
2294 DBGISR(("slgt_interrupt irq=%d entry\n", info->irq_level));
2295
2296 spin_lock(&info->lock);
2297
2298 while((gsr = rd_reg32(info, GSR) & 0xffffff00)) {
2299 DBGISR(("%s gsr=%08x\n", info->device_name, gsr));
2300 info->irq_occurred = true;
2301 for(i=0; i < info->port_count ; i++) {
2302 if (info->port_array[i] == NULL)
2303 continue;
2304 if (gsr & (BIT8 << i))
2305 isr_serial(info->port_array[i]);
2306 if (gsr & (BIT16 << (i*2)))
2307 isr_rdma(info->port_array[i]);
2308 if (gsr & (BIT17 << (i*2)))
2309 isr_tdma(info->port_array[i]);
2310 }
2311 }
2312
2313 if (info->gpio_present) {
2314 unsigned int state;
2315 unsigned int changed;
2316 while ((changed = rd_reg32(info, IOSR)) != 0) {
2317 DBGISR(("%s iosr=%08x\n", info->device_name, changed));
2318 /* read latched state of GPIO signals */
2319 state = rd_reg32(info, IOVR);
2320 /* clear pending GPIO interrupt bits */
2321 wr_reg32(info, IOSR, changed);
2322 for (i=0 ; i < info->port_count ; i++) {
2323 if (info->port_array[i] != NULL)
2324 isr_gpio(info->port_array[i], changed, state);
2325 }
2326 }
2327 }
2328
2329 for(i=0; i < info->port_count ; i++) {
2330 struct slgt_info *port = info->port_array[i];
2331
2332 if (port && (port->port.count || port->netcount) &&
2333 port->pending_bh && !port->bh_running &&
2334 !port->bh_requested) {
2335 DBGISR(("%s bh queued\n", port->device_name));
2336 schedule_work(&port->task);
2337 port->bh_requested = true;
2338 }
2339 }
2340
2341 spin_unlock(&info->lock);
2342
2343 DBGISR(("slgt_interrupt irq=%d exit\n", info->irq_level));
2344 return IRQ_HANDLED;
2345 }
2346
2347 static int startup(struct slgt_info *info)
2348 {
2349 DBGINFO(("%s startup\n", info->device_name));
2350
2351 if (info->port.flags & ASYNC_INITIALIZED)
2352 return 0;
2353
2354 if (!info->tx_buf) {
2355 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2356 if (!info->tx_buf) {
2357 DBGERR(("%s can't allocate tx buffer\n", info->device_name));
2358 return -ENOMEM;
2359 }
2360 }
2361
2362 info->pending_bh = 0;
2363
2364 memset(&info->icount, 0, sizeof(info->icount));
2365
2366 /* program hardware for current parameters */
2367 change_params(info);
2368
2369 if (info->port.tty)
2370 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2371
2372 info->port.flags |= ASYNC_INITIALIZED;
2373
2374 return 0;
2375 }
2376
2377 /*
2378 * called by close() and hangup() to shutdown hardware
2379 */
2380 static void shutdown(struct slgt_info *info)
2381 {
2382 unsigned long flags;
2383
2384 if (!(info->port.flags & ASYNC_INITIALIZED))
2385 return;
2386
2387 DBGINFO(("%s shutdown\n", info->device_name));
2388
2389 /* clear status wait queue because status changes */
2390 /* can't happen after shutting down the hardware */
2391 wake_up_interruptible(&info->status_event_wait_q);
2392 wake_up_interruptible(&info->event_wait_q);
2393
2394 del_timer_sync(&info->tx_timer);
2395 del_timer_sync(&info->rx_timer);
2396
2397 kfree(info->tx_buf);
2398 info->tx_buf = NULL;
2399
2400 spin_lock_irqsave(&info->lock,flags);
2401
2402 tx_stop(info);
2403 rx_stop(info);
2404
2405 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
2406
2407 if (!info->port.tty || info->port.tty->termios->c_cflag & HUPCL) {
2408 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2409 set_signals(info);
2410 }
2411
2412 flush_cond_wait(&info->gpio_wait_q);
2413
2414 spin_unlock_irqrestore(&info->lock,flags);
2415
2416 if (info->port.tty)
2417 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2418
2419 info->port.flags &= ~ASYNC_INITIALIZED;
2420 }
2421
2422 static void program_hw(struct slgt_info *info)
2423 {
2424 unsigned long flags;
2425
2426 spin_lock_irqsave(&info->lock,flags);
2427
2428 rx_stop(info);
2429 tx_stop(info);
2430
2431 if (info->params.mode != MGSL_MODE_ASYNC ||
2432 info->netcount)
2433 sync_mode(info);
2434 else
2435 async_mode(info);
2436
2437 set_signals(info);
2438
2439 info->dcd_chkcount = 0;
2440 info->cts_chkcount = 0;
2441 info->ri_chkcount = 0;
2442 info->dsr_chkcount = 0;
2443
2444 slgt_irq_on(info, IRQ_DCD | IRQ_CTS | IRQ_DSR | IRQ_RI);
2445 get_signals(info);
2446
2447 if (info->netcount ||
2448 (info->port.tty && info->port.tty->termios->c_cflag & CREAD))
2449 rx_start(info);
2450
2451 spin_unlock_irqrestore(&info->lock,flags);
2452 }
2453
2454 /*
2455 * reconfigure adapter based on new parameters
2456 */
2457 static void change_params(struct slgt_info *info)
2458 {
2459 unsigned cflag;
2460 int bits_per_char;
2461
2462 if (!info->port.tty || !info->port.tty->termios)
2463 return;
2464 DBGINFO(("%s change_params\n", info->device_name));
2465
2466 cflag = info->port.tty->termios->c_cflag;
2467
2468 /* if B0 rate (hangup) specified then negate DTR and RTS */
2469 /* otherwise assert DTR and RTS */
2470 if (cflag & CBAUD)
2471 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
2472 else
2473 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2474
2475 /* byte size and parity */
2476
2477 switch (cflag & CSIZE) {
2478 case CS5: info->params.data_bits = 5; break;
2479 case CS6: info->params.data_bits = 6; break;
2480 case CS7: info->params.data_bits = 7; break;
2481 case CS8: info->params.data_bits = 8; break;
2482 default: info->params.data_bits = 7; break;
2483 }
2484
2485 info->params.stop_bits = (cflag & CSTOPB) ? 2 : 1;
2486
2487 if (cflag & PARENB)
2488 info->params.parity = (cflag & PARODD) ? ASYNC_PARITY_ODD : ASYNC_PARITY_EVEN;
2489 else
2490 info->params.parity = ASYNC_PARITY_NONE;
2491
2492 /* calculate number of jiffies to transmit a full
2493 * FIFO (32 bytes) at specified data rate
2494 */
2495 bits_per_char = info->params.data_bits +
2496 info->params.stop_bits + 1;
2497
2498 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2499
2500 if (info->params.data_rate) {
2501 info->timeout = (32*HZ*bits_per_char) /
2502 info->params.data_rate;
2503 }
2504 info->timeout += HZ/50; /* Add .02 seconds of slop */
2505
2506 if (cflag & CRTSCTS)
2507 info->port.flags |= ASYNC_CTS_FLOW;
2508 else
2509 info->port.flags &= ~ASYNC_CTS_FLOW;
2510
2511 if (cflag & CLOCAL)
2512 info->port.flags &= ~ASYNC_CHECK_CD;
2513 else
2514 info->port.flags |= ASYNC_CHECK_CD;
2515
2516 /* process tty input control flags */
2517
2518 info->read_status_mask = IRQ_RXOVER;
2519 if (I_INPCK(info->port.tty))
2520 info->read_status_mask |= MASK_PARITY | MASK_FRAMING;
2521 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2522 info->read_status_mask |= MASK_BREAK;
2523 if (I_IGNPAR(info->port.tty))
2524 info->ignore_status_mask |= MASK_PARITY | MASK_FRAMING;
2525 if (I_IGNBRK(info->port.tty)) {
2526 info->ignore_status_mask |= MASK_BREAK;
2527 /* If ignoring parity and break indicators, ignore
2528 * overruns too. (For real raw support).
2529 */
2530 if (I_IGNPAR(info->port.tty))
2531 info->ignore_status_mask |= MASK_OVERRUN;
2532 }
2533
2534 program_hw(info);
2535 }
2536
2537 static int get_stats(struct slgt_info *info, struct mgsl_icount __user *user_icount)
2538 {
2539 DBGINFO(("%s get_stats\n", info->device_name));
2540 if (!user_icount) {
2541 memset(&info->icount, 0, sizeof(info->icount));
2542 } else {
2543 if (copy_to_user(user_icount, &info->icount, sizeof(struct mgsl_icount)))
2544 return -EFAULT;
2545 }
2546 return 0;
2547 }
2548
2549 static int get_params(struct slgt_info *info, MGSL_PARAMS __user *user_params)
2550 {
2551 DBGINFO(("%s get_params\n", info->device_name));
2552 if (copy_to_user(user_params, &info->params, sizeof(MGSL_PARAMS)))
2553 return -EFAULT;
2554 return 0;
2555 }
2556
2557 static int set_params(struct slgt_info *info, MGSL_PARAMS __user *new_params)
2558 {
2559 unsigned long flags;
2560 MGSL_PARAMS tmp_params;
2561
2562 DBGINFO(("%s set_params\n", info->device_name));
2563 if (copy_from_user(&tmp_params, new_params, sizeof(MGSL_PARAMS)))
2564 return -EFAULT;
2565
2566 spin_lock_irqsave(&info->lock, flags);
2567 if (tmp_params.mode == MGSL_MODE_BASE_CLOCK)
2568 info->base_clock = tmp_params.clock_speed;
2569 else
2570 memcpy(&info->params, &tmp_params, sizeof(MGSL_PARAMS));
2571 spin_unlock_irqrestore(&info->lock, flags);
2572
2573 program_hw(info);
2574
2575 return 0;
2576 }
2577
2578 static int get_txidle(struct slgt_info *info, int __user *idle_mode)
2579 {
2580 DBGINFO(("%s get_txidle=%d\n", info->device_name, info->idle_mode));
2581 if (put_user(info->idle_mode, idle_mode))
2582 return -EFAULT;
2583 return 0;
2584 }
2585
2586 static int set_txidle(struct slgt_info *info, int idle_mode)
2587 {
2588 unsigned long flags;
2589 DBGINFO(("%s set_txidle(%d)\n", info->device_name, idle_mode));
2590 spin_lock_irqsave(&info->lock,flags);
2591 info->idle_mode = idle_mode;
2592 if (info->params.mode != MGSL_MODE_ASYNC)
2593 tx_set_idle(info);
2594 spin_unlock_irqrestore(&info->lock,flags);
2595 return 0;
2596 }
2597
2598 static int tx_enable(struct slgt_info *info, int enable)
2599 {
2600 unsigned long flags;
2601 DBGINFO(("%s tx_enable(%d)\n", info->device_name, enable));
2602 spin_lock_irqsave(&info->lock,flags);
2603 if (enable) {
2604 if (!info->tx_enabled)
2605 tx_start(info);
2606 } else {
2607 if (info->tx_enabled)
2608 tx_stop(info);
2609 }
2610 spin_unlock_irqrestore(&info->lock,flags);
2611 return 0;
2612 }
2613
2614 /*
2615 * abort transmit HDLC frame
2616 */
2617 static int tx_abort(struct slgt_info *info)
2618 {
2619 unsigned long flags;
2620 DBGINFO(("%s tx_abort\n", info->device_name));
2621 spin_lock_irqsave(&info->lock,flags);
2622 tdma_reset(info);
2623 spin_unlock_irqrestore(&info->lock,flags);
2624 return 0;
2625 }
2626
2627 static int rx_enable(struct slgt_info *info, int enable)
2628 {
2629 unsigned long flags;
2630 unsigned int rbuf_fill_level;
2631 DBGINFO(("%s rx_enable(%08x)\n", info->device_name, enable));
2632 spin_lock_irqsave(&info->lock,flags);
2633 /*
2634 * enable[31..16] = receive DMA buffer fill level
2635 * 0 = noop (leave fill level unchanged)
2636 * fill level must be multiple of 4 and <= buffer size
2637 */
2638 rbuf_fill_level = ((unsigned int)enable) >> 16;
2639 if (rbuf_fill_level) {
2640 if ((rbuf_fill_level > DMABUFSIZE) || (rbuf_fill_level % 4)) {
2641 spin_unlock_irqrestore(&info->lock, flags);
2642 return -EINVAL;
2643 }
2644 info->rbuf_fill_level = rbuf_fill_level;
2645 rx_stop(info); /* restart receiver to use new fill level */
2646 }
2647
2648 /*
2649 * enable[1..0] = receiver enable command
2650 * 0 = disable
2651 * 1 = enable
2652 * 2 = enable or force hunt mode if already enabled
2653 */
2654 enable &= 3;
2655 if (enable) {
2656 if (!info->rx_enabled)
2657 rx_start(info);
2658 else if (enable == 2) {
2659 /* force hunt mode (write 1 to RCR[3]) */
2660 wr_reg16(info, RCR, rd_reg16(info, RCR) | BIT3);
2661 }
2662 } else {
2663 if (info->rx_enabled)
2664 rx_stop(info);
2665 }
2666 spin_unlock_irqrestore(&info->lock,flags);
2667 return 0;
2668 }
2669
2670 /*
2671 * wait for specified event to occur
2672 */
2673 static int wait_mgsl_event(struct slgt_info *info, int __user *mask_ptr)
2674 {
2675 unsigned long flags;
2676 int s;
2677 int rc=0;
2678 struct mgsl_icount cprev, cnow;
2679 int events;
2680 int mask;
2681 struct _input_signal_events oldsigs, newsigs;
2682 DECLARE_WAITQUEUE(wait, current);
2683
2684 if (get_user(mask, mask_ptr))
2685 return -EFAULT;
2686
2687 DBGINFO(("%s wait_mgsl_event(%d)\n", info->device_name, mask));
2688
2689 spin_lock_irqsave(&info->lock,flags);
2690
2691 /* return immediately if state matches requested events */
2692 get_signals(info);
2693 s = info->signals;
2694
2695 events = mask &
2696 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2697 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2698 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2699 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2700 if (events) {
2701 spin_unlock_irqrestore(&info->lock,flags);
2702 goto exit;
2703 }
2704
2705 /* save current irq counts */
2706 cprev = info->icount;
2707 oldsigs = info->input_signal_events;
2708
2709 /* enable hunt and idle irqs if needed */
2710 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2711 unsigned short val = rd_reg16(info, SCR);
2712 if (!(val & IRQ_RXIDLE))
2713 wr_reg16(info, SCR, (unsigned short)(val | IRQ_RXIDLE));
2714 }
2715
2716 set_current_state(TASK_INTERRUPTIBLE);
2717 add_wait_queue(&info->event_wait_q, &wait);
2718
2719 spin_unlock_irqrestore(&info->lock,flags);
2720
2721 for(;;) {
2722 schedule();
2723 if (signal_pending(current)) {
2724 rc = -ERESTARTSYS;
2725 break;
2726 }
2727
2728 /* get current irq counts */
2729 spin_lock_irqsave(&info->lock,flags);
2730 cnow = info->icount;
2731 newsigs = info->input_signal_events;
2732 set_current_state(TASK_INTERRUPTIBLE);
2733 spin_unlock_irqrestore(&info->lock,flags);
2734
2735 /* if no change, wait aborted for some reason */
2736 if (newsigs.dsr_up == oldsigs.dsr_up &&
2737 newsigs.dsr_down == oldsigs.dsr_down &&
2738 newsigs.dcd_up == oldsigs.dcd_up &&
2739 newsigs.dcd_down == oldsigs.dcd_down &&
2740 newsigs.cts_up == oldsigs.cts_up &&
2741 newsigs.cts_down == oldsigs.cts_down &&
2742 newsigs.ri_up == oldsigs.ri_up &&
2743 newsigs.ri_down == oldsigs.ri_down &&
2744 cnow.exithunt == cprev.exithunt &&
2745 cnow.rxidle == cprev.rxidle) {
2746 rc = -EIO;
2747 break;
2748 }
2749
2750 events = mask &
2751 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2752 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2753 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2754 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2755 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2756 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2757 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2758 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2759 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2760 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2761 if (events)
2762 break;
2763
2764 cprev = cnow;
2765 oldsigs = newsigs;
2766 }
2767
2768 remove_wait_queue(&info->event_wait_q, &wait);
2769 set_current_state(TASK_RUNNING);
2770
2771
2772 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2773 spin_lock_irqsave(&info->lock,flags);
2774 if (!waitqueue_active(&info->event_wait_q)) {
2775 /* disable enable exit hunt mode/idle rcvd IRQs */
2776 wr_reg16(info, SCR,
2777 (unsigned short)(rd_reg16(info, SCR) & ~IRQ_RXIDLE));
2778 }
2779 spin_unlock_irqrestore(&info->lock,flags);
2780 }
2781 exit:
2782 if (rc == 0)
2783 rc = put_user(events, mask_ptr);
2784 return rc;
2785 }
2786
2787 static int get_interface(struct slgt_info *info, int __user *if_mode)
2788 {
2789 DBGINFO(("%s get_interface=%x\n", info->device_name, info->if_mode));
2790 if (put_user(info->if_mode, if_mode))
2791 return -EFAULT;
2792 return 0;
2793 }
2794
2795 static int set_interface(struct slgt_info *info, int if_mode)
2796 {
2797 unsigned long flags;
2798 unsigned short val;
2799
2800 DBGINFO(("%s set_interface=%x)\n", info->device_name, if_mode));
2801 spin_lock_irqsave(&info->lock,flags);
2802 info->if_mode = if_mode;
2803
2804 msc_set_vcr(info);
2805
2806 /* TCR (tx control) 07 1=RTS driver control */
2807 val = rd_reg16(info, TCR);
2808 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
2809 val |= BIT7;
2810 else
2811 val &= ~BIT7;
2812 wr_reg16(info, TCR, val);
2813
2814 spin_unlock_irqrestore(&info->lock,flags);
2815 return 0;
2816 }
2817
2818 /*
2819 * set general purpose IO pin state and direction
2820 *
2821 * user_gpio fields:
2822 * state each bit indicates a pin state
2823 * smask set bit indicates pin state to set
2824 * dir each bit indicates a pin direction (0=input, 1=output)
2825 * dmask set bit indicates pin direction to set
2826 */
2827 static int set_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2828 {
2829 unsigned long flags;
2830 struct gpio_desc gpio;
2831 __u32 data;
2832
2833 if (!info->gpio_present)
2834 return -EINVAL;
2835 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2836 return -EFAULT;
2837 DBGINFO(("%s set_gpio state=%08x smask=%08x dir=%08x dmask=%08x\n",
2838 info->device_name, gpio.state, gpio.smask,
2839 gpio.dir, gpio.dmask));
2840
2841 spin_lock_irqsave(&info->lock,flags);
2842 if (gpio.dmask) {
2843 data = rd_reg32(info, IODR);
2844 data |= gpio.dmask & gpio.dir;
2845 data &= ~(gpio.dmask & ~gpio.dir);
2846 wr_reg32(info, IODR, data);
2847 }
2848 if (gpio.smask) {
2849 data = rd_reg32(info, IOVR);
2850 data |= gpio.smask & gpio.state;
2851 data &= ~(gpio.smask & ~gpio.state);
2852 wr_reg32(info, IOVR, data);
2853 }
2854 spin_unlock_irqrestore(&info->lock,flags);
2855
2856 return 0;
2857 }
2858
2859 /*
2860 * get general purpose IO pin state and direction
2861 */
2862 static int get_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2863 {
2864 struct gpio_desc gpio;
2865 if (!info->gpio_present)
2866 return -EINVAL;
2867 gpio.state = rd_reg32(info, IOVR);
2868 gpio.smask = 0xffffffff;
2869 gpio.dir = rd_reg32(info, IODR);
2870 gpio.dmask = 0xffffffff;
2871 if (copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2872 return -EFAULT;
2873 DBGINFO(("%s get_gpio state=%08x dir=%08x\n",
2874 info->device_name, gpio.state, gpio.dir));
2875 return 0;
2876 }
2877
2878 /*
2879 * conditional wait facility
2880 */
2881 static void init_cond_wait(struct cond_wait *w, unsigned int data)
2882 {
2883 init_waitqueue_head(&w->q);
2884 init_waitqueue_entry(&w->wait, current);
2885 w->data = data;
2886 }
2887
2888 static void add_cond_wait(struct cond_wait **head, struct cond_wait *w)
2889 {
2890 set_current_state(TASK_INTERRUPTIBLE);
2891 add_wait_queue(&w->q, &w->wait);
2892 w->next = *head;
2893 *head = w;
2894 }
2895
2896 static void remove_cond_wait(struct cond_wait **head, struct cond_wait *cw)
2897 {
2898 struct cond_wait *w, *prev;
2899 remove_wait_queue(&cw->q, &cw->wait);
2900 set_current_state(TASK_RUNNING);
2901 for (w = *head, prev = NULL ; w != NULL ; prev = w, w = w->next) {
2902 if (w == cw) {
2903 if (prev != NULL)
2904 prev->next = w->next;
2905 else
2906 *head = w->next;
2907 break;
2908 }
2909 }
2910 }
2911
2912 static void flush_cond_wait(struct cond_wait **head)
2913 {
2914 while (*head != NULL) {
2915 wake_up_interruptible(&(*head)->q);
2916 *head = (*head)->next;
2917 }
2918 }
2919
2920 /*
2921 * wait for general purpose I/O pin(s) to enter specified state
2922 *
2923 * user_gpio fields:
2924 * state - bit indicates target pin state
2925 * smask - set bit indicates watched pin
2926 *
2927 * The wait ends when at least one watched pin enters the specified
2928 * state. When 0 (no error) is returned, user_gpio->state is set to the
2929 * state of all GPIO pins when the wait ends.
2930 *
2931 * Note: Each pin may be a dedicated input, dedicated output, or
2932 * configurable input/output. The number and configuration of pins
2933 * varies with the specific adapter model. Only input pins (dedicated
2934 * or configured) can be monitored with this function.
2935 */
2936 static int wait_gpio(struct slgt_info *info, struct gpio_desc __user *user_gpio)
2937 {
2938 unsigned long flags;
2939 int rc = 0;
2940 struct gpio_desc gpio;
2941 struct cond_wait wait;
2942 u32 state;
2943
2944 if (!info->gpio_present)
2945 return -EINVAL;
2946 if (copy_from_user(&gpio, user_gpio, sizeof(gpio)))
2947 return -EFAULT;
2948 DBGINFO(("%s wait_gpio() state=%08x smask=%08x\n",
2949 info->device_name, gpio.state, gpio.smask));
2950 /* ignore output pins identified by set IODR bit */
2951 if ((gpio.smask &= ~rd_reg32(info, IODR)) == 0)
2952 return -EINVAL;
2953 init_cond_wait(&wait, gpio.smask);
2954
2955 spin_lock_irqsave(&info->lock, flags);
2956 /* enable interrupts for watched pins */
2957 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask);
2958 /* get current pin states */
2959 state = rd_reg32(info, IOVR);
2960
2961 if (gpio.smask & ~(state ^ gpio.state)) {
2962 /* already in target state */
2963 gpio.state = state;
2964 } else {
2965 /* wait for target state */
2966 add_cond_wait(&info->gpio_wait_q, &wait);
2967 spin_unlock_irqrestore(&info->lock, flags);
2968 schedule();
2969 if (signal_pending(current))
2970 rc = -ERESTARTSYS;
2971 else
2972 gpio.state = wait.data;
2973 spin_lock_irqsave(&info->lock, flags);
2974 remove_cond_wait(&info->gpio_wait_q, &wait);
2975 }
2976
2977 /* disable all GPIO interrupts if no waiting processes */
2978 if (info->gpio_wait_q == NULL)
2979 wr_reg32(info, IOER, 0);
2980 spin_unlock_irqrestore(&info->lock,flags);
2981
2982 if ((rc == 0) && copy_to_user(user_gpio, &gpio, sizeof(gpio)))
2983 rc = -EFAULT;
2984 return rc;
2985 }
2986
2987 static int modem_input_wait(struct slgt_info *info,int arg)
2988 {
2989 unsigned long flags;
2990 int rc;
2991 struct mgsl_icount cprev, cnow;
2992 DECLARE_WAITQUEUE(wait, current);
2993
2994 /* save current irq counts */
2995 spin_lock_irqsave(&info->lock,flags);
2996 cprev = info->icount;
2997 add_wait_queue(&info->status_event_wait_q, &wait);
2998 set_current_state(TASK_INTERRUPTIBLE);
2999 spin_unlock_irqrestore(&info->lock,flags);
3000
3001 for(;;) {
3002 schedule();
3003 if (signal_pending(current)) {
3004 rc = -ERESTARTSYS;
3005 break;
3006 }
3007
3008 /* get new irq counts */
3009 spin_lock_irqsave(&info->lock,flags);
3010 cnow = info->icount;
3011 set_current_state(TASK_INTERRUPTIBLE);
3012 spin_unlock_irqrestore(&info->lock,flags);
3013
3014 /* if no change, wait aborted for some reason */
3015 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3016 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3017 rc = -EIO;
3018 break;
3019 }
3020
3021 /* check for change in caller specified modem input */
3022 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3023 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3024 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3025 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3026 rc = 0;
3027 break;
3028 }
3029
3030 cprev = cnow;
3031 }
3032 remove_wait_queue(&info->status_event_wait_q, &wait);
3033 set_current_state(TASK_RUNNING);
3034 return rc;
3035 }
3036
3037 /*
3038 * return state of serial control and status signals
3039 */
3040 static int tiocmget(struct tty_struct *tty, struct file *file)
3041 {
3042 struct slgt_info *info = tty->driver_data;
3043 unsigned int result;
3044 unsigned long flags;
3045
3046 spin_lock_irqsave(&info->lock,flags);
3047 get_signals(info);
3048 spin_unlock_irqrestore(&info->lock,flags);
3049
3050 result = ((info->signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3051 ((info->signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3052 ((info->signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3053 ((info->signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3054 ((info->signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3055 ((info->signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3056
3057 DBGINFO(("%s tiocmget value=%08X\n", info->device_name, result));
3058 return result;
3059 }
3060
3061 /*
3062 * set modem control signals (DTR/RTS)
3063 *
3064 * cmd signal command: TIOCMBIS = set bit TIOCMBIC = clear bit
3065 * TIOCMSET = set/clear signal values
3066 * value bit mask for command
3067 */
3068 static int tiocmset(struct tty_struct *tty, struct file *file,
3069 unsigned int set, unsigned int clear)
3070 {
3071 struct slgt_info *info = tty->driver_data;
3072 unsigned long flags;
3073
3074 DBGINFO(("%s tiocmset(%x,%x)\n", info->device_name, set, clear));
3075
3076 if (set & TIOCM_RTS)
3077 info->signals |= SerialSignal_RTS;
3078 if (set & TIOCM_DTR)
3079 info->signals |= SerialSignal_DTR;
3080 if (clear & TIOCM_RTS)
3081 info->signals &= ~SerialSignal_RTS;
3082 if (clear & TIOCM_DTR)
3083 info->signals &= ~SerialSignal_DTR;
3084
3085 spin_lock_irqsave(&info->lock,flags);
3086 set_signals(info);
3087 spin_unlock_irqrestore(&info->lock,flags);
3088 return 0;
3089 }
3090
3091 static int carrier_raised(struct tty_port *port)
3092 {
3093 unsigned long flags;
3094 struct slgt_info *info = container_of(port, struct slgt_info, port);
3095
3096 spin_lock_irqsave(&info->lock,flags);
3097 get_signals(info);
3098 spin_unlock_irqrestore(&info->lock,flags);
3099 return (info->signals & SerialSignal_DCD) ? 1 : 0;
3100 }
3101
3102 static void dtr_rts(struct tty_port *port, int on)
3103 {
3104 unsigned long flags;
3105 struct slgt_info *info = container_of(port, struct slgt_info, port);
3106
3107 spin_lock_irqsave(&info->lock,flags);
3108 if (on)
3109 info->signals |= SerialSignal_RTS + SerialSignal_DTR;
3110 else
3111 info->signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3112 set_signals(info);
3113 spin_unlock_irqrestore(&info->lock,flags);
3114 }
3115
3116
3117 /*
3118 * block current process until the device is ready to open
3119 */
3120 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3121 struct slgt_info *info)
3122 {
3123 DECLARE_WAITQUEUE(wait, current);
3124 int retval;
3125 bool do_clocal = false;
3126 bool extra_count = false;
3127 unsigned long flags;
3128 int cd;
3129 struct tty_port *port = &info->port;
3130
3131 DBGINFO(("%s block_til_ready\n", tty->driver->name));
3132
3133 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3134 /* nonblock mode is set or port is not enabled */
3135 port->flags |= ASYNC_NORMAL_ACTIVE;
3136 return 0;
3137 }
3138
3139 if (tty->termios->c_cflag & CLOCAL)
3140 do_clocal = true;
3141
3142 /* Wait for carrier detect and the line to become
3143 * free (i.e., not in use by the callout). While we are in
3144 * this loop, port->count is dropped by one, so that
3145 * close() knows when to free things. We restore it upon
3146 * exit, either normal or abnormal.
3147 */
3148
3149 retval = 0;
3150 add_wait_queue(&port->open_wait, &wait);
3151
3152 spin_lock_irqsave(&info->lock, flags);
3153 if (!tty_hung_up_p(filp)) {
3154 extra_count = true;
3155 port->count--;
3156 }
3157 spin_unlock_irqrestore(&info->lock, flags);
3158 port->blocked_open++;
3159
3160 while (1) {
3161 if ((tty->termios->c_cflag & CBAUD))
3162 tty_port_raise_dtr_rts(port);
3163
3164 set_current_state(TASK_INTERRUPTIBLE);
3165
3166 if (tty_hung_up_p(filp) || !(port->flags & ASYNC_INITIALIZED)){
3167 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3168 -EAGAIN : -ERESTARTSYS;
3169 break;
3170 }
3171
3172 cd = tty_port_carrier_raised(port);
3173
3174 if (!(port->flags & ASYNC_CLOSING) && (do_clocal || cd ))
3175 break;
3176
3177 if (signal_pending(current)) {
3178 retval = -ERESTARTSYS;
3179 break;
3180 }
3181
3182 DBGINFO(("%s block_til_ready wait\n", tty->driver->name));
3183 schedule();
3184 }
3185
3186 set_current_state(TASK_RUNNING);
3187 remove_wait_queue(&port->open_wait, &wait);
3188
3189 if (extra_count)
3190 port->count++;
3191 port->blocked_open--;
3192
3193 if (!retval)
3194 port->flags |= ASYNC_NORMAL_ACTIVE;
3195
3196 DBGINFO(("%s block_til_ready ready, rc=%d\n", tty->driver->name, retval));
3197 return retval;
3198 }
3199
3200 static int alloc_tmp_rbuf(struct slgt_info *info)
3201 {
3202 info->tmp_rbuf = kmalloc(info->max_frame_size + 5, GFP_KERNEL);
3203 if (info->tmp_rbuf == NULL)
3204 return -ENOMEM;
3205 return 0;
3206 }
3207
3208 static void free_tmp_rbuf(struct slgt_info *info)
3209 {
3210 kfree(info->tmp_rbuf);
3211 info->tmp_rbuf = NULL;
3212 }
3213
3214 /*
3215 * allocate DMA descriptor lists.
3216 */
3217 static int alloc_desc(struct slgt_info *info)
3218 {
3219 unsigned int i;
3220 unsigned int pbufs;
3221
3222 /* allocate memory to hold descriptor lists */
3223 info->bufs = pci_alloc_consistent(info->pdev, DESC_LIST_SIZE, &info->bufs_dma_addr);
3224 if (info->bufs == NULL)
3225 return -ENOMEM;
3226
3227 memset(info->bufs, 0, DESC_LIST_SIZE);
3228
3229 info->rbufs = (struct slgt_desc*)info->bufs;
3230 info->tbufs = ((struct slgt_desc*)info->bufs) + info->rbuf_count;
3231
3232 pbufs = (unsigned int)info->bufs_dma_addr;
3233
3234 /*
3235 * Build circular lists of descriptors
3236 */
3237
3238 for (i=0; i < info->rbuf_count; i++) {
3239 /* physical address of this descriptor */
3240 info->rbufs[i].pdesc = pbufs + (i * sizeof(struct slgt_desc));
3241
3242 /* physical address of next descriptor */
3243 if (i == info->rbuf_count - 1)
3244 info->rbufs[i].next = cpu_to_le32(pbufs);
3245 else
3246 info->rbufs[i].next = cpu_to_le32(pbufs + ((i+1) * sizeof(struct slgt_desc)));
3247 set_desc_count(info->rbufs[i], DMABUFSIZE);
3248 }
3249
3250 for (i=0; i < info->tbuf_count; i++) {
3251 /* physical address of this descriptor */
3252 info->tbufs[i].pdesc = pbufs + ((info->rbuf_count + i) * sizeof(struct slgt_desc));
3253
3254 /* physical address of next descriptor */
3255 if (i == info->tbuf_count - 1)
3256 info->tbufs[i].next = cpu_to_le32(pbufs + info->rbuf_count * sizeof(struct slgt_desc));
3257 else
3258 info->tbufs[i].next = cpu_to_le32(pbufs + ((info->rbuf_count + i + 1) * sizeof(struct slgt_desc)));
3259 }
3260
3261 return 0;
3262 }
3263
3264 static void free_desc(struct slgt_info *info)
3265 {
3266 if (info->bufs != NULL) {
3267 pci_free_consistent(info->pdev, DESC_LIST_SIZE, info->bufs, info->bufs_dma_addr);
3268 info->bufs = NULL;
3269 info->rbufs = NULL;
3270 info->tbufs = NULL;
3271 }
3272 }
3273
3274 static int alloc_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3275 {
3276 int i;
3277 for (i=0; i < count; i++) {
3278 if ((bufs[i].buf = pci_alloc_consistent(info->pdev, DMABUFSIZE, &bufs[i].buf_dma_addr)) == NULL)
3279 return -ENOMEM;
3280 bufs[i].pbuf = cpu_to_le32((unsigned int)bufs[i].buf_dma_addr);
3281 }
3282 return 0;
3283 }
3284
3285 static void free_bufs(struct slgt_info *info, struct slgt_desc *bufs, int count)
3286 {
3287 int i;
3288 for (i=0; i < count; i++) {
3289 if (bufs[i].buf == NULL)
3290 continue;
3291 pci_free_consistent(info->pdev, DMABUFSIZE, bufs[i].buf, bufs[i].buf_dma_addr);
3292 bufs[i].buf = NULL;
3293 }
3294 }
3295
3296 static int alloc_dma_bufs(struct slgt_info *info)
3297 {
3298 info->rbuf_count = 32;
3299 info->tbuf_count = 32;
3300
3301 if (alloc_desc(info) < 0 ||
3302 alloc_bufs(info, info->rbufs, info->rbuf_count) < 0 ||
3303 alloc_bufs(info, info->tbufs, info->tbuf_count) < 0 ||
3304 alloc_tmp_rbuf(info) < 0) {
3305 DBGERR(("%s DMA buffer alloc fail\n", info->device_name));
3306 return -ENOMEM;
3307 }
3308 reset_rbufs(info);
3309 return 0;
3310 }
3311
3312 static void free_dma_bufs(struct slgt_info *info)
3313 {
3314 if (info->bufs) {
3315 free_bufs(info, info->rbufs, info->rbuf_count);
3316 free_bufs(info, info->tbufs, info->tbuf_count);
3317 free_desc(info);
3318 }
3319 free_tmp_rbuf(info);
3320 }
3321
3322 static int claim_resources(struct slgt_info *info)
3323 {
3324 if (request_mem_region(info->phys_reg_addr, SLGT_REG_SIZE, "synclink_gt") == NULL) {
3325 DBGERR(("%s reg addr conflict, addr=%08X\n",
3326 info->device_name, info->phys_reg_addr));
3327 info->init_error = DiagStatus_AddressConflict;
3328 goto errout;
3329 }
3330 else
3331 info->reg_addr_requested = true;
3332
3333 info->reg_addr = ioremap_nocache(info->phys_reg_addr, SLGT_REG_SIZE);
3334 if (!info->reg_addr) {
3335 DBGERR(("%s cant map device registers, addr=%08X\n",
3336 info->device_name, info->phys_reg_addr));
3337 info->init_error = DiagStatus_CantAssignPciResources;
3338 goto errout;
3339 }
3340 return 0;
3341
3342 errout:
3343 release_resources(info);
3344 return -ENODEV;
3345 }
3346
3347 static void release_resources(struct slgt_info *info)
3348 {
3349 if (info->irq_requested) {
3350 free_irq(info->irq_level, info);
3351 info->irq_requested = false;
3352 }
3353
3354 if (info->reg_addr_requested) {
3355 release_mem_region(info->phys_reg_addr, SLGT_REG_SIZE);
3356 info->reg_addr_requested = false;
3357 }
3358
3359 if (info->reg_addr) {
3360 iounmap(info->reg_addr);
3361 info->reg_addr = NULL;
3362 }
3363 }
3364
3365 /* Add the specified device instance data structure to the
3366 * global linked list of devices and increment the device count.
3367 */
3368 static void add_device(struct slgt_info *info)
3369 {
3370 char *devstr;
3371
3372 info->next_device = NULL;
3373 info->line = slgt_device_count;
3374 sprintf(info->device_name, "%s%d", tty_dev_prefix, info->line);
3375
3376 if (info->line < MAX_DEVICES) {
3377 if (maxframe[info->line])
3378 info->max_frame_size = maxframe[info->line];
3379 }
3380
3381 slgt_device_count++;
3382
3383 if (!slgt_device_list)
3384 slgt_device_list = info;
3385 else {
3386 struct slgt_info *current_dev = slgt_device_list;
3387 while(current_dev->next_device)
3388 current_dev = current_dev->next_device;
3389 current_dev->next_device = info;
3390 }
3391
3392 if (info->max_frame_size < 4096)
3393 info->max_frame_size = 4096;
3394 else if (info->max_frame_size > 65535)
3395 info->max_frame_size = 65535;
3396
3397 switch(info->pdev->device) {
3398 case SYNCLINK_GT_DEVICE_ID:
3399 devstr = "GT";
3400 break;
3401 case SYNCLINK_GT2_DEVICE_ID:
3402 devstr = "GT2";
3403 break;
3404 case SYNCLINK_GT4_DEVICE_ID:
3405 devstr = "GT4";
3406 break;
3407 case SYNCLINK_AC_DEVICE_ID:
3408 devstr = "AC";
3409 info->params.mode = MGSL_MODE_ASYNC;
3410 break;
3411 default:
3412 devstr = "(unknown model)";
3413 }
3414 printk("SyncLink %s %s IO=%08x IRQ=%d MaxFrameSize=%u\n",
3415 devstr, info->device_name, info->phys_reg_addr,
3416 info->irq_level, info->max_frame_size);
3417
3418 #if SYNCLINK_GENERIC_HDLC
3419 hdlcdev_init(info);
3420 #endif
3421 }
3422
3423 static const struct tty_port_operations slgt_port_ops = {
3424 .carrier_raised = carrier_raised,
3425 .dtr_rts = dtr_rts,
3426 };
3427
3428 /*
3429 * allocate device instance structure, return NULL on failure
3430 */
3431 static struct slgt_info *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3432 {
3433 struct slgt_info *info;
3434
3435 info = kzalloc(sizeof(struct slgt_info), GFP_KERNEL);
3436
3437 if (!info) {
3438 DBGERR(("%s device alloc failed adapter=%d port=%d\n",
3439 driver_name, adapter_num, port_num));
3440 } else {
3441 tty_port_init(&info->port);
3442 info->port.ops = &slgt_port_ops;
3443 info->magic = MGSL_MAGIC;
3444 INIT_WORK(&info->task, bh_handler);
3445 info->max_frame_size = 4096;
3446 info->base_clock = 14745600;
3447 info->rbuf_fill_level = DMABUFSIZE;
3448 info->port.close_delay = 5*HZ/10;
3449 info->port.closing_wait = 30*HZ;
3450 init_waitqueue_head(&info->status_event_wait_q);
3451 init_waitqueue_head(&info->event_wait_q);
3452 spin_lock_init(&info->netlock);
3453 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3454 info->idle_mode = HDLC_TXIDLE_FLAGS;
3455 info->adapter_num = adapter_num;
3456 info->port_num = port_num;
3457
3458 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3459 setup_timer(&info->rx_timer, rx_timeout, (unsigned long)info);
3460
3461 /* Copy configuration info to device instance data */
3462 info->pdev = pdev;
3463 info->irq_level = pdev->irq;
3464 info->phys_reg_addr = pci_resource_start(pdev,0);
3465
3466 info->bus_type = MGSL_BUS_TYPE_PCI;
3467 info->irq_flags = IRQF_SHARED;
3468
3469 info->init_error = -1; /* assume error, set to 0 on successful init */
3470 }
3471
3472 return info;
3473 }
3474
3475 static void device_init(int adapter_num, struct pci_dev *pdev)
3476 {
3477 struct slgt_info *port_array[SLGT_MAX_PORTS];
3478 int i;
3479 int port_count = 1;
3480
3481 if (pdev->device == SYNCLINK_GT2_DEVICE_ID)
3482 port_count = 2;
3483 else if (pdev->device == SYNCLINK_GT4_DEVICE_ID)
3484 port_count = 4;
3485
3486 /* allocate device instances for all ports */
3487 for (i=0; i < port_count; ++i) {
3488 port_array[i] = alloc_dev(adapter_num, i, pdev);
3489 if (port_array[i] == NULL) {
3490 for (--i; i >= 0; --i)
3491 kfree(port_array[i]);
3492 return;
3493 }
3494 }
3495
3496 /* give copy of port_array to all ports and add to device list */
3497 for (i=0; i < port_count; ++i) {
3498 memcpy(port_array[i]->port_array, port_array, sizeof(port_array));
3499 add_device(port_array[i]);
3500 port_array[i]->port_count = port_count;
3501 spin_lock_init(&port_array[i]->lock);
3502 }
3503
3504 /* Allocate and claim adapter resources */
3505 if (!claim_resources(port_array[0])) {
3506
3507 alloc_dma_bufs(port_array[0]);
3508
3509 /* copy resource information from first port to others */
3510 for (i = 1; i < port_count; ++i) {
3511 port_array[i]->lock = port_array[0]->lock;
3512 port_array[i]->irq_level = port_array[0]->irq_level;
3513 port_array[i]->reg_addr = port_array[0]->reg_addr;
3514 alloc_dma_bufs(port_array[i]);
3515 }
3516
3517 if (request_irq(port_array[0]->irq_level,
3518 slgt_interrupt,
3519 port_array[0]->irq_flags,
3520 port_array[0]->device_name,
3521 port_array[0]) < 0) {
3522 DBGERR(("%s request_irq failed IRQ=%d\n",
3523 port_array[0]->device_name,
3524 port_array[0]->irq_level));
3525 } else {
3526 port_array[0]->irq_requested = true;
3527 adapter_test(port_array[0]);
3528 for (i=1 ; i < port_count ; i++) {
3529 port_array[i]->init_error = port_array[0]->init_error;
3530 port_array[i]->gpio_present = port_array[0]->gpio_present;
3531 }
3532 }
3533 }
3534
3535 for (i=0; i < port_count; ++i)
3536 tty_register_device(serial_driver, port_array[i]->line, &(port_array[i]->pdev->dev));
3537 }
3538
3539 static int __devinit init_one(struct pci_dev *dev,
3540 const struct pci_device_id *ent)
3541 {
3542 if (pci_enable_device(dev)) {
3543 printk("error enabling pci device %p\n", dev);
3544 return -EIO;
3545 }
3546 pci_set_master(dev);
3547 device_init(slgt_device_count, dev);
3548 return 0;
3549 }
3550
3551 static void __devexit remove_one(struct pci_dev *dev)
3552 {
3553 }
3554
3555 static const struct tty_operations ops = {
3556 .open = open,
3557 .close = close,
3558 .write = write,
3559 .put_char = put_char,
3560 .flush_chars = flush_chars,
3561 .write_room = write_room,
3562 .chars_in_buffer = chars_in_buffer,
3563 .flush_buffer = flush_buffer,
3564 .ioctl = ioctl,
3565 .compat_ioctl = slgt_compat_ioctl,
3566 .throttle = throttle,
3567 .unthrottle = unthrottle,
3568 .send_xchar = send_xchar,
3569 .break_ctl = set_break,
3570 .wait_until_sent = wait_until_sent,
3571 .set_termios = set_termios,
3572 .stop = tx_hold,
3573 .start = tx_release,
3574 .hangup = hangup,
3575 .tiocmget = tiocmget,
3576 .tiocmset = tiocmset,
3577 .proc_fops = &synclink_gt_proc_fops,
3578 };
3579
3580 static void slgt_cleanup(void)
3581 {
3582 int rc;
3583 struct slgt_info *info;
3584 struct slgt_info *tmp;
3585
3586 printk(KERN_INFO "unload %s\n", driver_name);
3587
3588 if (serial_driver) {
3589 for (info=slgt_device_list ; info != NULL ; info=info->next_device)
3590 tty_unregister_device(serial_driver, info->line);
3591 if ((rc = tty_unregister_driver(serial_driver)))
3592 DBGERR(("tty_unregister_driver error=%d\n", rc));
3593 put_tty_driver(serial_driver);
3594 }
3595
3596 /* reset devices */
3597 info = slgt_device_list;
3598 while(info) {
3599 reset_port(info);
3600 info = info->next_device;
3601 }
3602
3603 /* release devices */
3604 info = slgt_device_list;
3605 while(info) {
3606 #if SYNCLINK_GENERIC_HDLC
3607 hdlcdev_exit(info);
3608 #endif
3609 free_dma_bufs(info);
3610 free_tmp_rbuf(info);
3611 if (info->port_num == 0)
3612 release_resources(info);
3613 tmp = info;
3614 info = info->next_device;
3615 kfree(tmp);
3616 }
3617
3618 if (pci_registered)
3619 pci_unregister_driver(&pci_driver);
3620 }
3621
3622 /*
3623 * Driver initialization entry point.
3624 */
3625 static int __init slgt_init(void)
3626 {
3627 int rc;
3628
3629 printk(KERN_INFO "%s\n", driver_name);
3630
3631 serial_driver = alloc_tty_driver(MAX_DEVICES);
3632 if (!serial_driver) {
3633 printk("%s can't allocate tty driver\n", driver_name);
3634 return -ENOMEM;
3635 }
3636
3637 /* Initialize the tty_driver structure */
3638
3639 serial_driver->owner = THIS_MODULE;
3640 serial_driver->driver_name = tty_driver_name;
3641 serial_driver->name = tty_dev_prefix;
3642 serial_driver->major = ttymajor;
3643 serial_driver->minor_start = 64;
3644 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3645 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3646 serial_driver->init_termios = tty_std_termios;
3647 serial_driver->init_termios.c_cflag =
3648 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3649 serial_driver->init_termios.c_ispeed = 9600;
3650 serial_driver->init_termios.c_ospeed = 9600;
3651 serial_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_DYNAMIC_DEV;
3652 tty_set_operations(serial_driver, &ops);
3653 if ((rc = tty_register_driver(serial_driver)) < 0) {
3654 DBGERR(("%s can't register serial driver\n", driver_name));
3655 put_tty_driver(serial_driver);
3656 serial_driver = NULL;
3657 goto error;
3658 }
3659
3660 printk(KERN_INFO "%s, tty major#%d\n",
3661 driver_name, serial_driver->major);
3662
3663 slgt_device_count = 0;
3664 if ((rc = pci_register_driver(&pci_driver)) < 0) {
3665 printk("%s pci_register_driver error=%d\n", driver_name, rc);
3666 goto error;
3667 }
3668 pci_registered = true;
3669
3670 if (!slgt_device_list)
3671 printk("%s no devices found\n",driver_name);
3672
3673 return 0;
3674
3675 error:
3676 slgt_cleanup();
3677 return rc;
3678 }
3679
3680 static void __exit slgt_exit(void)
3681 {
3682 slgt_cleanup();
3683 }
3684
3685 module_init(slgt_init);
3686 module_exit(slgt_exit);
3687
3688 /*
3689 * register access routines
3690 */
3691
3692 #define CALC_REGADDR() \
3693 unsigned long reg_addr = ((unsigned long)info->reg_addr) + addr; \
3694 if (addr >= 0x80) \
3695 reg_addr += (info->port_num) * 32;
3696
3697 static __u8 rd_reg8(struct slgt_info *info, unsigned int addr)
3698 {
3699 CALC_REGADDR();
3700 return readb((void __iomem *)reg_addr);
3701 }
3702
3703 static void wr_reg8(struct slgt_info *info, unsigned int addr, __u8 value)
3704 {
3705 CALC_REGADDR();
3706 writeb(value, (void __iomem *)reg_addr);
3707 }
3708
3709 static __u16 rd_reg16(struct slgt_info *info, unsigned int addr)
3710 {
3711 CALC_REGADDR();
3712 return readw((void __iomem *)reg_addr);
3713 }
3714
3715 static void wr_reg16(struct slgt_info *info, unsigned int addr, __u16 value)
3716 {
3717 CALC_REGADDR();
3718 writew(value, (void __iomem *)reg_addr);
3719 }
3720
3721 static __u32 rd_reg32(struct slgt_info *info, unsigned int addr)
3722 {
3723 CALC_REGADDR();
3724 return readl((void __iomem *)reg_addr);
3725 }
3726
3727 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value)
3728 {
3729 CALC_REGADDR();
3730 writel(value, (void __iomem *)reg_addr);
3731 }
3732
3733 static void rdma_reset(struct slgt_info *info)
3734 {
3735 unsigned int i;
3736
3737 /* set reset bit */
3738 wr_reg32(info, RDCSR, BIT1);
3739
3740 /* wait for enable bit cleared */
3741 for(i=0 ; i < 1000 ; i++)
3742 if (!(rd_reg32(info, RDCSR) & BIT0))
3743 break;
3744 }
3745
3746 static void tdma_reset(struct slgt_info *info)
3747 {
3748 unsigned int i;
3749
3750 /* set reset bit */
3751 wr_reg32(info, TDCSR, BIT1);
3752
3753 /* wait for enable bit cleared */
3754 for(i=0 ; i < 1000 ; i++)
3755 if (!(rd_reg32(info, TDCSR) & BIT0))
3756 break;
3757 }
3758
3759 /*
3760 * enable internal loopback
3761 * TxCLK and RxCLK are generated from BRG
3762 * and TxD is looped back to RxD internally.
3763 */
3764 static void enable_loopback(struct slgt_info *info)
3765 {
3766 /* SCR (serial control) BIT2=looopback enable */
3767 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2));
3768
3769 if (info->params.mode != MGSL_MODE_ASYNC) {
3770 /* CCR (clock control)
3771 * 07..05 tx clock source (010 = BRG)
3772 * 04..02 rx clock source (010 = BRG)
3773 * 01 auxclk enable (0 = disable)
3774 * 00 BRG enable (1 = enable)
3775 *
3776 * 0100 1001
3777 */
3778 wr_reg8(info, CCR, 0x49);
3779
3780 /* set speed if available, otherwise use default */
3781 if (info->params.clock_speed)
3782 set_rate(info, info->params.clock_speed);
3783 else
3784 set_rate(info, 3686400);
3785 }
3786 }
3787
3788 /*
3789 * set baud rate generator to specified rate
3790 */
3791 static void set_rate(struct slgt_info *info, u32 rate)
3792 {
3793 unsigned int div;
3794 unsigned int osc = info->base_clock;
3795
3796 /* div = osc/rate - 1
3797 *
3798 * Round div up if osc/rate is not integer to
3799 * force to next slowest rate.
3800 */
3801
3802 if (rate) {
3803 div = osc/rate;
3804 if (!(osc % rate) && div)
3805 div--;
3806 wr_reg16(info, BDR, (unsigned short)div);
3807 }
3808 }
3809
3810 static void rx_stop(struct slgt_info *info)
3811 {
3812 unsigned short val;
3813
3814 /* disable and reset receiver */
3815 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3816 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3817 wr_reg16(info, RCR, val); /* clear reset bit */
3818
3819 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA + IRQ_RXIDLE);
3820
3821 /* clear pending rx interrupts */
3822 wr_reg16(info, SSR, IRQ_RXIDLE + IRQ_RXOVER);
3823
3824 rdma_reset(info);
3825
3826 info->rx_enabled = false;
3827 info->rx_restart = false;
3828 }
3829
3830 static void rx_start(struct slgt_info *info)
3831 {
3832 unsigned short val;
3833
3834 slgt_irq_off(info, IRQ_RXOVER + IRQ_RXDATA);
3835
3836 /* clear pending rx overrun IRQ */
3837 wr_reg16(info, SSR, IRQ_RXOVER);
3838
3839 /* reset and disable receiver */
3840 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */
3841 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */
3842 wr_reg16(info, RCR, val); /* clear reset bit */
3843
3844 rdma_reset(info);
3845 reset_rbufs(info);
3846
3847 /* set 1st descriptor address */
3848 wr_reg32(info, RDDAR, info->rbufs[0].pdesc);
3849
3850 if (info->params.mode != MGSL_MODE_ASYNC) {
3851 /* enable rx DMA and DMA interrupt */
3852 wr_reg32(info, RDCSR, (BIT2 + BIT0));
3853 } else {
3854 /* enable saving of rx status, rx DMA and DMA interrupt */
3855 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0));
3856 }
3857
3858 slgt_irq_on(info, IRQ_RXOVER);
3859
3860 /* enable receiver */
3861 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | BIT1));
3862
3863 info->rx_restart = false;
3864 info->rx_enabled = true;
3865 }
3866
3867 static void tx_start(struct slgt_info *info)
3868 {
3869 if (!info->tx_enabled) {
3870 wr_reg16(info, TCR,
3871 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2));
3872 info->tx_enabled = true;
3873 }
3874
3875 if (info->tx_count) {
3876 info->drop_rts_on_tx_done = false;
3877
3878 if (info->params.mode != MGSL_MODE_ASYNC) {
3879 if (info->params.flags & HDLC_FLAG_AUTO_RTS) {
3880 get_signals(info);
3881 if (!(info->signals & SerialSignal_RTS)) {
3882 info->signals |= SerialSignal_RTS;
3883 set_signals(info);
3884 info->drop_rts_on_tx_done = true;
3885 }
3886 }
3887
3888 slgt_irq_off(info, IRQ_TXDATA);
3889 slgt_irq_on(info, IRQ_TXUNDER + IRQ_TXIDLE);
3890 /* clear tx idle and underrun status bits */
3891 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3892 if (info->params.mode == MGSL_MODE_HDLC)
3893 mod_timer(&info->tx_timer, jiffies +
3894 msecs_to_jiffies(5000));
3895 } else {
3896 slgt_irq_off(info, IRQ_TXDATA);
3897 slgt_irq_on(info, IRQ_TXIDLE);
3898 /* clear tx idle status bit */
3899 wr_reg16(info, SSR, IRQ_TXIDLE);
3900 }
3901 tdma_start(info);
3902 info->tx_active = true;
3903 }
3904 }
3905
3906 /*
3907 * start transmit DMA if inactive and there are unsent buffers
3908 */
3909 static void tdma_start(struct slgt_info *info)
3910 {
3911 unsigned int i;
3912
3913 if (rd_reg32(info, TDCSR) & BIT0)
3914 return;
3915
3916 /* transmit DMA inactive, check for unsent buffers */
3917 i = info->tbuf_start;
3918 while (!desc_count(info->tbufs[i])) {
3919 if (++i == info->tbuf_count)
3920 i = 0;
3921 if (i == info->tbuf_current)
3922 return;
3923 }
3924 info->tbuf_start = i;
3925
3926 /* there are unsent buffers, start transmit DMA */
3927
3928 /* reset needed if previous error condition */
3929 tdma_reset(info);
3930
3931 /* set 1st descriptor address */
3932 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc);
3933 wr_reg32(info, TDCSR, BIT2 + BIT0); /* IRQ + DMA enable */
3934 }
3935
3936 static void tx_stop(struct slgt_info *info)
3937 {
3938 unsigned short val;
3939
3940 del_timer(&info->tx_timer);
3941
3942 tdma_reset(info);
3943
3944 /* reset and disable transmitter */
3945 val = rd_reg16(info, TCR) & ~BIT1; /* clear enable bit */
3946 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */
3947
3948 slgt_irq_off(info, IRQ_TXDATA + IRQ_TXIDLE + IRQ_TXUNDER);
3949
3950 /* clear tx idle and underrun status bit */
3951 wr_reg16(info, SSR, (unsigned short)(IRQ_TXIDLE + IRQ_TXUNDER));
3952
3953 reset_tbufs(info);
3954
3955 info->tx_enabled = false;
3956 info->tx_active = false;
3957 }
3958
3959 static void reset_port(struct slgt_info *info)
3960 {
3961 if (!info->reg_addr)
3962 return;
3963
3964 tx_stop(info);
3965 rx_stop(info);
3966
3967 info->signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
3968 set_signals(info);
3969
3970 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3971 }
3972
3973 static void reset_adapter(struct slgt_info *info)
3974 {
3975 int i;
3976 for (i=0; i < info->port_count; ++i) {
3977 if (info->port_array[i])
3978 reset_port(info->port_array[i]);
3979 }
3980 }
3981
3982 static void async_mode(struct slgt_info *info)
3983 {
3984 unsigned short val;
3985
3986 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
3987 tx_stop(info);
3988 rx_stop(info);
3989
3990 /* TCR (tx control)
3991 *
3992 * 15..13 mode, 010=async
3993 * 12..10 encoding, 000=NRZ
3994 * 09 parity enable
3995 * 08 1=odd parity, 0=even parity
3996 * 07 1=RTS driver control
3997 * 06 1=break enable
3998 * 05..04 character length
3999 * 00=5 bits
4000 * 01=6 bits
4001 * 10=7 bits
4002 * 11=8 bits
4003 * 03 0=1 stop bit, 1=2 stop bits
4004 * 02 reset
4005 * 01 enable
4006 * 00 auto-CTS enable
4007 */
4008 val = 0x4000;
4009
4010 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4011 val |= BIT7;
4012
4013 if (info->params.parity != ASYNC_PARITY_NONE) {
4014 val |= BIT9;
4015 if (info->params.parity == ASYNC_PARITY_ODD)
4016 val |= BIT8;
4017 }
4018
4019 switch (info->params.data_bits)
4020 {
4021 case 6: val |= BIT4; break;
4022 case 7: val |= BIT5; break;
4023 case 8: val |= BIT5 + BIT4; break;
4024 }
4025
4026 if (info->params.stop_bits != 1)
4027 val |= BIT3;
4028
4029 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4030 val |= BIT0;
4031
4032 wr_reg16(info, TCR, val);
4033
4034 /* RCR (rx control)
4035 *
4036 * 15..13 mode, 010=async
4037 * 12..10 encoding, 000=NRZ
4038 * 09 parity enable
4039 * 08 1=odd parity, 0=even parity
4040 * 07..06 reserved, must be 0
4041 * 05..04 character length
4042 * 00=5 bits
4043 * 01=6 bits
4044 * 10=7 bits
4045 * 11=8 bits
4046 * 03 reserved, must be zero
4047 * 02 reset
4048 * 01 enable
4049 * 00 auto-DCD enable
4050 */
4051 val = 0x4000;
4052
4053 if (info->params.parity != ASYNC_PARITY_NONE) {
4054 val |= BIT9;
4055 if (info->params.parity == ASYNC_PARITY_ODD)
4056 val |= BIT8;
4057 }
4058
4059 switch (info->params.data_bits)
4060 {
4061 case 6: val |= BIT4; break;
4062 case 7: val |= BIT5; break;
4063 case 8: val |= BIT5 + BIT4; break;
4064 }
4065
4066 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4067 val |= BIT0;
4068
4069 wr_reg16(info, RCR, val);
4070
4071 /* CCR (clock control)
4072 *
4073 * 07..05 011 = tx clock source is BRG/16
4074 * 04..02 010 = rx clock source is BRG
4075 * 01 0 = auxclk disabled
4076 * 00 1 = BRG enabled
4077 *
4078 * 0110 1001
4079 */
4080 wr_reg8(info, CCR, 0x69);
4081
4082 msc_set_vcr(info);
4083
4084 /* SCR (serial control)
4085 *
4086 * 15 1=tx req on FIFO half empty
4087 * 14 1=rx req on FIFO half full
4088 * 13 tx data IRQ enable
4089 * 12 tx idle IRQ enable
4090 * 11 rx break on IRQ enable
4091 * 10 rx data IRQ enable
4092 * 09 rx break off IRQ enable
4093 * 08 overrun IRQ enable
4094 * 07 DSR IRQ enable
4095 * 06 CTS IRQ enable
4096 * 05 DCD IRQ enable
4097 * 04 RI IRQ enable
4098 * 03 0=16x sampling, 1=8x sampling
4099 * 02 1=txd->rxd internal loopback enable
4100 * 01 reserved, must be zero
4101 * 00 1=master IRQ enable
4102 */
4103 val = BIT15 + BIT14 + BIT0;
4104 /* JCR[8] : 1 = x8 async mode feature available */
4105 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate &&
4106 ((info->base_clock < (info->params.data_rate * 16)) ||
4107 (info->base_clock % (info->params.data_rate * 16)))) {
4108 /* use 8x sampling */
4109 val |= BIT3;
4110 set_rate(info, info->params.data_rate * 8);
4111 } else {
4112 /* use 16x sampling */
4113 set_rate(info, info->params.data_rate * 16);
4114 }
4115 wr_reg16(info, SCR, val);
4116
4117 slgt_irq_on(info, IRQ_RXBREAK | IRQ_RXOVER);
4118
4119 if (info->params.loopback)
4120 enable_loopback(info);
4121 }
4122
4123 static void sync_mode(struct slgt_info *info)
4124 {
4125 unsigned short val;
4126
4127 slgt_irq_off(info, IRQ_ALL | IRQ_MASTER);
4128 tx_stop(info);
4129 rx_stop(info);
4130
4131 /* TCR (tx control)
4132 *
4133 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4134 * 12..10 encoding
4135 * 09 CRC enable
4136 * 08 CRC32
4137 * 07 1=RTS driver control
4138 * 06 preamble enable
4139 * 05..04 preamble length
4140 * 03 share open/close flag
4141 * 02 reset
4142 * 01 enable
4143 * 00 auto-CTS enable
4144 */
4145 val = BIT2;
4146
4147 switch(info->params.mode) {
4148 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4149 case MGSL_MODE_BISYNC: val |= BIT15; break;
4150 case MGSL_MODE_RAW: val |= BIT13; break;
4151 }
4152 if (info->if_mode & MGSL_INTERFACE_RTS_EN)
4153 val |= BIT7;
4154
4155 switch(info->params.encoding)
4156 {
4157 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4158 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4159 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4160 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4161 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4162 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4163 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4164 }
4165
4166 switch (info->params.crc_type & HDLC_CRC_MASK)
4167 {
4168 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4169 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4170 }
4171
4172 if (info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE)
4173 val |= BIT6;
4174
4175 switch (info->params.preamble_length)
4176 {
4177 case HDLC_PREAMBLE_LENGTH_16BITS: val |= BIT5; break;
4178 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4179 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; break;
4180 }
4181
4182 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4183 val |= BIT0;
4184
4185 wr_reg16(info, TCR, val);
4186
4187 /* TPR (transmit preamble) */
4188
4189 switch (info->params.preamble)
4190 {
4191 case HDLC_PREAMBLE_PATTERN_FLAGS: val = 0x7e; break;
4192 case HDLC_PREAMBLE_PATTERN_ONES: val = 0xff; break;
4193 case HDLC_PREAMBLE_PATTERN_ZEROS: val = 0x00; break;
4194 case HDLC_PREAMBLE_PATTERN_10: val = 0x55; break;
4195 case HDLC_PREAMBLE_PATTERN_01: val = 0xaa; break;
4196 default: val = 0x7e; break;
4197 }
4198 wr_reg8(info, TPR, (unsigned char)val);
4199
4200 /* RCR (rx control)
4201 *
4202 * 15..13 mode, 000=HDLC 001=raw 010=async 011=monosync 100=bisync
4203 * 12..10 encoding
4204 * 09 CRC enable
4205 * 08 CRC32
4206 * 07..03 reserved, must be 0
4207 * 02 reset
4208 * 01 enable
4209 * 00 auto-DCD enable
4210 */
4211 val = 0;
4212
4213 switch(info->params.mode) {
4214 case MGSL_MODE_MONOSYNC: val |= BIT14 + BIT13; break;
4215 case MGSL_MODE_BISYNC: val |= BIT15; break;
4216 case MGSL_MODE_RAW: val |= BIT13; break;
4217 }
4218
4219 switch(info->params.encoding)
4220 {
4221 case HDLC_ENCODING_NRZB: val |= BIT10; break;
4222 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break;
4223 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break;
4224 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4225 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4226 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4227 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4228 }
4229
4230 switch (info->params.crc_type & HDLC_CRC_MASK)
4231 {
4232 case HDLC_CRC_16_CCITT: val |= BIT9; break;
4233 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break;
4234 }
4235
4236 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4237 val |= BIT0;
4238
4239 wr_reg16(info, RCR, val);
4240
4241 /* CCR (clock control)
4242 *
4243 * 07..05 tx clock source
4244 * 04..02 rx clock source
4245 * 01 auxclk enable
4246 * 00 BRG enable
4247 */
4248 val = 0;
4249
4250 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4251 {
4252 // when RxC source is DPLL, BRG generates 16X DPLL
4253 // reference clock, so take TxC from BRG/16 to get
4254 // transmit clock at actual data rate
4255 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4256 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */
4257 else
4258 val |= BIT6; /* 010, txclk = BRG */
4259 }
4260 else if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4261 val |= BIT7; /* 100, txclk = DPLL Input */
4262 else if (info->params.flags & HDLC_FLAG_TXC_RXCPIN)
4263 val |= BIT5; /* 001, txclk = RXC Input */
4264
4265 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4266 val |= BIT3; /* 010, rxclk = BRG */
4267 else if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4268 val |= BIT4; /* 100, rxclk = DPLL */
4269 else if (info->params.flags & HDLC_FLAG_RXC_TXCPIN)
4270 val |= BIT2; /* 001, rxclk = TXC Input */
4271
4272 if (info->params.clock_speed)
4273 val |= BIT1 + BIT0;
4274
4275 wr_reg8(info, CCR, (unsigned char)val);
4276
4277 if (info->params.flags & (HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL))
4278 {
4279 // program DPLL mode
4280 switch(info->params.encoding)
4281 {
4282 case HDLC_ENCODING_BIPHASE_MARK:
4283 case HDLC_ENCODING_BIPHASE_SPACE:
4284 val = BIT7; break;
4285 case HDLC_ENCODING_BIPHASE_LEVEL:
4286 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:
4287 val = BIT7 + BIT6; break;
4288 default: val = BIT6; // NRZ encodings
4289 }
4290 wr_reg16(info, RCR, (unsigned short)(rd_reg16(info, RCR) | val));
4291
4292 // DPLL requires a 16X reference clock from BRG
4293 set_rate(info, info->params.clock_speed * 16);
4294 }
4295 else
4296 set_rate(info, info->params.clock_speed);
4297
4298 tx_set_idle(info);
4299
4300 msc_set_vcr(info);
4301
4302 /* SCR (serial control)
4303 *
4304 * 15 1=tx req on FIFO half empty
4305 * 14 1=rx req on FIFO half full
4306 * 13 tx data IRQ enable
4307 * 12 tx idle IRQ enable
4308 * 11 underrun IRQ enable
4309 * 10 rx data IRQ enable
4310 * 09 rx idle IRQ enable
4311 * 08 overrun IRQ enable
4312 * 07 DSR IRQ enable
4313 * 06 CTS IRQ enable
4314 * 05 DCD IRQ enable
4315 * 04 RI IRQ enable
4316 * 03 reserved, must be zero
4317 * 02 1=txd->rxd internal loopback enable
4318 * 01 reserved, must be zero
4319 * 00 1=master IRQ enable
4320 */
4321 wr_reg16(info, SCR, BIT15 + BIT14 + BIT0);
4322
4323 if (info->params.loopback)
4324 enable_loopback(info);
4325 }
4326
4327 /*
4328 * set transmit idle mode
4329 */
4330 static void tx_set_idle(struct slgt_info *info)
4331 {
4332 unsigned char val;
4333 unsigned short tcr;
4334
4335 /* if preamble enabled (tcr[6] == 1) then tx idle size = 8 bits
4336 * else tcr[5:4] = tx idle size: 00 = 8 bits, 01 = 16 bits
4337 */
4338 tcr = rd_reg16(info, TCR);
4339 if (info->idle_mode & HDLC_TXIDLE_CUSTOM_16) {
4340 /* disable preamble, set idle size to 16 bits */
4341 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4;
4342 /* MSB of 16 bit idle specified in tx preamble register (TPR) */
4343 wr_reg8(info, TPR, (unsigned char)((info->idle_mode >> 8) & 0xff));
4344 } else if (!(tcr & BIT6)) {
4345 /* preamble is disabled, set idle size to 8 bits */
4346 tcr &= ~(BIT5 + BIT4);
4347 }
4348 wr_reg16(info, TCR, tcr);
4349
4350 if (info->idle_mode & (HDLC_TXIDLE_CUSTOM_8 | HDLC_TXIDLE_CUSTOM_16)) {
4351 /* LSB of custom tx idle specified in tx idle register */
4352 val = (unsigned char)(info->idle_mode & 0xff);
4353 } else {
4354 /* standard 8 bit idle patterns */
4355 switch(info->idle_mode)
4356 {
4357 case HDLC_TXIDLE_FLAGS: val = 0x7e; break;
4358 case HDLC_TXIDLE_ALT_ZEROS_ONES:
4359 case HDLC_TXIDLE_ALT_MARK_SPACE: val = 0xaa; break;
4360 case HDLC_TXIDLE_ZEROS:
4361 case HDLC_TXIDLE_SPACE: val = 0x00; break;
4362 default: val = 0xff;
4363 }
4364 }
4365
4366 wr_reg8(info, TIR, val);
4367 }
4368
4369 /*
4370 * get state of V24 status (input) signals
4371 */
4372 static void get_signals(struct slgt_info *info)
4373 {
4374 unsigned short status = rd_reg16(info, SSR);
4375
4376 /* clear all serial signals except DTR and RTS */
4377 info->signals &= SerialSignal_DTR + SerialSignal_RTS;
4378
4379 if (status & BIT3)
4380 info->signals |= SerialSignal_DSR;
4381 if (status & BIT2)
4382 info->signals |= SerialSignal_CTS;
4383 if (status & BIT1)
4384 info->signals |= SerialSignal_DCD;
4385 if (status & BIT0)
4386 info->signals |= SerialSignal_RI;
4387 }
4388
4389 /*
4390 * set V.24 Control Register based on current configuration
4391 */
4392 static void msc_set_vcr(struct slgt_info *info)
4393 {
4394 unsigned char val = 0;
4395
4396 /* VCR (V.24 control)
4397 *
4398 * 07..04 serial IF select
4399 * 03 DTR
4400 * 02 RTS
4401 * 01 LL
4402 * 00 RL
4403 */
4404
4405 switch(info->if_mode & MGSL_INTERFACE_MASK)
4406 {
4407 case MGSL_INTERFACE_RS232:
4408 val |= BIT5; /* 0010 */
4409 break;
4410 case MGSL_INTERFACE_V35:
4411 val |= BIT7 + BIT6 + BIT5; /* 1110 */
4412 break;
4413 case MGSL_INTERFACE_RS422:
4414 val |= BIT6; /* 0100 */
4415 break;
4416 }
4417
4418 if (info->if_mode & MGSL_INTERFACE_MSB_FIRST)
4419 val |= BIT4;
4420 if (info->signals & SerialSignal_DTR)
4421 val |= BIT3;
4422 if (info->signals & SerialSignal_RTS)
4423 val |= BIT2;
4424 if (info->if_mode & MGSL_INTERFACE_LL)
4425 val |= BIT1;
4426 if (info->if_mode & MGSL_INTERFACE_RL)
4427 val |= BIT0;
4428 wr_reg8(info, VCR, val);
4429 }
4430
4431 /*
4432 * set state of V24 control (output) signals
4433 */
4434 static void set_signals(struct slgt_info *info)
4435 {
4436 unsigned char val = rd_reg8(info, VCR);
4437 if (info->signals & SerialSignal_DTR)
4438 val |= BIT3;
4439 else
4440 val &= ~BIT3;
4441 if (info->signals & SerialSignal_RTS)
4442 val |= BIT2;
4443 else
4444 val &= ~BIT2;
4445 wr_reg8(info, VCR, val);
4446 }
4447
4448 /*
4449 * free range of receive DMA buffers (i to last)
4450 */
4451 static void free_rbufs(struct slgt_info *info, unsigned int i, unsigned int last)
4452 {
4453 int done = 0;
4454
4455 while(!done) {
4456 /* reset current buffer for reuse */
4457 info->rbufs[i].status = 0;
4458 set_desc_count(info->rbufs[i], info->rbuf_fill_level);
4459 if (i == last)
4460 done = 1;
4461 if (++i == info->rbuf_count)
4462 i = 0;
4463 }
4464 info->rbuf_current = i;
4465 }
4466
4467 /*
4468 * mark all receive DMA buffers as free
4469 */
4470 static void reset_rbufs(struct slgt_info *info)
4471 {
4472 free_rbufs(info, 0, info->rbuf_count - 1);
4473 }
4474
4475 /*
4476 * pass receive HDLC frame to upper layer
4477 *
4478 * return true if frame available, otherwise false
4479 */
4480 static bool rx_get_frame(struct slgt_info *info)
4481 {
4482 unsigned int start, end;
4483 unsigned short status;
4484 unsigned int framesize = 0;
4485 unsigned long flags;
4486 struct tty_struct *tty = info->port.tty;
4487 unsigned char addr_field = 0xff;
4488 unsigned int crc_size = 0;
4489
4490 switch (info->params.crc_type & HDLC_CRC_MASK) {
4491 case HDLC_CRC_16_CCITT: crc_size = 2; break;
4492 case HDLC_CRC_32_CCITT: crc_size = 4; break;
4493 }
4494
4495 check_again:
4496
4497 framesize = 0;
4498 addr_field = 0xff;
4499 start = end = info->rbuf_current;
4500
4501 for (;;) {
4502 if (!desc_complete(info->rbufs[end]))
4503 goto cleanup;
4504
4505 if (framesize == 0 && info->params.addr_filter != 0xff)
4506 addr_field = info->rbufs[end].buf[0];
4507
4508 framesize += desc_count(info->rbufs[end]);
4509
4510 if (desc_eof(info->rbufs[end]))
4511 break;
4512
4513 if (++end == info->rbuf_count)
4514 end = 0;
4515
4516 if (end == info->rbuf_current) {
4517 if (info->rx_enabled){
4518 spin_lock_irqsave(&info->lock,flags);
4519 rx_start(info);
4520 spin_unlock_irqrestore(&info->lock,flags);
4521 }
4522 goto cleanup;
4523 }
4524 }
4525
4526 /* status
4527 *
4528 * 15 buffer complete
4529 * 14..06 reserved
4530 * 05..04 residue
4531 * 02 eof (end of frame)
4532 * 01 CRC error
4533 * 00 abort
4534 */
4535 status = desc_status(info->rbufs[end]);
4536
4537 /* ignore CRC bit if not using CRC (bit is undefined) */
4538 if ((info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_NONE)
4539 status &= ~BIT1;
4540
4541 if (framesize == 0 ||
4542 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4543 free_rbufs(info, start, end);
4544 goto check_again;
4545 }
4546
4547 if (framesize < (2 + crc_size) || status & BIT0) {
4548 info->icount.rxshort++;
4549 framesize = 0;
4550 } else if (status & BIT1) {
4551 info->icount.rxcrc++;
4552 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX))
4553 framesize = 0;
4554 }
4555
4556 #if SYNCLINK_GENERIC_HDLC
4557 if (framesize == 0) {
4558 info->netdev->stats.rx_errors++;
4559 info->netdev->stats.rx_frame_errors++;
4560 }
4561 #endif
4562
4563 DBGBH(("%s rx frame status=%04X size=%d\n",
4564 info->device_name, status, framesize));
4565 DBGDATA(info, info->rbufs[start].buf, min_t(int, framesize, info->rbuf_fill_level), "rx");
4566
4567 if (framesize) {
4568 if (!(info->params.crc_type & HDLC_CRC_RETURN_EX)) {
4569 framesize -= crc_size;
4570 crc_size = 0;
4571 }
4572
4573 if (framesize > info->max_frame_size + crc_size)
4574 info->icount.rxlong++;
4575 else {
4576 /* copy dma buffer(s) to contiguous temp buffer */
4577 int copy_count = framesize;
4578 int i = start;
4579 unsigned char *p = info->tmp_rbuf;
4580 info->tmp_rbuf_count = framesize;
4581
4582 info->icount.rxok++;
4583
4584 while(copy_count) {
4585 int partial_count = min_t(int, copy_count, info->rbuf_fill_level);
4586 memcpy(p, info->rbufs[i].buf, partial_count);
4587 p += partial_count;
4588 copy_count -= partial_count;
4589 if (++i == info->rbuf_count)
4590 i = 0;
4591 }
4592
4593 if (info->params.crc_type & HDLC_CRC_RETURN_EX) {
4594 *p = (status & BIT1) ? RX_CRC_ERROR : RX_OK;
4595 framesize++;
4596 }
4597
4598 #if SYNCLINK_GENERIC_HDLC
4599 if (info->netcount)
4600 hdlcdev_rx(info,info->tmp_rbuf, framesize);
4601 else
4602 #endif
4603 ldisc_receive_buf(tty, info->tmp_rbuf, info->flag_buf, framesize);
4604 }
4605 }
4606 free_rbufs(info, start, end);
4607 return true;
4608
4609 cleanup:
4610 return false;
4611 }
4612
4613 /*
4614 * pass receive buffer (RAW synchronous mode) to tty layer
4615 * return true if buffer available, otherwise false
4616 */
4617 static bool rx_get_buf(struct slgt_info *info)
4618 {
4619 unsigned int i = info->rbuf_current;
4620 unsigned int count;
4621
4622 if (!desc_complete(info->rbufs[i]))
4623 return false;
4624 count = desc_count(info->rbufs[i]);
4625 switch(info->params.mode) {
4626 case MGSL_MODE_MONOSYNC:
4627 case MGSL_MODE_BISYNC:
4628 /* ignore residue in byte synchronous modes */
4629 if (desc_residue(info->rbufs[i]))
4630 count--;
4631 break;
4632 }
4633 DBGDATA(info, info->rbufs[i].buf, count, "rx");
4634 DBGINFO(("rx_get_buf size=%d\n", count));
4635 if (count)
4636 ldisc_receive_buf(info->port.tty, info->rbufs[i].buf,
4637 info->flag_buf, count);
4638 free_rbufs(info, i, i);
4639 return true;
4640 }
4641
4642 static void reset_tbufs(struct slgt_info *info)
4643 {
4644 unsigned int i;
4645 info->tbuf_current = 0;
4646 for (i=0 ; i < info->tbuf_count ; i++) {
4647 info->tbufs[i].status = 0;
4648 info->tbufs[i].count = 0;
4649 }
4650 }
4651
4652 /*
4653 * return number of free transmit DMA buffers
4654 */
4655 static unsigned int free_tbuf_count(struct slgt_info *info)
4656 {
4657 unsigned int count = 0;
4658 unsigned int i = info->tbuf_current;
4659
4660 do
4661 {
4662 if (desc_count(info->tbufs[i]))
4663 break; /* buffer in use */
4664 ++count;
4665 if (++i == info->tbuf_count)
4666 i=0;
4667 } while (i != info->tbuf_current);
4668
4669 /* if tx DMA active, last zero count buffer is in use */
4670 if (count && (rd_reg32(info, TDCSR) & BIT0))
4671 --count;
4672
4673 return count;
4674 }
4675
4676 /*
4677 * return number of bytes in unsent transmit DMA buffers
4678 * and the serial controller tx FIFO
4679 */
4680 static unsigned int tbuf_bytes(struct slgt_info *info)
4681 {
4682 unsigned int total_count = 0;
4683 unsigned int i = info->tbuf_current;
4684 unsigned int reg_value;
4685 unsigned int count;
4686 unsigned int active_buf_count = 0;
4687
4688 /*
4689 * Add descriptor counts for all tx DMA buffers.
4690 * If count is zero (cleared by DMA controller after read),
4691 * the buffer is complete or is actively being read from.
4692 *
4693 * Record buf_count of last buffer with zero count starting
4694 * from current ring position. buf_count is mirror
4695 * copy of count and is not cleared by serial controller.
4696 * If DMA controller is active, that buffer is actively
4697 * being read so add to total.
4698 */
4699 do {
4700 count = desc_count(info->tbufs[i]);
4701 if (count)
4702 total_count += count;
4703 else if (!total_count)
4704 active_buf_count = info->tbufs[i].buf_count;
4705 if (++i == info->tbuf_count)
4706 i = 0;
4707 } while (i != info->tbuf_current);
4708
4709 /* read tx DMA status register */
4710 reg_value = rd_reg32(info, TDCSR);
4711
4712 /* if tx DMA active, last zero count buffer is in use */
4713 if (reg_value & BIT0)
4714 total_count += active_buf_count;
4715
4716 /* add tx FIFO count = reg_value[15..8] */
4717 total_count += (reg_value >> 8) & 0xff;
4718
4719 /* if transmitter active add one byte for shift register */
4720 if (info->tx_active)
4721 total_count++;
4722
4723 return total_count;
4724 }
4725
4726 /*
4727 * load transmit DMA buffer(s) with data
4728 */
4729 static void tx_load(struct slgt_info *info, const char *buf, unsigned int size)
4730 {
4731 unsigned short count;
4732 unsigned int i;
4733 struct slgt_desc *d;
4734
4735 if (size == 0)
4736 return;
4737
4738 DBGDATA(info, buf, size, "tx");
4739
4740 info->tbuf_start = i = info->tbuf_current;
4741
4742 while (size) {
4743 d = &info->tbufs[i];
4744 if (++i == info->tbuf_count)
4745 i = 0;
4746
4747 count = (unsigned short)((size > DMABUFSIZE) ? DMABUFSIZE : size);
4748 memcpy(d->buf, buf, count);
4749
4750 size -= count;
4751 buf += count;
4752
4753 /*
4754 * set EOF bit for last buffer of HDLC frame or
4755 * for every buffer in raw mode
4756 */
4757 if ((!size && info->params.mode == MGSL_MODE_HDLC) ||
4758 info->params.mode == MGSL_MODE_RAW)
4759 set_desc_eof(*d, 1);
4760 else
4761 set_desc_eof(*d, 0);
4762
4763 set_desc_count(*d, count);
4764 d->buf_count = count;
4765 }
4766
4767 info->tbuf_current = i;
4768 }
4769
4770 static int register_test(struct slgt_info *info)
4771 {
4772 static unsigned short patterns[] =
4773 {0x0000, 0xffff, 0xaaaa, 0x5555, 0x6969, 0x9696};
4774 static unsigned int count = sizeof(patterns)/sizeof(patterns[0]);
4775 unsigned int i;
4776 int rc = 0;
4777
4778 for (i=0 ; i < count ; i++) {
4779 wr_reg16(info, TIR, patterns[i]);
4780 wr_reg16(info, BDR, patterns[(i+1)%count]);
4781 if ((rd_reg16(info, TIR) != patterns[i]) ||
4782 (rd_reg16(info, BDR) != patterns[(i+1)%count])) {
4783 rc = -ENODEV;
4784 break;
4785 }
4786 }
4787 info->gpio_present = (rd_reg32(info, JCR) & BIT5) ? 1 : 0;
4788 info->init_error = rc ? 0 : DiagStatus_AddressFailure;
4789 return rc;
4790 }
4791
4792 static int irq_test(struct slgt_info *info)
4793 {
4794 unsigned long timeout;
4795 unsigned long flags;
4796 struct tty_struct *oldtty = info->port.tty;
4797 u32 speed = info->params.data_rate;
4798
4799 info->params.data_rate = 921600;
4800 info->port.tty = NULL;
4801
4802 spin_lock_irqsave(&info->lock, flags);
4803 async_mode(info);
4804 slgt_irq_on(info, IRQ_TXIDLE);
4805
4806 /* enable transmitter */
4807 wr_reg16(info, TCR,
4808 (unsigned short)(rd_reg16(info, TCR) | BIT1));
4809
4810 /* write one byte and wait for tx idle */
4811 wr_reg16(info, TDR, 0);
4812
4813 /* assume failure */
4814 info->init_error = DiagStatus_IrqFailure;
4815 info->irq_occurred = false;
4816
4817 spin_unlock_irqrestore(&info->lock, flags);
4818
4819 timeout=100;
4820 while(timeout-- && !info->irq_occurred)
4821 msleep_interruptible(10);
4822
4823 spin_lock_irqsave(&info->lock,flags);
4824 reset_port(info);
4825 spin_unlock_irqrestore(&info->lock,flags);
4826
4827 info->params.data_rate = speed;
4828 info->port.tty = oldtty;
4829
4830 info->init_error = info->irq_occurred ? 0 : DiagStatus_IrqFailure;
4831 return info->irq_occurred ? 0 : -ENODEV;
4832 }
4833
4834 static int loopback_test_rx(struct slgt_info *info)
4835 {
4836 unsigned char *src, *dest;
4837 int count;
4838
4839 if (desc_complete(info->rbufs[0])) {
4840 count = desc_count(info->rbufs[0]);
4841 src = info->rbufs[0].buf;
4842 dest = info->tmp_rbuf;
4843
4844 for( ; count ; count-=2, src+=2) {
4845 /* src=data byte (src+1)=status byte */
4846 if (!(*(src+1) & (BIT9 + BIT8))) {
4847 *dest = *src;
4848 dest++;
4849 info->tmp_rbuf_count++;
4850 }
4851 }
4852 DBGDATA(info, info->tmp_rbuf, info->tmp_rbuf_count, "rx");
4853 return 1;
4854 }
4855 return 0;
4856 }
4857
4858 static int loopback_test(struct slgt_info *info)
4859 {
4860 #define TESTFRAMESIZE 20
4861
4862 unsigned long timeout;
4863 u16 count = TESTFRAMESIZE;
4864 unsigned char buf[TESTFRAMESIZE];
4865 int rc = -ENODEV;
4866 unsigned long flags;
4867
4868 struct tty_struct *oldtty = info->port.tty;
4869 MGSL_PARAMS params;
4870
4871 memcpy(&params, &info->params, sizeof(params));
4872
4873 info->params.mode = MGSL_MODE_ASYNC;
4874 info->params.data_rate = 921600;
4875 info->params.loopback = 1;
4876 info->port.tty = NULL;
4877
4878 /* build and send transmit frame */
4879 for (count = 0; count < TESTFRAMESIZE; ++count)
4880 buf[count] = (unsigned char)count;
4881
4882 info->tmp_rbuf_count = 0;
4883 memset(info->tmp_rbuf, 0, TESTFRAMESIZE);
4884
4885 /* program hardware for HDLC and enabled receiver */
4886 spin_lock_irqsave(&info->lock,flags);
4887 async_mode(info);
4888 rx_start(info);
4889 info->tx_count = count;
4890 tx_load(info, buf, count);
4891 tx_start(info);
4892 spin_unlock_irqrestore(&info->lock, flags);
4893
4894 /* wait for receive complete */
4895 for (timeout = 100; timeout; --timeout) {
4896 msleep_interruptible(10);
4897 if (loopback_test_rx(info)) {
4898 rc = 0;
4899 break;
4900 }
4901 }
4902
4903 /* verify received frame length and contents */
4904 if (!rc && (info->tmp_rbuf_count != count ||
4905 memcmp(buf, info->tmp_rbuf, count))) {
4906 rc = -ENODEV;
4907 }
4908
4909 spin_lock_irqsave(&info->lock,flags);
4910 reset_adapter(info);
4911 spin_unlock_irqrestore(&info->lock,flags);
4912
4913 memcpy(&info->params, &params, sizeof(info->params));
4914 info->port.tty = oldtty;
4915
4916 info->init_error = rc ? DiagStatus_DmaFailure : 0;
4917 return rc;
4918 }
4919
4920 static int adapter_test(struct slgt_info *info)
4921 {
4922 DBGINFO(("testing %s\n", info->device_name));
4923 if (register_test(info) < 0) {
4924 printk("register test failure %s addr=%08X\n",
4925 info->device_name, info->phys_reg_addr);
4926 } else if (irq_test(info) < 0) {
4927 printk("IRQ test failure %s IRQ=%d\n",
4928 info->device_name, info->irq_level);
4929 } else if (loopback_test(info) < 0) {
4930 printk("loopback test failure %s\n", info->device_name);
4931 }
4932 return info->init_error;
4933 }
4934
4935 /*
4936 * transmit timeout handler
4937 */
4938 static void tx_timeout(unsigned long context)
4939 {
4940 struct slgt_info *info = (struct slgt_info*)context;
4941 unsigned long flags;
4942
4943 DBGINFO(("%s tx_timeout\n", info->device_name));
4944 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
4945 info->icount.txtimeout++;
4946 }
4947 spin_lock_irqsave(&info->lock,flags);
4948 info->tx_active = false;
4949 info->tx_count = 0;
4950 spin_unlock_irqrestore(&info->lock,flags);
4951
4952 #if SYNCLINK_GENERIC_HDLC
4953 if (info->netcount)
4954 hdlcdev_tx_done(info);
4955 else
4956 #endif
4957 bh_transmit(info);
4958 }
4959
4960 /*
4961 * receive buffer polling timer
4962 */
4963 static void rx_timeout(unsigned long context)
4964 {
4965 struct slgt_info *info = (struct slgt_info*)context;
4966 unsigned long flags;
4967
4968 DBGINFO(("%s rx_timeout\n", info->device_name));
4969 spin_lock_irqsave(&info->lock, flags);
4970 info->pending_bh |= BH_RECEIVE;
4971 spin_unlock_irqrestore(&info->lock, flags);
4972 bh_handler(&info->task);
4973 }
4974
Linux kernel - Deliverables
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