2 * Telecom Clock driver for Intel NetStructure(tm) MPCBL0010
4 * Copyright (C) 2005 Kontron Canada
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or (at
11 * your option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
16 * NON INFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * Send feedback to <sebastien.bouchard@ca.kontron.com> and the current
24 * Maintainer <mark.gross@intel.com>
26 * Description : This is the TELECOM CLOCK module driver for the ATCA
27 * MPCBL0010 ATCA computer.
30 #include <linux/module.h>
31 #include <linux/init.h>
32 #include <linux/sched.h>
33 #include <linux/kernel.h> /* printk() */
34 #include <linux/fs.h> /* everything... */
35 #include <linux/errno.h> /* error codes */
36 #include <linux/slab.h>
37 #include <linux/ioport.h>
38 #include <linux/interrupt.h>
39 #include <linux/spinlock.h>
40 #include <linux/timer.h>
41 #include <linux/sysfs.h>
42 #include <linux/device.h>
43 #include <linux/miscdevice.h>
44 #include <linux/platform_device.h>
45 #include <asm/io.h> /* inb/outb */
46 #include <asm/uaccess.h>
48 MODULE_AUTHOR("Sebastien Bouchard <sebastien.bouchard@ca.kontron.com>");
49 MODULE_LICENSE("GPL");
51 /*Hardware Reset of the PLL */
53 #define RESET_OFF 0x01
56 #define NORMAL_MODE 0x00
57 #define HOLDOVER_MODE 0x10
58 #define FREERUN_MODE 0x20
61 #define FILTER_6HZ 0x04
62 #define FILTER_12HZ 0x00
64 /* SELECT REFERENCE FREQUENCY */
65 #define REF_CLK1_8kHz 0x00
66 #define REF_CLK2_19_44MHz 0x02
68 /* Select primary or secondary redundant clock */
69 #define PRIMARY_CLOCK 0x00
70 #define SECONDARY_CLOCK 0x01
72 /* CLOCK TRANSMISSION DEFINE */
74 #define CLK_16_384MHz 0xfb
76 #define CLK_1_544MHz 0x00
77 #define CLK_2_048MHz 0x01
78 #define CLK_4_096MHz 0x02
79 #define CLK_6_312MHz 0x03
80 #define CLK_8_192MHz 0x04
81 #define CLK_19_440MHz 0x06
83 #define CLK_8_592MHz 0x08
84 #define CLK_11_184MHz 0x09
85 #define CLK_34_368MHz 0x0b
86 #define CLK_44_736MHz 0x0a
88 /* RECEIVED REFERENCE */
92 /* HARDWARE SWITCHING DEFINE */
93 #define HW_ENABLE 0x80
94 #define HW_DISABLE 0x00
96 /* HARDWARE SWITCHING MODE DEFINE */
97 #define PLL_HOLDOVER 0x40
98 #define LOST_CLOCK 0x00
101 #define UNLOCK_MASK 0x10
102 #define HOLDOVER_MASK 0x20
103 #define SEC_LOST_MASK 0x40
104 #define PRI_LOST_MASK 0x80
106 /* INTERRUPT CAUSE DEFINE */
108 #define PRI_LOS_01_MASK 0x01
109 #define PRI_LOS_10_MASK 0x02
111 #define SEC_LOS_01_MASK 0x04
112 #define SEC_LOS_10_MASK 0x08
114 #define HOLDOVER_01_MASK 0x10
115 #define HOLDOVER_10_MASK 0x20
117 #define UNLOCK_01_MASK 0x40
118 #define UNLOCK_10_MASK 0x80
120 struct tlclk_alarms
{
122 __u32 lost_primary_clock
;
123 __u32 lost_secondary_clock
;
124 __u32 primary_clock_back
;
125 __u32 secondary_clock_back
;
126 __u32 switchover_primary
;
127 __u32 switchover_secondary
;
129 __u32 pll_end_holdover
;
133 /* Telecom clock I/O register definition */
134 #define TLCLK_BASE 0xa08
135 #define TLCLK_REG0 TLCLK_BASE
136 #define TLCLK_REG1 (TLCLK_BASE+1)
137 #define TLCLK_REG2 (TLCLK_BASE+2)
138 #define TLCLK_REG3 (TLCLK_BASE+3)
139 #define TLCLK_REG4 (TLCLK_BASE+4)
140 #define TLCLK_REG5 (TLCLK_BASE+5)
141 #define TLCLK_REG6 (TLCLK_BASE+6)
142 #define TLCLK_REG7 (TLCLK_BASE+7)
144 #define SET_PORT_BITS(port, mask, val) outb(((inb(port) & mask) | val), port)
146 /* 0 = Dynamic allocation of the major device number */
147 #define TLCLK_MAJOR 0
149 /* sysfs interface definition:
150 Upon loading the driver will create a sysfs directory under
151 /sys/devices/platform/telco_clock.
153 This directory exports the following interfaces. There operation is
154 documented in the MCPBL0010 TPS under the Telecom Clock API section, 11.4.
159 enable_clk3a_output :
160 enable_clk3b_output :
161 enable_clka0_output :
162 enable_clka1_output :
163 enable_clkb0_output :
164 enable_clkb1_output :
167 hardware_switching_mode :
172 select_amcb1_transmit_clock :
173 select_amcb2_transmit_clock :
174 select_redundant_clock :
175 select_ref_frequency :
177 All sysfs interfaces are integers in hex format, i.e echo 99 > refalign
178 has the same effect as echo 0x99 > refalign.
181 static unsigned int telclk_interrupt
;
183 static int int_events
; /* Event that generate a interrupt */
184 static int got_event
; /* if events processing have been done */
186 static void switchover_timeout(unsigned long data
);
187 static struct timer_list switchover_timer
=
188 TIMER_INITIALIZER(switchover_timeout
, 0, 0);
190 static struct tlclk_alarms
*alarm_events
;
192 static DEFINE_SPINLOCK(event_lock
);
194 static int tlclk_major
= TLCLK_MAJOR
;
196 static irqreturn_t
tlclk_interrupt(int irq
, void *dev_id
);
198 static DECLARE_WAIT_QUEUE_HEAD(wq
);
200 static int tlclk_open(struct inode
*inode
, struct file
*filp
)
204 /* Make sure there is no interrupt pending while
205 * initialising interrupt handler */
208 /* This device is wired through the FPGA IO space of the ATCA blade
209 * we can't share this IRQ */
210 result
= request_irq(telclk_interrupt
, &tlclk_interrupt
,
211 IRQF_DISABLED
, "telco_clock", tlclk_interrupt
);
212 if (result
== -EBUSY
) {
213 printk(KERN_ERR
"tlclk: Interrupt can't be reserved.\n");
216 inb(TLCLK_REG6
); /* Clear interrupt events */
221 static int tlclk_release(struct inode
*inode
, struct file
*filp
)
223 free_irq(telclk_interrupt
, tlclk_interrupt
);
228 static ssize_t
tlclk_read(struct file
*filp
, char __user
*buf
, size_t count
,
231 if (count
< sizeof(struct tlclk_alarms
))
234 wait_event_interruptible(wq
, got_event
);
235 if (copy_to_user(buf
, alarm_events
, sizeof(struct tlclk_alarms
)))
238 memset(alarm_events
, 0, sizeof(struct tlclk_alarms
));
241 return sizeof(struct tlclk_alarms
);
244 static ssize_t
tlclk_write(struct file
*filp
, const char __user
*buf
, size_t count
,
250 static const struct file_operations tlclk_fops
= {
252 .write
= tlclk_write
,
254 .release
= tlclk_release
,
258 static struct miscdevice tlclk_miscdev
= {
259 .minor
= MISC_DYNAMIC_MINOR
,
260 .name
= "telco_clock",
264 static ssize_t
show_current_ref(struct device
*d
,
265 struct device_attribute
*attr
, char *buf
)
267 unsigned long ret_val
;
270 spin_lock_irqsave(&event_lock
, flags
);
271 ret_val
= ((inb(TLCLK_REG1
) & 0x08) >> 3);
272 spin_unlock_irqrestore(&event_lock
, flags
);
274 return sprintf(buf
, "0x%lX\n", ret_val
);
277 static DEVICE_ATTR(current_ref
, S_IRUGO
, show_current_ref
, NULL
);
280 static ssize_t
show_telclock_version(struct device
*d
,
281 struct device_attribute
*attr
, char *buf
)
283 unsigned long ret_val
;
286 spin_lock_irqsave(&event_lock
, flags
);
287 ret_val
= inb(TLCLK_REG5
);
288 spin_unlock_irqrestore(&event_lock
, flags
);
290 return sprintf(buf
, "0x%lX\n", ret_val
);
293 static DEVICE_ATTR(telclock_version
, S_IRUGO
,
294 show_telclock_version
, NULL
);
296 static ssize_t
show_alarms(struct device
*d
,
297 struct device_attribute
*attr
, char *buf
)
299 unsigned long ret_val
;
302 spin_lock_irqsave(&event_lock
, flags
);
303 ret_val
= (inb(TLCLK_REG2
) & 0xf0);
304 spin_unlock_irqrestore(&event_lock
, flags
);
306 return sprintf(buf
, "0x%lX\n", ret_val
);
309 static DEVICE_ATTR(alarms
, S_IRUGO
, show_alarms
, NULL
);
311 static ssize_t
store_received_ref_clk3a(struct device
*d
,
312 struct device_attribute
*attr
, const char *buf
, size_t count
)
318 sscanf(buf
, "%lX", &tmp
);
319 dev_dbg(d
, ": tmp = 0x%lX\n", tmp
);
321 val
= (unsigned char)tmp
;
322 spin_lock_irqsave(&event_lock
, flags
);
323 SET_PORT_BITS(TLCLK_REG1
, 0xef, val
);
324 spin_unlock_irqrestore(&event_lock
, flags
);
326 return strnlen(buf
, count
);
329 static DEVICE_ATTR(received_ref_clk3a
, (S_IWUSR
|S_IWGRP
), NULL
,
330 store_received_ref_clk3a
);
333 static ssize_t
store_received_ref_clk3b(struct device
*d
,
334 struct device_attribute
*attr
, const char *buf
, size_t count
)
340 sscanf(buf
, "%lX", &tmp
);
341 dev_dbg(d
, ": tmp = 0x%lX\n", tmp
);
343 val
= (unsigned char)tmp
;
344 spin_lock_irqsave(&event_lock
, flags
);
345 SET_PORT_BITS(TLCLK_REG1
, 0xdf, val
<< 1);
346 spin_unlock_irqrestore(&event_lock
, flags
);
348 return strnlen(buf
, count
);
351 static DEVICE_ATTR(received_ref_clk3b
, (S_IWUSR
|S_IWGRP
), NULL
,
352 store_received_ref_clk3b
);
355 static ssize_t
store_enable_clk3b_output(struct device
*d
,
356 struct device_attribute
*attr
, const char *buf
, size_t count
)
362 sscanf(buf
, "%lX", &tmp
);
363 dev_dbg(d
, ": tmp = 0x%lX\n", tmp
);
365 val
= (unsigned char)tmp
;
366 spin_lock_irqsave(&event_lock
, flags
);
367 SET_PORT_BITS(TLCLK_REG3
, 0x7f, val
<< 7);
368 spin_unlock_irqrestore(&event_lock
, flags
);
370 return strnlen(buf
, count
);
373 static DEVICE_ATTR(enable_clk3b_output
, (S_IWUSR
|S_IWGRP
), NULL
,
374 store_enable_clk3b_output
);
376 static ssize_t
store_enable_clk3a_output(struct device
*d
,
377 struct device_attribute
*attr
, const char *buf
, size_t count
)
383 sscanf(buf
, "%lX", &tmp
);
384 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
386 val
= (unsigned char)tmp
;
387 spin_lock_irqsave(&event_lock
, flags
);
388 SET_PORT_BITS(TLCLK_REG3
, 0xbf, val
<< 6);
389 spin_unlock_irqrestore(&event_lock
, flags
);
391 return strnlen(buf
, count
);
394 static DEVICE_ATTR(enable_clk3a_output
, (S_IWUSR
|S_IWGRP
), NULL
,
395 store_enable_clk3a_output
);
397 static ssize_t
store_enable_clkb1_output(struct device
*d
,
398 struct device_attribute
*attr
, const char *buf
, size_t count
)
404 sscanf(buf
, "%lX", &tmp
);
405 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
407 val
= (unsigned char)tmp
;
408 spin_lock_irqsave(&event_lock
, flags
);
409 SET_PORT_BITS(TLCLK_REG2
, 0xf7, val
<< 3);
410 spin_unlock_irqrestore(&event_lock
, flags
);
412 return strnlen(buf
, count
);
415 static DEVICE_ATTR(enable_clkb1_output
, (S_IWUSR
|S_IWGRP
), NULL
,
416 store_enable_clkb1_output
);
419 static ssize_t
store_enable_clka1_output(struct device
*d
,
420 struct device_attribute
*attr
, const char *buf
, size_t count
)
426 sscanf(buf
, "%lX", &tmp
);
427 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
429 val
= (unsigned char)tmp
;
430 spin_lock_irqsave(&event_lock
, flags
);
431 SET_PORT_BITS(TLCLK_REG2
, 0xfb, val
<< 2);
432 spin_unlock_irqrestore(&event_lock
, flags
);
434 return strnlen(buf
, count
);
437 static DEVICE_ATTR(enable_clka1_output
, (S_IWUSR
|S_IWGRP
), NULL
,
438 store_enable_clka1_output
);
440 static ssize_t
store_enable_clkb0_output(struct device
*d
,
441 struct device_attribute
*attr
, const char *buf
, size_t count
)
447 sscanf(buf
, "%lX", &tmp
);
448 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
450 val
= (unsigned char)tmp
;
451 spin_lock_irqsave(&event_lock
, flags
);
452 SET_PORT_BITS(TLCLK_REG2
, 0xfd, val
<< 1);
453 spin_unlock_irqrestore(&event_lock
, flags
);
455 return strnlen(buf
, count
);
458 static DEVICE_ATTR(enable_clkb0_output
, (S_IWUSR
|S_IWGRP
), NULL
,
459 store_enable_clkb0_output
);
461 static ssize_t
store_enable_clka0_output(struct device
*d
,
462 struct device_attribute
*attr
, const char *buf
, size_t count
)
468 sscanf(buf
, "%lX", &tmp
);
469 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
471 val
= (unsigned char)tmp
;
472 spin_lock_irqsave(&event_lock
, flags
);
473 SET_PORT_BITS(TLCLK_REG2
, 0xfe, val
);
474 spin_unlock_irqrestore(&event_lock
, flags
);
476 return strnlen(buf
, count
);
479 static DEVICE_ATTR(enable_clka0_output
, (S_IWUSR
|S_IWGRP
), NULL
,
480 store_enable_clka0_output
);
482 static ssize_t
store_select_amcb2_transmit_clock(struct device
*d
,
483 struct device_attribute
*attr
, const char *buf
, size_t count
)
489 sscanf(buf
, "%lX", &tmp
);
490 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
492 val
= (unsigned char)tmp
;
493 spin_lock_irqsave(&event_lock
, flags
);
494 if ((val
== CLK_8kHz
) || (val
== CLK_16_384MHz
)) {
495 SET_PORT_BITS(TLCLK_REG3
, 0xc7, 0x28);
496 SET_PORT_BITS(TLCLK_REG1
, 0xfb, ~val
);
497 } else if (val
>= CLK_8_592MHz
) {
498 SET_PORT_BITS(TLCLK_REG3
, 0xc7, 0x38);
501 SET_PORT_BITS(TLCLK_REG0
, 0xfc, 2);
504 SET_PORT_BITS(TLCLK_REG0
, 0xfc, 0);
507 SET_PORT_BITS(TLCLK_REG0
, 0xfc, 3);
510 SET_PORT_BITS(TLCLK_REG0
, 0xfc, 1);
514 SET_PORT_BITS(TLCLK_REG3
, 0xc7, val
<< 3);
516 spin_unlock_irqrestore(&event_lock
, flags
);
518 return strnlen(buf
, count
);
521 static DEVICE_ATTR(select_amcb2_transmit_clock
, (S_IWUSR
|S_IWGRP
), NULL
,
522 store_select_amcb2_transmit_clock
);
524 static ssize_t
store_select_amcb1_transmit_clock(struct device
*d
,
525 struct device_attribute
*attr
, const char *buf
, size_t count
)
531 sscanf(buf
, "%lX", &tmp
);
532 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
534 val
= (unsigned char)tmp
;
535 spin_lock_irqsave(&event_lock
, flags
);
536 if ((val
== CLK_8kHz
) || (val
== CLK_16_384MHz
)) {
537 SET_PORT_BITS(TLCLK_REG3
, 0xf8, 0x5);
538 SET_PORT_BITS(TLCLK_REG1
, 0xfb, ~val
);
539 } else if (val
>= CLK_8_592MHz
) {
540 SET_PORT_BITS(TLCLK_REG3
, 0xf8, 0x7);
543 SET_PORT_BITS(TLCLK_REG0
, 0xfc, 1);
546 SET_PORT_BITS(TLCLK_REG0
, 0xfc, 0);
549 SET_PORT_BITS(TLCLK_REG0
, 0xfc, 3);
552 SET_PORT_BITS(TLCLK_REG0
, 0xfc, 2);
556 SET_PORT_BITS(TLCLK_REG3
, 0xf8, val
);
557 spin_unlock_irqrestore(&event_lock
, flags
);
559 return strnlen(buf
, count
);
562 static DEVICE_ATTR(select_amcb1_transmit_clock
, (S_IWUSR
|S_IWGRP
), NULL
,
563 store_select_amcb1_transmit_clock
);
565 static ssize_t
store_select_redundant_clock(struct device
*d
,
566 struct device_attribute
*attr
, const char *buf
, size_t count
)
572 sscanf(buf
, "%lX", &tmp
);
573 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
575 val
= (unsigned char)tmp
;
576 spin_lock_irqsave(&event_lock
, flags
);
577 SET_PORT_BITS(TLCLK_REG1
, 0xfe, val
);
578 spin_unlock_irqrestore(&event_lock
, flags
);
580 return strnlen(buf
, count
);
583 static DEVICE_ATTR(select_redundant_clock
, (S_IWUSR
|S_IWGRP
), NULL
,
584 store_select_redundant_clock
);
586 static ssize_t
store_select_ref_frequency(struct device
*d
,
587 struct device_attribute
*attr
, const char *buf
, size_t count
)
593 sscanf(buf
, "%lX", &tmp
);
594 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
596 val
= (unsigned char)tmp
;
597 spin_lock_irqsave(&event_lock
, flags
);
598 SET_PORT_BITS(TLCLK_REG1
, 0xfd, val
);
599 spin_unlock_irqrestore(&event_lock
, flags
);
601 return strnlen(buf
, count
);
604 static DEVICE_ATTR(select_ref_frequency
, (S_IWUSR
|S_IWGRP
), NULL
,
605 store_select_ref_frequency
);
607 static ssize_t
store_filter_select(struct device
*d
,
608 struct device_attribute
*attr
, const char *buf
, size_t count
)
614 sscanf(buf
, "%lX", &tmp
);
615 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
617 val
= (unsigned char)tmp
;
618 spin_lock_irqsave(&event_lock
, flags
);
619 SET_PORT_BITS(TLCLK_REG0
, 0xfb, val
);
620 spin_unlock_irqrestore(&event_lock
, flags
);
622 return strnlen(buf
, count
);
625 static DEVICE_ATTR(filter_select
, (S_IWUSR
|S_IWGRP
), NULL
, store_filter_select
);
627 static ssize_t
store_hardware_switching_mode(struct device
*d
,
628 struct device_attribute
*attr
, const char *buf
, size_t count
)
634 sscanf(buf
, "%lX", &tmp
);
635 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
637 val
= (unsigned char)tmp
;
638 spin_lock_irqsave(&event_lock
, flags
);
639 SET_PORT_BITS(TLCLK_REG0
, 0xbf, val
);
640 spin_unlock_irqrestore(&event_lock
, flags
);
642 return strnlen(buf
, count
);
645 static DEVICE_ATTR(hardware_switching_mode
, (S_IWUSR
|S_IWGRP
), NULL
,
646 store_hardware_switching_mode
);
648 static ssize_t
store_hardware_switching(struct device
*d
,
649 struct device_attribute
*attr
, const char *buf
, size_t count
)
655 sscanf(buf
, "%lX", &tmp
);
656 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
658 val
= (unsigned char)tmp
;
659 spin_lock_irqsave(&event_lock
, flags
);
660 SET_PORT_BITS(TLCLK_REG0
, 0x7f, val
);
661 spin_unlock_irqrestore(&event_lock
, flags
);
663 return strnlen(buf
, count
);
666 static DEVICE_ATTR(hardware_switching
, (S_IWUSR
|S_IWGRP
), NULL
,
667 store_hardware_switching
);
669 static ssize_t
store_refalign (struct device
*d
,
670 struct device_attribute
*attr
, const char *buf
, size_t count
)
675 sscanf(buf
, "%lX", &tmp
);
676 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
677 spin_lock_irqsave(&event_lock
, flags
);
678 SET_PORT_BITS(TLCLK_REG0
, 0xf7, 0);
679 SET_PORT_BITS(TLCLK_REG0
, 0xf7, 0x08);
680 SET_PORT_BITS(TLCLK_REG0
, 0xf7, 0);
681 spin_unlock_irqrestore(&event_lock
, flags
);
683 return strnlen(buf
, count
);
686 static DEVICE_ATTR(refalign
, (S_IWUSR
|S_IWGRP
), NULL
, store_refalign
);
688 static ssize_t
store_mode_select (struct device
*d
,
689 struct device_attribute
*attr
, const char *buf
, size_t count
)
695 sscanf(buf
, "%lX", &tmp
);
696 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
698 val
= (unsigned char)tmp
;
699 spin_lock_irqsave(&event_lock
, flags
);
700 SET_PORT_BITS(TLCLK_REG0
, 0xcf, val
);
701 spin_unlock_irqrestore(&event_lock
, flags
);
703 return strnlen(buf
, count
);
706 static DEVICE_ATTR(mode_select
, (S_IWUSR
|S_IWGRP
), NULL
, store_mode_select
);
708 static ssize_t
store_reset (struct device
*d
,
709 struct device_attribute
*attr
, const char *buf
, size_t count
)
715 sscanf(buf
, "%lX", &tmp
);
716 dev_dbg(d
, "tmp = 0x%lX\n", tmp
);
718 val
= (unsigned char)tmp
;
719 spin_lock_irqsave(&event_lock
, flags
);
720 SET_PORT_BITS(TLCLK_REG4
, 0xfd, val
);
721 spin_unlock_irqrestore(&event_lock
, flags
);
723 return strnlen(buf
, count
);
726 static DEVICE_ATTR(reset
, (S_IWUSR
|S_IWGRP
), NULL
, store_reset
);
728 static struct attribute
*tlclk_sysfs_entries
[] = {
729 &dev_attr_current_ref
.attr
,
730 &dev_attr_telclock_version
.attr
,
731 &dev_attr_alarms
.attr
,
732 &dev_attr_received_ref_clk3a
.attr
,
733 &dev_attr_received_ref_clk3b
.attr
,
734 &dev_attr_enable_clk3a_output
.attr
,
735 &dev_attr_enable_clk3b_output
.attr
,
736 &dev_attr_enable_clkb1_output
.attr
,
737 &dev_attr_enable_clka1_output
.attr
,
738 &dev_attr_enable_clkb0_output
.attr
,
739 &dev_attr_enable_clka0_output
.attr
,
740 &dev_attr_select_amcb1_transmit_clock
.attr
,
741 &dev_attr_select_amcb2_transmit_clock
.attr
,
742 &dev_attr_select_redundant_clock
.attr
,
743 &dev_attr_select_ref_frequency
.attr
,
744 &dev_attr_filter_select
.attr
,
745 &dev_attr_hardware_switching_mode
.attr
,
746 &dev_attr_hardware_switching
.attr
,
747 &dev_attr_refalign
.attr
,
748 &dev_attr_mode_select
.attr
,
749 &dev_attr_reset
.attr
,
753 static struct attribute_group tlclk_attribute_group
= {
754 .name
= NULL
, /* put in device directory */
755 .attrs
= tlclk_sysfs_entries
,
758 static struct platform_device
*tlclk_device
;
760 static int __init
tlclk_init(void)
764 ret
= register_chrdev(tlclk_major
, "telco_clock", &tlclk_fops
);
766 printk(KERN_ERR
"tlclk: can't get major %d.\n", tlclk_major
);
770 alarm_events
= kzalloc( sizeof(struct tlclk_alarms
), GFP_KERNEL
);
774 /* Read telecom clock IRQ number (Set by BIOS) */
775 if (!request_region(TLCLK_BASE
, 8, "telco_clock")) {
776 printk(KERN_ERR
"tlclk: request_region 0x%X failed.\n",
781 telclk_interrupt
= (inb(TLCLK_REG7
) & 0x0f);
783 if (0x0F == telclk_interrupt
) { /* not MCPBL0010 ? */
784 printk(KERN_ERR
"telclk_interrup = 0x%x non-mcpbl0010 hw.\n",
790 init_timer(&switchover_timer
);
792 ret
= misc_register(&tlclk_miscdev
);
794 printk(KERN_ERR
"tlclk: misc_register returns %d.\n", ret
);
798 tlclk_device
= platform_device_register_simple("telco_clock",
800 if (IS_ERR(tlclk_device
)) {
801 printk(KERN_ERR
"tlclk: platform_device_register failed.\n");
802 ret
= PTR_ERR(tlclk_device
);
806 ret
= sysfs_create_group(&tlclk_device
->dev
.kobj
,
807 &tlclk_attribute_group
);
809 printk(KERN_ERR
"tlclk: failed to create sysfs device attributes.\n");
815 platform_device_unregister(tlclk_device
);
817 misc_deregister(&tlclk_miscdev
);
819 release_region(TLCLK_BASE
, 8);
823 unregister_chrdev(tlclk_major
, "telco_clock");
827 static void __exit
tlclk_cleanup(void)
829 sysfs_remove_group(&tlclk_device
->dev
.kobj
, &tlclk_attribute_group
);
830 platform_device_unregister(tlclk_device
);
831 misc_deregister(&tlclk_miscdev
);
832 unregister_chrdev(tlclk_major
, "telco_clock");
834 release_region(TLCLK_BASE
, 8);
835 del_timer_sync(&switchover_timer
);
840 static void switchover_timeout(unsigned long data
)
843 if ((inb(TLCLK_REG1
) & 0x08) != (data
& 0x08))
844 alarm_events
->switchover_primary
++;
846 if ((inb(TLCLK_REG1
) & 0x08) != (data
& 0x08))
847 alarm_events
->switchover_secondary
++;
850 /* Alarm processing is done, wake up read task */
851 del_timer(&switchover_timer
);
856 static irqreturn_t
tlclk_interrupt(int irq
, void *dev_id
)
860 spin_lock_irqsave(&event_lock
, flags
);
861 /* Read and clear interrupt events */
862 int_events
= inb(TLCLK_REG6
);
864 /* Primary_Los changed from 0 to 1 ? */
865 if (int_events
& PRI_LOS_01_MASK
) {
866 if (inb(TLCLK_REG2
) & SEC_LOST_MASK
)
867 alarm_events
->lost_clocks
++;
869 alarm_events
->lost_primary_clock
++;
872 /* Primary_Los changed from 1 to 0 ? */
873 if (int_events
& PRI_LOS_10_MASK
) {
874 alarm_events
->primary_clock_back
++;
875 SET_PORT_BITS(TLCLK_REG1
, 0xFE, 1);
877 /* Secondary_Los changed from 0 to 1 ? */
878 if (int_events
& SEC_LOS_01_MASK
) {
879 if (inb(TLCLK_REG2
) & PRI_LOST_MASK
)
880 alarm_events
->lost_clocks
++;
882 alarm_events
->lost_secondary_clock
++;
884 /* Secondary_Los changed from 1 to 0 ? */
885 if (int_events
& SEC_LOS_10_MASK
) {
886 alarm_events
->secondary_clock_back
++;
887 SET_PORT_BITS(TLCLK_REG1
, 0xFE, 0);
889 if (int_events
& HOLDOVER_10_MASK
)
890 alarm_events
->pll_end_holdover
++;
892 if (int_events
& UNLOCK_01_MASK
)
893 alarm_events
->pll_lost_sync
++;
895 if (int_events
& UNLOCK_10_MASK
)
896 alarm_events
->pll_sync
++;
898 /* Holdover changed from 0 to 1 ? */
899 if (int_events
& HOLDOVER_01_MASK
) {
900 alarm_events
->pll_holdover
++;
902 /* TIMEOUT in ~10ms */
903 switchover_timer
.expires
= jiffies
+ msecs_to_jiffies(10);
904 switchover_timer
.data
= inb(TLCLK_REG1
);
905 add_timer(&switchover_timer
);
910 spin_unlock_irqrestore(&event_lock
, flags
);
915 module_init(tlclk_init
);
916 module_exit(tlclk_cleanup
);