2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Adjustable divider clock implementation
13 #include <linux/clk-provider.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
17 #include <linux/err.h>
18 #include <linux/string.h>
19 #include <linux/log2.h>
22 * DOC: basic adjustable divider clock that cannot gate
24 * Traits of this clock:
25 * prepare - clk_prepare only ensures that parents are prepared
26 * enable - clk_enable only ensures that parents are enabled
27 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
28 * parent - fixed parent. No clk_set_parent support
31 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
33 #define div_mask(width) ((1 << (width)) - 1)
35 static unsigned int _get_table_maxdiv(const struct clk_div_table
*table
,
38 unsigned int maxdiv
= 0, mask
= div_mask(width
);
39 const struct clk_div_table
*clkt
;
41 for (clkt
= table
; clkt
->div
; clkt
++)
42 if (clkt
->div
> maxdiv
&& clkt
->val
<= mask
)
47 static unsigned int _get_table_mindiv(const struct clk_div_table
*table
)
49 unsigned int mindiv
= UINT_MAX
;
50 const struct clk_div_table
*clkt
;
52 for (clkt
= table
; clkt
->div
; clkt
++)
53 if (clkt
->div
< mindiv
)
58 static unsigned int _get_maxdiv(const struct clk_div_table
*table
, u8 width
,
61 if (flags
& CLK_DIVIDER_ONE_BASED
)
62 return div_mask(width
);
63 if (flags
& CLK_DIVIDER_POWER_OF_TWO
)
64 return 1 << div_mask(width
);
66 return _get_table_maxdiv(table
, width
);
67 return div_mask(width
) + 1;
70 static unsigned int _get_table_div(const struct clk_div_table
*table
,
73 const struct clk_div_table
*clkt
;
75 for (clkt
= table
; clkt
->div
; clkt
++)
81 static unsigned int _get_div(const struct clk_div_table
*table
,
82 unsigned int val
, unsigned long flags
, u8 width
)
84 if (flags
& CLK_DIVIDER_ONE_BASED
)
86 if (flags
& CLK_DIVIDER_POWER_OF_TWO
)
88 if (flags
& CLK_DIVIDER_MAX_AT_ZERO
)
89 return val
? val
: div_mask(width
) + 1;
91 return _get_table_div(table
, val
);
95 static unsigned int _get_table_val(const struct clk_div_table
*table
,
98 const struct clk_div_table
*clkt
;
100 for (clkt
= table
; clkt
->div
; clkt
++)
101 if (clkt
->div
== div
)
106 static unsigned int _get_val(const struct clk_div_table
*table
,
107 unsigned int div
, unsigned long flags
, u8 width
)
109 if (flags
& CLK_DIVIDER_ONE_BASED
)
111 if (flags
& CLK_DIVIDER_POWER_OF_TWO
)
113 if (flags
& CLK_DIVIDER_MAX_AT_ZERO
)
114 return (div
== div_mask(width
) + 1) ? 0 : div
;
116 return _get_table_val(table
, div
);
120 unsigned long divider_recalc_rate(struct clk_hw
*hw
, unsigned long parent_rate
,
122 const struct clk_div_table
*table
,
125 struct clk_divider
*divider
= to_clk_divider(hw
);
128 div
= _get_div(table
, val
, flags
, divider
->width
);
130 WARN(!(flags
& CLK_DIVIDER_ALLOW_ZERO
),
131 "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
132 clk_hw_get_name(hw
));
136 return DIV_ROUND_UP_ULL((u64
)parent_rate
, div
);
138 EXPORT_SYMBOL_GPL(divider_recalc_rate
);
140 static unsigned long clk_divider_recalc_rate(struct clk_hw
*hw
,
141 unsigned long parent_rate
)
143 struct clk_divider
*divider
= to_clk_divider(hw
);
146 val
= clk_readl(divider
->reg
) >> divider
->shift
;
147 val
&= div_mask(divider
->width
);
149 return divider_recalc_rate(hw
, parent_rate
, val
, divider
->table
,
153 static bool _is_valid_table_div(const struct clk_div_table
*table
,
156 const struct clk_div_table
*clkt
;
158 for (clkt
= table
; clkt
->div
; clkt
++)
159 if (clkt
->div
== div
)
164 static bool _is_valid_div(const struct clk_div_table
*table
, unsigned int div
,
167 if (flags
& CLK_DIVIDER_POWER_OF_TWO
)
168 return is_power_of_2(div
);
170 return _is_valid_table_div(table
, div
);
174 static int _round_up_table(const struct clk_div_table
*table
, int div
)
176 const struct clk_div_table
*clkt
;
179 for (clkt
= table
; clkt
->div
; clkt
++) {
180 if (clkt
->div
== div
)
182 else if (clkt
->div
< div
)
185 if ((clkt
->div
- div
) < (up
- div
))
192 static int _round_down_table(const struct clk_div_table
*table
, int div
)
194 const struct clk_div_table
*clkt
;
195 int down
= _get_table_mindiv(table
);
197 for (clkt
= table
; clkt
->div
; clkt
++) {
198 if (clkt
->div
== div
)
200 else if (clkt
->div
> div
)
203 if ((div
- clkt
->div
) < (div
- down
))
210 static int _div_round_up(const struct clk_div_table
*table
,
211 unsigned long parent_rate
, unsigned long rate
,
214 int div
= DIV_ROUND_UP_ULL((u64
)parent_rate
, rate
);
216 if (flags
& CLK_DIVIDER_POWER_OF_TWO
)
217 div
= __roundup_pow_of_two(div
);
219 div
= _round_up_table(table
, div
);
224 static int _div_round_closest(const struct clk_div_table
*table
,
225 unsigned long parent_rate
, unsigned long rate
,
229 unsigned long up_rate
, down_rate
;
231 up
= DIV_ROUND_UP_ULL((u64
)parent_rate
, rate
);
232 down
= parent_rate
/ rate
;
234 if (flags
& CLK_DIVIDER_POWER_OF_TWO
) {
235 up
= __roundup_pow_of_two(up
);
236 down
= __rounddown_pow_of_two(down
);
238 up
= _round_up_table(table
, up
);
239 down
= _round_down_table(table
, down
);
242 up_rate
= DIV_ROUND_UP_ULL((u64
)parent_rate
, up
);
243 down_rate
= DIV_ROUND_UP_ULL((u64
)parent_rate
, down
);
245 return (rate
- up_rate
) <= (down_rate
- rate
) ? up
: down
;
248 static int _div_round(const struct clk_div_table
*table
,
249 unsigned long parent_rate
, unsigned long rate
,
252 if (flags
& CLK_DIVIDER_ROUND_CLOSEST
)
253 return _div_round_closest(table
, parent_rate
, rate
, flags
);
255 return _div_round_up(table
, parent_rate
, rate
, flags
);
258 static bool _is_best_div(unsigned long rate
, unsigned long now
,
259 unsigned long best
, unsigned long flags
)
261 if (flags
& CLK_DIVIDER_ROUND_CLOSEST
)
262 return abs(rate
- now
) < abs(rate
- best
);
264 return now
<= rate
&& now
> best
;
267 static int _next_div(const struct clk_div_table
*table
, int div
,
272 if (flags
& CLK_DIVIDER_POWER_OF_TWO
)
273 return __roundup_pow_of_two(div
);
275 return _round_up_table(table
, div
);
280 static int clk_divider_bestdiv(struct clk_hw
*hw
, unsigned long rate
,
281 unsigned long *best_parent_rate
,
282 const struct clk_div_table
*table
, u8 width
,
286 unsigned long parent_rate
, best
= 0, now
, maxdiv
;
287 unsigned long parent_rate_saved
= *best_parent_rate
;
292 maxdiv
= _get_maxdiv(table
, width
, flags
);
294 if (!(clk_hw_get_flags(hw
) & CLK_SET_RATE_PARENT
)) {
295 parent_rate
= *best_parent_rate
;
296 bestdiv
= _div_round(table
, parent_rate
, rate
, flags
);
297 bestdiv
= bestdiv
== 0 ? 1 : bestdiv
;
298 bestdiv
= bestdiv
> maxdiv
? maxdiv
: bestdiv
;
303 * The maximum divider we can use without overflowing
304 * unsigned long in rate * i below
306 maxdiv
= min(ULONG_MAX
/ rate
, maxdiv
);
308 for (i
= 1; i
<= maxdiv
; i
= _next_div(table
, i
, flags
)) {
309 if (!_is_valid_div(table
, i
, flags
))
311 if (rate
* i
== parent_rate_saved
) {
313 * It's the most ideal case if the requested rate can be
314 * divided from parent clock without needing to change
315 * parent rate, so return the divider immediately.
317 *best_parent_rate
= parent_rate_saved
;
320 parent_rate
= clk_hw_round_rate(clk_hw_get_parent(hw
),
322 now
= DIV_ROUND_UP_ULL((u64
)parent_rate
, i
);
323 if (_is_best_div(rate
, now
, best
, flags
)) {
326 *best_parent_rate
= parent_rate
;
331 bestdiv
= _get_maxdiv(table
, width
, flags
);
332 *best_parent_rate
= clk_hw_round_rate(clk_hw_get_parent(hw
), 1);
338 long divider_round_rate(struct clk_hw
*hw
, unsigned long rate
,
339 unsigned long *prate
, const struct clk_div_table
*table
,
340 u8 width
, unsigned long flags
)
344 div
= clk_divider_bestdiv(hw
, rate
, prate
, table
, width
, flags
);
346 return DIV_ROUND_UP_ULL((u64
)*prate
, div
);
348 EXPORT_SYMBOL_GPL(divider_round_rate
);
350 static long clk_divider_round_rate(struct clk_hw
*hw
, unsigned long rate
,
351 unsigned long *prate
)
353 struct clk_divider
*divider
= to_clk_divider(hw
);
356 /* if read only, just return current value */
357 if (divider
->flags
& CLK_DIVIDER_READ_ONLY
) {
358 bestdiv
= readl(divider
->reg
) >> divider
->shift
;
359 bestdiv
&= div_mask(divider
->width
);
360 bestdiv
= _get_div(divider
->table
, bestdiv
, divider
->flags
,
362 return DIV_ROUND_UP_ULL((u64
)*prate
, bestdiv
);
365 return divider_round_rate(hw
, rate
, prate
, divider
->table
,
366 divider
->width
, divider
->flags
);
369 int divider_get_val(unsigned long rate
, unsigned long parent_rate
,
370 const struct clk_div_table
*table
, u8 width
,
373 unsigned int div
, value
;
375 div
= DIV_ROUND_UP_ULL((u64
)parent_rate
, rate
);
377 if (!_is_valid_div(table
, div
, flags
))
380 value
= _get_val(table
, div
, flags
, width
);
382 return min_t(unsigned int, value
, div_mask(width
));
384 EXPORT_SYMBOL_GPL(divider_get_val
);
386 static int clk_divider_set_rate(struct clk_hw
*hw
, unsigned long rate
,
387 unsigned long parent_rate
)
389 struct clk_divider
*divider
= to_clk_divider(hw
);
391 unsigned long flags
= 0;
394 value
= divider_get_val(rate
, parent_rate
, divider
->table
,
395 divider
->width
, divider
->flags
);
398 spin_lock_irqsave(divider
->lock
, flags
);
400 __acquire(divider
->lock
);
402 if (divider
->flags
& CLK_DIVIDER_HIWORD_MASK
) {
403 val
= div_mask(divider
->width
) << (divider
->shift
+ 16);
405 val
= clk_readl(divider
->reg
);
406 val
&= ~(div_mask(divider
->width
) << divider
->shift
);
408 val
|= value
<< divider
->shift
;
409 clk_writel(val
, divider
->reg
);
412 spin_unlock_irqrestore(divider
->lock
, flags
);
414 __release(divider
->lock
);
419 const struct clk_ops clk_divider_ops
= {
420 .recalc_rate
= clk_divider_recalc_rate
,
421 .round_rate
= clk_divider_round_rate
,
422 .set_rate
= clk_divider_set_rate
,
424 EXPORT_SYMBOL_GPL(clk_divider_ops
);
426 static struct clk
*_register_divider(struct device
*dev
, const char *name
,
427 const char *parent_name
, unsigned long flags
,
428 void __iomem
*reg
, u8 shift
, u8 width
,
429 u8 clk_divider_flags
, const struct clk_div_table
*table
,
432 struct clk_divider
*div
;
434 struct clk_init_data init
;
436 if (clk_divider_flags
& CLK_DIVIDER_HIWORD_MASK
) {
437 if (width
+ shift
> 16) {
438 pr_warn("divider value exceeds LOWORD field\n");
439 return ERR_PTR(-EINVAL
);
443 /* allocate the divider */
444 div
= kzalloc(sizeof(*div
), GFP_KERNEL
);
446 return ERR_PTR(-ENOMEM
);
449 init
.ops
= &clk_divider_ops
;
450 init
.flags
= flags
| CLK_IS_BASIC
;
451 init
.parent_names
= (parent_name
? &parent_name
: NULL
);
452 init
.num_parents
= (parent_name
? 1 : 0);
454 /* struct clk_divider assignments */
458 div
->flags
= clk_divider_flags
;
460 div
->hw
.init
= &init
;
463 /* register the clock */
464 clk
= clk_register(dev
, &div
->hw
);
473 * clk_register_divider - register a divider clock with the clock framework
474 * @dev: device registering this clock
475 * @name: name of this clock
476 * @parent_name: name of clock's parent
477 * @flags: framework-specific flags
478 * @reg: register address to adjust divider
479 * @shift: number of bits to shift the bitfield
480 * @width: width of the bitfield
481 * @clk_divider_flags: divider-specific flags for this clock
482 * @lock: shared register lock for this clock
484 struct clk
*clk_register_divider(struct device
*dev
, const char *name
,
485 const char *parent_name
, unsigned long flags
,
486 void __iomem
*reg
, u8 shift
, u8 width
,
487 u8 clk_divider_flags
, spinlock_t
*lock
)
489 return _register_divider(dev
, name
, parent_name
, flags
, reg
, shift
,
490 width
, clk_divider_flags
, NULL
, lock
);
492 EXPORT_SYMBOL_GPL(clk_register_divider
);
495 * clk_register_divider_table - register a table based divider clock with
496 * the clock framework
497 * @dev: device registering this clock
498 * @name: name of this clock
499 * @parent_name: name of clock's parent
500 * @flags: framework-specific flags
501 * @reg: register address to adjust divider
502 * @shift: number of bits to shift the bitfield
503 * @width: width of the bitfield
504 * @clk_divider_flags: divider-specific flags for this clock
505 * @table: array of divider/value pairs ending with a div set to 0
506 * @lock: shared register lock for this clock
508 struct clk
*clk_register_divider_table(struct device
*dev
, const char *name
,
509 const char *parent_name
, unsigned long flags
,
510 void __iomem
*reg
, u8 shift
, u8 width
,
511 u8 clk_divider_flags
, const struct clk_div_table
*table
,
514 return _register_divider(dev
, name
, parent_name
, flags
, reg
, shift
,
515 width
, clk_divider_flags
, table
, lock
);
517 EXPORT_SYMBOL_GPL(clk_register_divider_table
);
519 void clk_unregister_divider(struct clk
*clk
)
521 struct clk_divider
*div
;
524 hw
= __clk_get_hw(clk
);
528 div
= to_clk_divider(hw
);
533 EXPORT_SYMBOL_GPL(clk_unregister_divider
);