clk: imx6ul: fix gpt2 clock names
[deliverable/linux.git] / drivers / clk / clk-fixed-factor.c
1 /*
2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Standard functionality for the common clock API.
9 */
10 #include <linux/module.h>
11 #include <linux/clk-provider.h>
12 #include <linux/slab.h>
13 #include <linux/err.h>
14 #include <linux/of.h>
15
16 /*
17 * DOC: basic fixed multiplier and divider clock that cannot gate
18 *
19 * Traits of this clock:
20 * prepare - clk_prepare only ensures that parents are prepared
21 * enable - clk_enable only ensures that parents are enabled
22 * rate - rate is fixed. clk->rate = parent->rate / div * mult
23 * parent - fixed parent. No clk_set_parent support
24 */
25
26 static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
27 unsigned long parent_rate)
28 {
29 struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
30 unsigned long long int rate;
31
32 rate = (unsigned long long int)parent_rate * fix->mult;
33 do_div(rate, fix->div);
34 return (unsigned long)rate;
35 }
36
37 static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate,
38 unsigned long *prate)
39 {
40 struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
41
42 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
43 unsigned long best_parent;
44
45 best_parent = (rate / fix->mult) * fix->div;
46 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
47 }
48
49 return (*prate / fix->div) * fix->mult;
50 }
51
52 static int clk_factor_set_rate(struct clk_hw *hw, unsigned long rate,
53 unsigned long parent_rate)
54 {
55 /*
56 * We must report success but we can do so unconditionally because
57 * clk_factor_round_rate returns values that ensure this call is a
58 * nop.
59 */
60
61 return 0;
62 }
63
64 const struct clk_ops clk_fixed_factor_ops = {
65 .round_rate = clk_factor_round_rate,
66 .set_rate = clk_factor_set_rate,
67 .recalc_rate = clk_factor_recalc_rate,
68 };
69 EXPORT_SYMBOL_GPL(clk_fixed_factor_ops);
70
71 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
72 const char *name, const char *parent_name, unsigned long flags,
73 unsigned int mult, unsigned int div)
74 {
75 struct clk_fixed_factor *fix;
76 struct clk_init_data init;
77 struct clk_hw *hw;
78 int ret;
79
80 fix = kmalloc(sizeof(*fix), GFP_KERNEL);
81 if (!fix)
82 return ERR_PTR(-ENOMEM);
83
84 /* struct clk_fixed_factor assignments */
85 fix->mult = mult;
86 fix->div = div;
87 fix->hw.init = &init;
88
89 init.name = name;
90 init.ops = &clk_fixed_factor_ops;
91 init.flags = flags | CLK_IS_BASIC;
92 init.parent_names = &parent_name;
93 init.num_parents = 1;
94
95 hw = &fix->hw;
96 ret = clk_hw_register(dev, hw);
97 if (ret) {
98 kfree(fix);
99 hw = ERR_PTR(ret);
100 }
101
102 return hw;
103 }
104 EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor);
105
106 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
107 const char *parent_name, unsigned long flags,
108 unsigned int mult, unsigned int div)
109 {
110 struct clk_hw *hw;
111
112 hw = clk_hw_register_fixed_factor(dev, name, parent_name, flags, mult,
113 div);
114 if (IS_ERR(hw))
115 return ERR_CAST(hw);
116 return hw->clk;
117 }
118 EXPORT_SYMBOL_GPL(clk_register_fixed_factor);
119
120 void clk_unregister_fixed_factor(struct clk *clk)
121 {
122 struct clk_hw *hw;
123
124 hw = __clk_get_hw(clk);
125 if (!hw)
126 return;
127
128 clk_unregister(clk);
129 kfree(to_clk_fixed_factor(hw));
130 }
131 EXPORT_SYMBOL_GPL(clk_unregister_fixed_factor);
132
133 void clk_hw_unregister_fixed_factor(struct clk_hw *hw)
134 {
135 struct clk_fixed_factor *fix;
136
137 fix = to_clk_fixed_factor(hw);
138
139 clk_hw_unregister(hw);
140 kfree(fix);
141 }
142 EXPORT_SYMBOL_GPL(clk_hw_unregister_fixed_factor);
143
144 #ifdef CONFIG_OF
145 /**
146 * of_fixed_factor_clk_setup() - Setup function for simple fixed factor clock
147 */
148 void __init of_fixed_factor_clk_setup(struct device_node *node)
149 {
150 struct clk *clk;
151 const char *clk_name = node->name;
152 const char *parent_name;
153 u32 div, mult;
154
155 if (of_property_read_u32(node, "clock-div", &div)) {
156 pr_err("%s Fixed factor clock <%s> must have a clock-div property\n",
157 __func__, node->name);
158 return;
159 }
160
161 if (of_property_read_u32(node, "clock-mult", &mult)) {
162 pr_err("%s Fixed factor clock <%s> must have a clock-mult property\n",
163 __func__, node->name);
164 return;
165 }
166
167 of_property_read_string(node, "clock-output-names", &clk_name);
168 parent_name = of_clk_get_parent_name(node, 0);
169
170 clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0,
171 mult, div);
172 if (!IS_ERR(clk))
173 of_clk_add_provider(node, of_clk_src_simple_get, clk);
174 }
175 EXPORT_SYMBOL_GPL(of_fixed_factor_clk_setup);
176 CLK_OF_DECLARE(fixed_factor_clk, "fixed-factor-clock",
177 of_fixed_factor_clk_setup);
178 #endif
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