drivers/clk/clk-gate.c

   1 /*
   2  * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
   3  * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * Gated clock implementation
  10  */
  11
  12 #include <linux/clk-provider.h>
  13 #include <linux/module.h>
  14 #include <linux/slab.h>
  15 #include <linux/io.h>
  16 #include <linux/err.h>
  17 #include <linux/string.h>
  18
  19 /**
  20  * DOC: basic gatable clock which can gate and ungate it's ouput
  21  *
  22  * Traits of this clock:
  23  * prepare - clk_(un)prepare only ensures parent is (un)prepared
  24  * enable - clk_enable and clk_disable are functional & control gating
  25  * rate - inherits rate from parent.  No clk_set_rate support
  26  * parent - fixed parent.  No clk_set_parent support
  27  */
  28
  29 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
  30
  31 /*
  32  * It works on following logic:
  33  *
  34  * For enabling clock, enable = 1
  35  *      set2dis = 1     -> clear bit    -> set = 0
  36  *      set2dis = 0     -> set bit      -> set = 1
  37  *
  38  * For disabling clock, enable = 0
  39  *      set2dis = 1     -> set bit      -> set = 1
  40  *      set2dis = 0     -> clear bit    -> set = 0
  41  *
  42  * So, result is always: enable xor set2dis.
  43  */
  44 static void clk_gate_endisable(struct clk_hw *hw, int enable)
  45 {
  46         struct clk_gate *gate = to_clk_gate(hw);
  47         int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
  48         unsigned long uninitialized_var(flags);
  49         u32 reg;
  50
  51         set ^= enable;
  52
  53         if (gate->lock)
  54                 spin_lock_irqsave(gate->lock, flags);
  55         else
  56                 __acquire(gate->lock);
  57
  58         if (gate->flags & CLK_GATE_HIWORD_MASK) {
  59                 reg = BIT(gate->bit_idx + 16);
  60                 if (set)
  61                         reg |= BIT(gate->bit_idx);
  62         } else {
  63                 reg = clk_readl(gate->reg);
  64
  65                 if (set)
  66                         reg |= BIT(gate->bit_idx);
  67                 else
  68                         reg &= ~BIT(gate->bit_idx);
  69         }
  70
  71         clk_writel(reg, gate->reg);
  72
  73         if (gate->lock)
  74                 spin_unlock_irqrestore(gate->lock, flags);
  75         else
  76                 __release(gate->lock);
  77 }
  78
  79 static int clk_gate_enable(struct clk_hw *hw)
  80 {
  81         clk_gate_endisable(hw, 1);
  82
  83         return 0;
  84 }
  85
  86 static void clk_gate_disable(struct clk_hw *hw)
  87 {
  88         clk_gate_endisable(hw, 0);
  89 }
  90
  91 static int clk_gate_is_enabled(struct clk_hw *hw)
  92 {
  93         u32 reg;
  94         struct clk_gate *gate = to_clk_gate(hw);
  95
  96         reg = clk_readl(gate->reg);
  97
  98         /* if a set bit disables this clk, flip it before masking */
  99         if (gate->flags & CLK_GATE_SET_TO_DISABLE)
 100                 reg ^= BIT(gate->bit_idx);
 101
 102         reg &= BIT(gate->bit_idx);
 103
 104         return reg ? 1 : 0;
 105 }
 106
 107 const struct clk_ops clk_gate_ops = {
 108         .enable = clk_gate_enable,
 109         .disable = clk_gate_disable,
 110         .is_enabled = clk_gate_is_enabled,
 111 };
 112 EXPORT_SYMBOL_GPL(clk_gate_ops);
 113
 114 /**
 115  * clk_register_gate - register a gate clock with the clock framework
 116  * @dev: device that is registering this clock
 117  * @name: name of this clock
 118  * @parent_name: name of this clock's parent
 119  * @flags: framework-specific flags for this clock
 120  * @reg: register address to control gating of this clock
 121  * @bit_idx: which bit in the register controls gating of this clock
 122  * @clk_gate_flags: gate-specific flags for this clock
 123  * @lock: shared register lock for this clock
 124  */
 125 struct clk *clk_register_gate(struct device *dev, const char *name,
 126                 const char *parent_name, unsigned long flags,
 127                 void __iomem *reg, u8 bit_idx,
 128                 u8 clk_gate_flags, spinlock_t *lock)
 129 {
 130         struct clk_gate *gate;
 131         struct clk *clk;
 132         struct clk_init_data init;
 133
 134         if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
 135                 if (bit_idx > 15) {
 136                         pr_err("gate bit exceeds LOWORD field\n");
 137                         return ERR_PTR(-EINVAL);
 138                 }
 139         }
 140
 141         /* allocate the gate */
 142         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
 143         if (!gate)
 144                 return ERR_PTR(-ENOMEM);
 145
 146         init.name = name;
 147         init.ops = &clk_gate_ops;
 148         init.flags = flags | CLK_IS_BASIC;
 149         init.parent_names = (parent_name ? &parent_name: NULL);
 150         init.num_parents = (parent_name ? 1 : 0);
 151
 152         /* struct clk_gate assignments */
 153         gate->reg = reg;
 154         gate->bit_idx = bit_idx;
 155         gate->flags = clk_gate_flags;
 156         gate->lock = lock;
 157         gate->hw.init = &init;
 158
 159         clk = clk_register(dev, &gate->hw);
 160
 161         if (IS_ERR(clk))
 162                 kfree(gate);
 163
 164         return clk;
 165 }
 166 EXPORT_SYMBOL_GPL(clk_register_gate);
 167
 168 void clk_unregister_gate(struct clk *clk)
 169 {
 170         struct clk_gate *gate;
 171         struct clk_hw *hw;
 172
 173         hw = __clk_get_hw(clk);
 174         if (!hw)
 175                 return;
 176
 177         gate = to_clk_gate(hw);
 178
 179         clk_unregister(clk);
 180         kfree(gate);
 181 }
 182 EXPORT_SYMBOL_GPL(clk_unregister_gate);