2 * Clock implementation for VIA/Wondermedia SoC's
3 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
18 #include <linux/slab.h>
19 #include <linux/bitops.h>
20 #include <linux/clkdev.h>
21 #include <linux/clk-provider.h>
23 /* All clocks share the same lock as none can be changed concurrently */
24 static DEFINE_SPINLOCK(_lock
);
28 void __iomem
*div_reg
;
29 unsigned int div_mask
;
36 * Add new PLL_TYPE_x definitions here as required. Use the first known model
37 * to support the new type as the name.
38 * Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and
39 * vtwm_pll_set_rate() to handle the new PLL_TYPE_x
42 #define PLL_TYPE_VT8500 0
43 #define PLL_TYPE_WM8650 1
44 #define PLL_TYPE_WM8750 2
53 static void __iomem
*pmc_base
;
55 #define to_clk_device(_hw) container_of(_hw, struct clk_device, hw)
57 #define VT8500_PMC_BUSY_MASK 0x18
59 static void vt8500_pmc_wait_busy(void)
61 while (readl(pmc_base
) & VT8500_PMC_BUSY_MASK
)
65 static int vt8500_dclk_enable(struct clk_hw
*hw
)
67 struct clk_device
*cdev
= to_clk_device(hw
);
69 unsigned long flags
= 0;
71 spin_lock_irqsave(cdev
->lock
, flags
);
73 en_val
= readl(cdev
->en_reg
);
74 en_val
|= BIT(cdev
->en_bit
);
75 writel(en_val
, cdev
->en_reg
);
77 spin_unlock_irqrestore(cdev
->lock
, flags
);
81 static void vt8500_dclk_disable(struct clk_hw
*hw
)
83 struct clk_device
*cdev
= to_clk_device(hw
);
85 unsigned long flags
= 0;
87 spin_lock_irqsave(cdev
->lock
, flags
);
89 en_val
= readl(cdev
->en_reg
);
90 en_val
&= ~BIT(cdev
->en_bit
);
91 writel(en_val
, cdev
->en_reg
);
93 spin_unlock_irqrestore(cdev
->lock
, flags
);
96 static int vt8500_dclk_is_enabled(struct clk_hw
*hw
)
98 struct clk_device
*cdev
= to_clk_device(hw
);
99 u32 en_val
= (readl(cdev
->en_reg
) & BIT(cdev
->en_bit
));
101 return en_val
? 1 : 0;
104 static unsigned long vt8500_dclk_recalc_rate(struct clk_hw
*hw
,
105 unsigned long parent_rate
)
107 struct clk_device
*cdev
= to_clk_device(hw
);
108 u32 div
= readl(cdev
->div_reg
) & cdev
->div_mask
;
110 /* Special case for SDMMC devices */
111 if ((cdev
->div_mask
== 0x3F) && (div
& BIT(5)))
112 div
= 64 * (div
& 0x1f);
114 /* div == 0 is actually the highest divisor */
116 div
= (cdev
->div_mask
+ 1);
118 return parent_rate
/ div
;
121 static long vt8500_dclk_round_rate(struct clk_hw
*hw
, unsigned long rate
,
122 unsigned long *prate
)
124 struct clk_device
*cdev
= to_clk_device(hw
);
130 divisor
= *prate
/ rate
;
132 /* If prate / rate would be decimal, incr the divisor */
133 if (rate
* divisor
< *prate
)
137 * If this is a request for SDMMC we have to adjust the divisor
138 * when >31 to use the fixed predivisor
140 if ((cdev
->div_mask
== 0x3F) && (divisor
> 31)) {
141 divisor
= 64 * ((divisor
/ 64) + 1);
144 return *prate
/ divisor
;
147 static int vt8500_dclk_set_rate(struct clk_hw
*hw
, unsigned long rate
,
148 unsigned long parent_rate
)
150 struct clk_device
*cdev
= to_clk_device(hw
);
152 unsigned long flags
= 0;
157 divisor
= parent_rate
/ rate
;
159 /* If prate / rate would be decimal, incr the divisor */
160 if (rate
* divisor
< parent_rate
)
163 if (divisor
== cdev
->div_mask
+ 1)
166 /* SDMMC mask may need to be corrected before testing if its valid */
167 if ((cdev
->div_mask
== 0x3F) && (divisor
> 31)) {
169 * Bit 5 is a fixed /64 predivisor. If the requested divisor
170 * is >31 then correct for the fixed divisor being required.
172 divisor
= 0x20 + (divisor
/ 64);
175 if (divisor
> cdev
->div_mask
) {
176 pr_err("%s: invalid divisor for clock\n", __func__
);
180 spin_lock_irqsave(cdev
->lock
, flags
);
182 vt8500_pmc_wait_busy();
183 writel(divisor
, cdev
->div_reg
);
184 vt8500_pmc_wait_busy();
186 spin_lock_irqsave(cdev
->lock
, flags
);
192 static const struct clk_ops vt8500_gated_clk_ops
= {
193 .enable
= vt8500_dclk_enable
,
194 .disable
= vt8500_dclk_disable
,
195 .is_enabled
= vt8500_dclk_is_enabled
,
198 static const struct clk_ops vt8500_divisor_clk_ops
= {
199 .round_rate
= vt8500_dclk_round_rate
,
200 .set_rate
= vt8500_dclk_set_rate
,
201 .recalc_rate
= vt8500_dclk_recalc_rate
,
204 static const struct clk_ops vt8500_gated_divisor_clk_ops
= {
205 .enable
= vt8500_dclk_enable
,
206 .disable
= vt8500_dclk_disable
,
207 .is_enabled
= vt8500_dclk_is_enabled
,
208 .round_rate
= vt8500_dclk_round_rate
,
209 .set_rate
= vt8500_dclk_set_rate
,
210 .recalc_rate
= vt8500_dclk_recalc_rate
,
213 #define CLK_INIT_GATED BIT(0)
214 #define CLK_INIT_DIVISOR BIT(1)
215 #define CLK_INIT_GATED_DIVISOR (CLK_INIT_DIVISOR | CLK_INIT_GATED)
217 static __init
void vtwm_device_clk_init(struct device_node
*node
)
221 struct clk_device
*dev_clk
;
222 const char *clk_name
= node
->name
;
223 const char *parent_name
;
224 struct clk_init_data init
;
226 int clk_init_flags
= 0;
228 dev_clk
= kzalloc(sizeof(*dev_clk
), GFP_KERNEL
);
229 if (WARN_ON(!dev_clk
))
232 dev_clk
->lock
= &_lock
;
234 rc
= of_property_read_u32(node
, "enable-reg", &en_reg
);
236 dev_clk
->en_reg
= pmc_base
+ en_reg
;
237 rc
= of_property_read_u32(node
, "enable-bit", &dev_clk
->en_bit
);
239 pr_err("%s: enable-bit property required for gated clock\n",
243 clk_init_flags
|= CLK_INIT_GATED
;
246 rc
= of_property_read_u32(node
, "divisor-reg", &div_reg
);
248 dev_clk
->div_reg
= pmc_base
+ div_reg
;
250 * use 0x1f as the default mask since it covers
251 * almost all the clocks and reduces dts properties
253 dev_clk
->div_mask
= 0x1f;
255 of_property_read_u32(node
, "divisor-mask", &dev_clk
->div_mask
);
256 clk_init_flags
|= CLK_INIT_DIVISOR
;
259 of_property_read_string(node
, "clock-output-names", &clk_name
);
261 switch (clk_init_flags
) {
263 init
.ops
= &vt8500_gated_clk_ops
;
265 case CLK_INIT_DIVISOR
:
266 init
.ops
= &vt8500_divisor_clk_ops
;
268 case CLK_INIT_GATED_DIVISOR
:
269 init
.ops
= &vt8500_gated_divisor_clk_ops
;
272 pr_err("%s: Invalid clock description in device tree\n",
278 init
.name
= clk_name
;
280 parent_name
= of_clk_get_parent_name(node
, 0);
281 init
.parent_names
= &parent_name
;
282 init
.num_parents
= 1;
284 dev_clk
->hw
.init
= &init
;
286 clk
= clk_register(NULL
, &dev_clk
->hw
);
287 if (WARN_ON(IS_ERR(clk
))) {
291 rc
= of_clk_add_provider(node
, of_clk_src_simple_get
, clk
);
292 clk_register_clkdev(clk
, clk_name
, NULL
);
294 CLK_OF_DECLARE(vt8500_device
, "via,vt8500-device-clock", vtwm_device_clk_init
);
296 /* PLL clock related functions */
298 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
300 /* Helper macros for PLL_VT8500 */
301 #define VT8500_PLL_MUL(x) ((x & 0x1F) << 1)
302 #define VT8500_PLL_DIV(x) ((x & 0x100) ? 1 : 2)
304 #define VT8500_BITS_TO_FREQ(r, m, d) \
307 #define VT8500_BITS_TO_VAL(m, d) \
308 ((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F))
310 /* Helper macros for PLL_WM8650 */
311 #define WM8650_PLL_MUL(x) (x & 0x3FF)
312 #define WM8650_PLL_DIV(x) (((x >> 10) & 7) * (1 << ((x >> 13) & 3)))
314 #define WM8650_BITS_TO_FREQ(r, m, d1, d2) \
315 (r * m / (d1 * (1 << d2)))
317 #define WM8650_BITS_TO_VAL(m, d1, d2) \
318 ((d2 << 13) | (d1 << 10) | (m & 0x3FF))
320 /* Helper macros for PLL_WM8750 */
321 #define WM8750_PLL_MUL(x) (((x >> 16) & 0xFF) + 1)
322 #define WM8750_PLL_DIV(x) ((((x >> 8) & 1) + 1) * (1 << (x & 7)))
324 #define WM8750_BITS_TO_FREQ(r, m, d1, d2) \
325 (r * (m+1) / ((d1+1) * (1 << d2)))
327 #define WM8750_BITS_TO_VAL(f, m, d1, d2) \
328 ((f << 24) | ((m - 1) << 16) | ((d1 - 1) << 8) | d2)
331 static void vt8500_find_pll_bits(unsigned long rate
, unsigned long parent_rate
,
332 u32
*multiplier
, u32
*prediv
)
337 if ((rate
< parent_rate
* 4) || (rate
> parent_rate
* 62)) {
338 pr_err("%s: requested rate out of range\n", __func__
);
343 if (rate
<= parent_rate
* 31)
344 /* use the prediv to double the resolution */
349 *multiplier
= rate
/ (parent_rate
/ *prediv
);
350 tclk
= (parent_rate
/ *prediv
) * *multiplier
;
353 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__
,
357 static void wm8650_find_pll_bits(unsigned long rate
, unsigned long parent_rate
,
358 u32
*multiplier
, u32
*divisor1
, u32
*divisor2
)
361 u32 best_mul
, best_div1
, best_div2
;
362 unsigned long tclk
, rate_err
, best_err
;
364 best_err
= (unsigned long)-1;
366 /* Find the closest match (lower or equal to requested) */
367 for (div1
= 5; div1
>= 3; div1
--)
368 for (div2
= 3; div2
>= 0; div2
--)
369 for (mul
= 3; mul
<= 1023; mul
++) {
370 tclk
= parent_rate
* mul
/ (div1
* (1 << div2
));
373 /* error will always be +ve */
374 rate_err
= rate
- tclk
;
382 if (rate_err
< best_err
) {
390 /* if we got here, it wasn't an exact match */
391 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__
, rate
,
393 *multiplier
= best_mul
;
394 *divisor1
= best_div1
;
395 *divisor2
= best_div2
;
398 static u32
wm8750_get_filter(u32 parent_rate
, u32 divisor1
)
400 /* calculate frequency (MHz) after pre-divisor */
401 u32 freq
= (parent_rate
/ 1000000) / (divisor1
+ 1);
403 if ((freq
< 10) || (freq
> 200))
404 pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n",
409 else if (freq
>= 104)
425 static void wm8750_find_pll_bits(unsigned long rate
, unsigned long parent_rate
,
426 u32
*filter
, u32
*multiplier
, u32
*divisor1
, u32
*divisor2
)
429 u32 best_mul
, best_div1
, best_div2
;
430 unsigned long tclk
, rate_err
, best_err
;
432 best_err
= (unsigned long)-1;
434 /* Find the closest match (lower or equal to requested) */
435 for (div1
= 1; div1
>= 0; div1
--)
436 for (div2
= 7; div2
>= 0; div2
--)
437 for (mul
= 0; mul
<= 255; mul
++) {
438 tclk
= parent_rate
* (mul
+ 1) / ((div1
+ 1) * (1 << div2
));
441 /* error will always be +ve */
442 rate_err
= rate
- tclk
;
444 *filter
= wm8750_get_filter(parent_rate
, div1
);
451 if (rate_err
< best_err
) {
459 /* if we got here, it wasn't an exact match */
460 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__
, rate
,
463 *filter
= wm8750_get_filter(parent_rate
, best_div1
);
464 *multiplier
= best_mul
;
465 *divisor1
= best_div1
;
466 *divisor2
= best_div2
;
469 static int vtwm_pll_set_rate(struct clk_hw
*hw
, unsigned long rate
,
470 unsigned long parent_rate
)
472 struct clk_pll
*pll
= to_clk_pll(hw
);
473 u32 filter
, mul
, div1
, div2
;
475 unsigned long flags
= 0;
480 case PLL_TYPE_VT8500
:
481 vt8500_find_pll_bits(rate
, parent_rate
, &mul
, &div1
);
482 pll_val
= VT8500_BITS_TO_VAL(mul
, div1
);
484 case PLL_TYPE_WM8650
:
485 wm8650_find_pll_bits(rate
, parent_rate
, &mul
, &div1
, &div2
);
486 pll_val
= WM8650_BITS_TO_VAL(mul
, div1
, div2
);
488 case PLL_TYPE_WM8750
:
489 wm8750_find_pll_bits(rate
, parent_rate
, &filter
, &mul
, &div1
, &div2
);
490 pll_val
= WM8750_BITS_TO_VAL(filter
, mul
, div1
, div2
);
492 pr_err("%s: invalid pll type\n", __func__
);
496 spin_lock_irqsave(pll
->lock
, flags
);
498 vt8500_pmc_wait_busy();
499 writel(pll_val
, pll
->reg
);
500 vt8500_pmc_wait_busy();
502 spin_unlock_irqrestore(pll
->lock
, flags
);
507 static long vtwm_pll_round_rate(struct clk_hw
*hw
, unsigned long rate
,
508 unsigned long *prate
)
510 struct clk_pll
*pll
= to_clk_pll(hw
);
511 u32 filter
, mul
, div1
, div2
;
515 case PLL_TYPE_VT8500
:
516 vt8500_find_pll_bits(rate
, *prate
, &mul
, &div1
);
517 round_rate
= VT8500_BITS_TO_FREQ(*prate
, mul
, div1
);
519 case PLL_TYPE_WM8650
:
520 wm8650_find_pll_bits(rate
, *prate
, &mul
, &div1
, &div2
);
521 round_rate
= WM8650_BITS_TO_FREQ(*prate
, mul
, div1
, div2
);
523 case PLL_TYPE_WM8750
:
524 wm8750_find_pll_bits(rate
, *prate
, &filter
, &mul
, &div1
, &div2
);
525 round_rate
= WM8750_BITS_TO_FREQ(*prate
, mul
, div1
, div2
);
533 static unsigned long vtwm_pll_recalc_rate(struct clk_hw
*hw
,
534 unsigned long parent_rate
)
536 struct clk_pll
*pll
= to_clk_pll(hw
);
537 u32 pll_val
= readl(pll
->reg
);
538 unsigned long pll_freq
;
541 case PLL_TYPE_VT8500
:
542 pll_freq
= parent_rate
* VT8500_PLL_MUL(pll_val
);
543 pll_freq
/= VT8500_PLL_DIV(pll_val
);
545 case PLL_TYPE_WM8650
:
546 pll_freq
= parent_rate
* WM8650_PLL_MUL(pll_val
);
547 pll_freq
/= WM8650_PLL_DIV(pll_val
);
549 case PLL_TYPE_WM8750
:
550 pll_freq
= parent_rate
* WM8750_PLL_MUL(pll_val
);
551 pll_freq
/= WM8750_PLL_DIV(pll_val
);
560 const struct clk_ops vtwm_pll_ops
= {
561 .round_rate
= vtwm_pll_round_rate
,
562 .set_rate
= vtwm_pll_set_rate
,
563 .recalc_rate
= vtwm_pll_recalc_rate
,
566 static __init
void vtwm_pll_clk_init(struct device_node
*node
, int pll_type
)
570 struct clk_pll
*pll_clk
;
571 const char *clk_name
= node
->name
;
572 const char *parent_name
;
573 struct clk_init_data init
;
576 rc
= of_property_read_u32(node
, "reg", ®
);
580 pll_clk
= kzalloc(sizeof(*pll_clk
), GFP_KERNEL
);
581 if (WARN_ON(!pll_clk
))
584 pll_clk
->reg
= pmc_base
+ reg
;
585 pll_clk
->lock
= &_lock
;
586 pll_clk
->type
= pll_type
;
588 of_property_read_string(node
, "clock-output-names", &clk_name
);
590 init
.name
= clk_name
;
591 init
.ops
= &vtwm_pll_ops
;
593 parent_name
= of_clk_get_parent_name(node
, 0);
594 init
.parent_names
= &parent_name
;
595 init
.num_parents
= 1;
597 pll_clk
->hw
.init
= &init
;
599 clk
= clk_register(NULL
, &pll_clk
->hw
);
600 if (WARN_ON(IS_ERR(clk
))) {
604 rc
= of_clk_add_provider(node
, of_clk_src_simple_get
, clk
);
605 clk_register_clkdev(clk
, clk_name
, NULL
);
609 /* Wrappers for initialization functions */
611 static void __init
vt8500_pll_init(struct device_node
*node
)
613 vtwm_pll_clk_init(node
, PLL_TYPE_VT8500
);
615 CLK_OF_DECLARE(vt8500_pll
, "via,vt8500-pll-clock", vt8500_pll_init
);
617 static void __init
wm8650_pll_init(struct device_node
*node
)
619 vtwm_pll_clk_init(node
, PLL_TYPE_WM8650
);
621 CLK_OF_DECLARE(wm8650_pll
, "wm,wm8650-pll-clock", wm8650_pll_init
);
623 static void __init
wm8750_pll_init(struct device_node
*node
)
625 vtwm_pll_clk_init(node
, PLL_TYPE_WM8750
);
627 CLK_OF_DECLARE(wm8750_pll
, "wm,wm8750-pll-clock", wm8750_pll_init
);
629 void __init
vtwm_clk_init(void __iomem
*base
)