2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2012 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/delay.h>
17 #include <linux/slab.h>
18 #include <linux/jiffies.h>
19 #include <linux/err.h>
22 #define PLL_NUM_OFFSET 0x10
23 #define PLL_DENOM_OFFSET 0x20
25 #define BM_PLL_POWER (0x1 << 12)
26 #define BM_PLL_LOCK (0x1 << 31)
29 * struct clk_pllv3 - IMX PLL clock version 3
30 * @clk_hw: clock source
31 * @base: base address of PLL registers
32 * @powerup_set: set POWER bit to power up the PLL
33 * @div_mask: mask of divider bits
34 * @div_shift: shift of divider bits
36 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
37 * is actually a multiplier, and always sits at bit 0.
47 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
49 static int clk_pllv3_wait_lock(struct clk_pllv3
*pll
)
51 unsigned long timeout
= jiffies
+ msecs_to_jiffies(10);
52 u32 val
= readl_relaxed(pll
->base
) & BM_PLL_POWER
;
54 /* No need to wait for lock when pll is not powered up */
55 if ((pll
->powerup_set
&& !val
) || (!pll
->powerup_set
&& val
))
58 /* Wait for PLL to lock */
60 if (readl_relaxed(pll
->base
) & BM_PLL_LOCK
)
62 if (time_after(jiffies
, timeout
))
64 usleep_range(50, 500);
67 return readl_relaxed(pll
->base
) & BM_PLL_LOCK
? 0 : -ETIMEDOUT
;
70 static int clk_pllv3_prepare(struct clk_hw
*hw
)
72 struct clk_pllv3
*pll
= to_clk_pllv3(hw
);
75 val
= readl_relaxed(pll
->base
);
80 writel_relaxed(val
, pll
->base
);
82 return clk_pllv3_wait_lock(pll
);
85 static void clk_pllv3_unprepare(struct clk_hw
*hw
)
87 struct clk_pllv3
*pll
= to_clk_pllv3(hw
);
90 val
= readl_relaxed(pll
->base
);
95 writel_relaxed(val
, pll
->base
);
98 static unsigned long clk_pllv3_recalc_rate(struct clk_hw
*hw
,
99 unsigned long parent_rate
)
101 struct clk_pllv3
*pll
= to_clk_pllv3(hw
);
102 u32 div
= (readl_relaxed(pll
->base
) >> pll
->div_shift
) & pll
->div_mask
;
104 return (div
== 1) ? parent_rate
* 22 : parent_rate
* 20;
107 static long clk_pllv3_round_rate(struct clk_hw
*hw
, unsigned long rate
,
108 unsigned long *prate
)
110 unsigned long parent_rate
= *prate
;
112 return (rate
>= parent_rate
* 22) ? parent_rate
* 22 :
116 static int clk_pllv3_set_rate(struct clk_hw
*hw
, unsigned long rate
,
117 unsigned long parent_rate
)
119 struct clk_pllv3
*pll
= to_clk_pllv3(hw
);
122 if (rate
== parent_rate
* 22)
124 else if (rate
== parent_rate
* 20)
129 val
= readl_relaxed(pll
->base
);
130 val
&= ~(pll
->div_mask
<< pll
->div_shift
);
131 val
|= (div
<< pll
->div_shift
);
132 writel_relaxed(val
, pll
->base
);
134 return clk_pllv3_wait_lock(pll
);
137 static const struct clk_ops clk_pllv3_ops
= {
138 .prepare
= clk_pllv3_prepare
,
139 .unprepare
= clk_pllv3_unprepare
,
140 .recalc_rate
= clk_pllv3_recalc_rate
,
141 .round_rate
= clk_pllv3_round_rate
,
142 .set_rate
= clk_pllv3_set_rate
,
145 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw
*hw
,
146 unsigned long parent_rate
)
148 struct clk_pllv3
*pll
= to_clk_pllv3(hw
);
149 u32 div
= readl_relaxed(pll
->base
) & pll
->div_mask
;
151 return parent_rate
* div
/ 2;
154 static long clk_pllv3_sys_round_rate(struct clk_hw
*hw
, unsigned long rate
,
155 unsigned long *prate
)
157 unsigned long parent_rate
= *prate
;
158 unsigned long min_rate
= parent_rate
* 54 / 2;
159 unsigned long max_rate
= parent_rate
* 108 / 2;
164 else if (rate
< min_rate
)
166 div
= rate
* 2 / parent_rate
;
168 return parent_rate
* div
/ 2;
171 static int clk_pllv3_sys_set_rate(struct clk_hw
*hw
, unsigned long rate
,
172 unsigned long parent_rate
)
174 struct clk_pllv3
*pll
= to_clk_pllv3(hw
);
175 unsigned long min_rate
= parent_rate
* 54 / 2;
176 unsigned long max_rate
= parent_rate
* 108 / 2;
179 if (rate
< min_rate
|| rate
> max_rate
)
182 div
= rate
* 2 / parent_rate
;
183 val
= readl_relaxed(pll
->base
);
184 val
&= ~pll
->div_mask
;
186 writel_relaxed(val
, pll
->base
);
188 return clk_pllv3_wait_lock(pll
);
191 static const struct clk_ops clk_pllv3_sys_ops
= {
192 .prepare
= clk_pllv3_prepare
,
193 .unprepare
= clk_pllv3_unprepare
,
194 .recalc_rate
= clk_pllv3_sys_recalc_rate
,
195 .round_rate
= clk_pllv3_sys_round_rate
,
196 .set_rate
= clk_pllv3_sys_set_rate
,
199 static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw
*hw
,
200 unsigned long parent_rate
)
202 struct clk_pllv3
*pll
= to_clk_pllv3(hw
);
203 u32 mfn
= readl_relaxed(pll
->base
+ PLL_NUM_OFFSET
);
204 u32 mfd
= readl_relaxed(pll
->base
+ PLL_DENOM_OFFSET
);
205 u32 div
= readl_relaxed(pll
->base
) & pll
->div_mask
;
207 return (parent_rate
* div
) + ((parent_rate
/ mfd
) * mfn
);
210 static long clk_pllv3_av_round_rate(struct clk_hw
*hw
, unsigned long rate
,
211 unsigned long *prate
)
213 unsigned long parent_rate
= *prate
;
214 unsigned long min_rate
= parent_rate
* 27;
215 unsigned long max_rate
= parent_rate
* 54;
217 u32 mfn
, mfd
= 1000000;
222 else if (rate
< min_rate
)
225 div
= rate
/ parent_rate
;
226 temp64
= (u64
) (rate
- div
* parent_rate
);
228 do_div(temp64
, parent_rate
);
231 return parent_rate
* div
+ parent_rate
/ mfd
* mfn
;
234 static int clk_pllv3_av_set_rate(struct clk_hw
*hw
, unsigned long rate
,
235 unsigned long parent_rate
)
237 struct clk_pllv3
*pll
= to_clk_pllv3(hw
);
238 unsigned long min_rate
= parent_rate
* 27;
239 unsigned long max_rate
= parent_rate
* 54;
241 u32 mfn
, mfd
= 1000000;
244 if (rate
< min_rate
|| rate
> max_rate
)
247 div
= rate
/ parent_rate
;
248 temp64
= (u64
) (rate
- div
* parent_rate
);
250 do_div(temp64
, parent_rate
);
253 val
= readl_relaxed(pll
->base
);
254 val
&= ~pll
->div_mask
;
256 writel_relaxed(val
, pll
->base
);
257 writel_relaxed(mfn
, pll
->base
+ PLL_NUM_OFFSET
);
258 writel_relaxed(mfd
, pll
->base
+ PLL_DENOM_OFFSET
);
260 return clk_pllv3_wait_lock(pll
);
263 static const struct clk_ops clk_pllv3_av_ops
= {
264 .prepare
= clk_pllv3_prepare
,
265 .unprepare
= clk_pllv3_unprepare
,
266 .recalc_rate
= clk_pllv3_av_recalc_rate
,
267 .round_rate
= clk_pllv3_av_round_rate
,
268 .set_rate
= clk_pllv3_av_set_rate
,
271 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw
*hw
,
272 unsigned long parent_rate
)
277 static const struct clk_ops clk_pllv3_enet_ops
= {
278 .prepare
= clk_pllv3_prepare
,
279 .unprepare
= clk_pllv3_unprepare
,
280 .recalc_rate
= clk_pllv3_enet_recalc_rate
,
283 struct clk
*imx_clk_pllv3(enum imx_pllv3_type type
, const char *name
,
284 const char *parent_name
, void __iomem
*base
,
287 struct clk_pllv3
*pll
;
288 const struct clk_ops
*ops
;
290 struct clk_init_data init
;
292 pll
= kzalloc(sizeof(*pll
), GFP_KERNEL
);
294 return ERR_PTR(-ENOMEM
);
298 ops
= &clk_pllv3_sys_ops
;
300 case IMX_PLLV3_USB_VF610
:
303 ops
= &clk_pllv3_ops
;
304 pll
->powerup_set
= true;
307 ops
= &clk_pllv3_av_ops
;
310 ops
= &clk_pllv3_enet_ops
;
313 ops
= &clk_pllv3_ops
;
316 pll
->div_mask
= div_mask
;
321 init
.parent_names
= &parent_name
;
322 init
.num_parents
= 1;
324 pll
->hw
.init
= &init
;
326 clk
= clk_register(NULL
, &pll
->hw
);