drivers/clk/meson/meson8b-clkc.c

   1 /*
   2  * Copyright (c) 2015 Endless Mobile, Inc.
   3  * Author: Carlo Caione <carlo@endlessm.com>
   4  *
   5  * Copyright (c) 2016 BayLibre, Inc.
   6  * Michael Turquette <mturquette@baylibre.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <linux/clk.h>
  22 #include <linux/clk-provider.h>
  23 #include <linux/of_address.h>
  24 #include <dt-bindings/clock/meson8b-clkc.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/module.h>
  27
  28 #include "clkc.h"
  29
  30 /*
  31  * Clock controller register offsets
  32  *
  33  * Register offsets from the HardKernel[0] data sheet are listed in comment
  34  * blocks below. Those offsets must be multiplied by 4 before adding them to
  35  * the base address to get the right value
  36  *
  37  * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
  38  */
  39 #define MESON8B_REG_SYS_CPU_CNTL1       0x015c /* 0x57 offset in data sheet */
  40 #define MESON8B_REG_HHI_MPEG            0x0174 /* 0x5d offset in data sheet */
  41 #define MESON8B_REG_MALI                0x01b0 /* 0x6c offset in data sheet */
  42 #define MESON8B_REG_PLL_FIXED           0x0280
  43 #define MESON8B_REG_PLL_SYS             0x0300
  44 #define MESON8B_REG_PLL_VID             0x0320
  45
  46 static DEFINE_SPINLOCK(clk_lock);
  47
  48 static const struct pll_rate_table sys_pll_rate_table[] = {
  49         PLL_RATE(312000000, 52, 1, 2),
  50         PLL_RATE(336000000, 56, 1, 2),
  51         PLL_RATE(360000000, 60, 1, 2),
  52         PLL_RATE(384000000, 64, 1, 2),
  53         PLL_RATE(408000000, 68, 1, 2),
  54         PLL_RATE(432000000, 72, 1, 2),
  55         PLL_RATE(456000000, 76, 1, 2),
  56         PLL_RATE(480000000, 80, 1, 2),
  57         PLL_RATE(504000000, 84, 1, 2),
  58         PLL_RATE(528000000, 88, 1, 2),
  59         PLL_RATE(552000000, 92, 1, 2),
  60         PLL_RATE(576000000, 96, 1, 2),
  61         PLL_RATE(600000000, 50, 1, 1),
  62         PLL_RATE(624000000, 52, 1, 1),
  63         PLL_RATE(648000000, 54, 1, 1),
  64         PLL_RATE(672000000, 56, 1, 1),
  65         PLL_RATE(696000000, 58, 1, 1),
  66         PLL_RATE(720000000, 60, 1, 1),
  67         PLL_RATE(744000000, 62, 1, 1),
  68         PLL_RATE(768000000, 64, 1, 1),
  69         PLL_RATE(792000000, 66, 1, 1),
  70         PLL_RATE(816000000, 68, 1, 1),
  71         PLL_RATE(840000000, 70, 1, 1),
  72         PLL_RATE(864000000, 72, 1, 1),
  73         PLL_RATE(888000000, 74, 1, 1),
  74         PLL_RATE(912000000, 76, 1, 1),
  75         PLL_RATE(936000000, 78, 1, 1),
  76         PLL_RATE(960000000, 80, 1, 1),
  77         PLL_RATE(984000000, 82, 1, 1),
  78         PLL_RATE(1008000000, 84, 1, 1),
  79         PLL_RATE(1032000000, 86, 1, 1),
  80         PLL_RATE(1056000000, 88, 1, 1),
  81         PLL_RATE(1080000000, 90, 1, 1),
  82         PLL_RATE(1104000000, 92, 1, 1),
  83         PLL_RATE(1128000000, 94, 1, 1),
  84         PLL_RATE(1152000000, 96, 1, 1),
  85         PLL_RATE(1176000000, 98, 1, 1),
  86         PLL_RATE(1200000000, 50, 1, 0),
  87         PLL_RATE(1224000000, 51, 1, 0),
  88         PLL_RATE(1248000000, 52, 1, 0),
  89         PLL_RATE(1272000000, 53, 1, 0),
  90         PLL_RATE(1296000000, 54, 1, 0),
  91         PLL_RATE(1320000000, 55, 1, 0),
  92         PLL_RATE(1344000000, 56, 1, 0),
  93         PLL_RATE(1368000000, 57, 1, 0),
  94         PLL_RATE(1392000000, 58, 1, 0),
  95         PLL_RATE(1416000000, 59, 1, 0),
  96         PLL_RATE(1440000000, 60, 1, 0),
  97         PLL_RATE(1464000000, 61, 1, 0),
  98         PLL_RATE(1488000000, 62, 1, 0),
  99         PLL_RATE(1512000000, 63, 1, 0),
 100         PLL_RATE(1536000000, 64, 1, 0),
 101         { /* sentinel */ },
 102 };
 103
 104 static const struct clk_div_table cpu_div_table[] = {
 105         { .val = 1, .div = 1 },
 106         { .val = 2, .div = 2 },
 107         { .val = 3, .div = 3 },
 108         { .val = 2, .div = 4 },
 109         { .val = 3, .div = 6 },
 110         { .val = 4, .div = 8 },
 111         { .val = 5, .div = 10 },
 112         { .val = 6, .div = 12 },
 113         { .val = 7, .div = 14 },
 114         { .val = 8, .div = 16 },
 115         { /* sentinel */ },
 116 };
 117
 118 static struct clk_fixed_rate meson8b_xtal = {
 119         .fixed_rate = 24000000,
 120         .hw.init = &(struct clk_init_data){
 121                 .name = "xtal",
 122                 .num_parents = 0,
 123                 .ops = &clk_fixed_rate_ops,
 124         },
 125 };
 126
 127 static struct meson_clk_pll meson8b_fixed_pll = {
 128         .m = {
 129                 .reg_off = MESON8B_REG_PLL_FIXED,
 130                 .shift   = 0,
 131                 .width   = 9,
 132         },
 133         .n = {
 134                 .reg_off = MESON8B_REG_PLL_FIXED,
 135                 .shift   = 9,
 136                 .width   = 5,
 137         },
 138         .od = {
 139                 .reg_off = MESON8B_REG_PLL_FIXED,
 140                 .shift   = 16,
 141                 .width   = 2,
 142         },
 143         .lock = &clk_lock,
 144         .hw.init = &(struct clk_init_data){
 145                 .name = "fixed_pll",
 146                 .ops = &meson_clk_pll_ro_ops,
 147                 .parent_names = (const char *[]){ "xtal" },
 148                 .num_parents = 1,
 149                 .flags = CLK_GET_RATE_NOCACHE,
 150         },
 151 };
 152
 153 static struct meson_clk_pll meson8b_vid_pll = {
 154         .m = {
 155                 .reg_off = MESON8B_REG_PLL_VID,
 156                 .shift   = 0,
 157                 .width   = 9,
 158         },
 159         .n = {
 160                 .reg_off = MESON8B_REG_PLL_VID,
 161                 .shift   = 9,
 162                 .width   = 5,
 163         },
 164         .od = {
 165                 .reg_off = MESON8B_REG_PLL_VID,
 166                 .shift   = 16,
 167                 .width   = 2,
 168         },
 169         .lock = &clk_lock,
 170         .hw.init = &(struct clk_init_data){
 171                 .name = "vid_pll",
 172                 .ops = &meson_clk_pll_ro_ops,
 173                 .parent_names = (const char *[]){ "xtal" },
 174                 .num_parents = 1,
 175                 .flags = CLK_GET_RATE_NOCACHE,
 176         },
 177 };
 178
 179 static struct meson_clk_pll meson8b_sys_pll = {
 180         .m = {
 181                 .reg_off = MESON8B_REG_PLL_SYS,
 182                 .shift   = 0,
 183                 .width   = 9,
 184         },
 185         .n = {
 186                 .reg_off = MESON8B_REG_PLL_SYS,
 187                 .shift   = 9,
 188                 .width   = 5,
 189         },
 190         .od = {
 191                 .reg_off = MESON8B_REG_PLL_SYS,
 192                 .shift   = 16,
 193                 .width   = 2,
 194         },
 195         .rate_table = sys_pll_rate_table,
 196         .rate_count = ARRAY_SIZE(sys_pll_rate_table),
 197         .lock = &clk_lock,
 198         .hw.init = &(struct clk_init_data){
 199                 .name = "sys_pll",
 200                 .ops = &meson_clk_pll_ops,
 201                 .parent_names = (const char *[]){ "xtal" },
 202                 .num_parents = 1,
 203                 .flags = CLK_GET_RATE_NOCACHE,
 204         },
 205 };
 206
 207 static struct clk_fixed_factor meson8b_fclk_div2 = {
 208         .mult = 1,
 209         .div = 2,
 210         .hw.init = &(struct clk_init_data){
 211                 .name = "fclk_div2",
 212                 .ops = &clk_fixed_factor_ops,
 213                 .parent_names = (const char *[]){ "fixed_pll" },
 214                 .num_parents = 1,
 215         },
 216 };
 217
 218 static struct clk_fixed_factor meson8b_fclk_div3 = {
 219         .mult = 1,
 220         .div = 3,
 221         .hw.init = &(struct clk_init_data){
 222                 .name = "fclk_div3",
 223                 .ops = &clk_fixed_factor_ops,
 224                 .parent_names = (const char *[]){ "fixed_pll" },
 225                 .num_parents = 1,
 226         },
 227 };
 228
 229 static struct clk_fixed_factor meson8b_fclk_div4 = {
 230         .mult = 1,
 231         .div = 4,
 232         .hw.init = &(struct clk_init_data){
 233                 .name = "fclk_div4",
 234                 .ops = &clk_fixed_factor_ops,
 235                 .parent_names = (const char *[]){ "fixed_pll" },
 236                 .num_parents = 1,
 237         },
 238 };
 239
 240 static struct clk_fixed_factor meson8b_fclk_div5 = {
 241         .mult = 1,
 242         .div = 5,
 243         .hw.init = &(struct clk_init_data){
 244                 .name = "fclk_div5",
 245                 .ops = &clk_fixed_factor_ops,
 246                 .parent_names = (const char *[]){ "fixed_pll" },
 247                 .num_parents = 1,
 248         },
 249 };
 250
 251 static struct clk_fixed_factor meson8b_fclk_div7 = {
 252         .mult = 1,
 253         .div = 7,
 254         .hw.init = &(struct clk_init_data){
 255                 .name = "fclk_div7",
 256                 .ops = &clk_fixed_factor_ops,
 257                 .parent_names = (const char *[]){ "fixed_pll" },
 258                 .num_parents = 1,
 259         },
 260 };
 261
 262 /*
 263  * FIXME cpu clocks and the legacy composite clocks (e.g. clk81) are both PLL
 264  * post-dividers and should be modeled with their respective PLLs via the
 265  * forthcoming coordinated clock rates feature
 266  */
 267 static struct meson_clk_cpu meson8b_cpu_clk = {
 268         .reg_off = MESON8B_REG_SYS_CPU_CNTL1,
 269         .div_table = cpu_div_table,
 270         .clk_nb.notifier_call = meson_clk_cpu_notifier_cb,
 271         .hw.init = &(struct clk_init_data){
 272                 .name = "cpu_clk",
 273                 .ops = &meson_clk_cpu_ops,
 274                 .parent_names = (const char *[]){ "sys_pll" },
 275                 .num_parents = 1,
 276         },
 277 };
 278
 279 static u32 mux_table_clk81[]    = { 6, 5, 7 };
 280
 281 struct clk_mux meson8b_mpeg_clk_sel = {
 282         .reg = (void *)MESON8B_REG_HHI_MPEG,
 283         .mask = 0x7,
 284         .shift = 12,
 285         .flags = CLK_MUX_READ_ONLY,
 286         .table = mux_table_clk81,
 287         .lock = &clk_lock,
 288         .hw.init = &(struct clk_init_data){
 289                 .name = "mpeg_clk_sel",
 290                 .ops = &clk_mux_ro_ops,
 291                 /*
 292                  * FIXME bits 14:12 selects from 8 possible parents:
 293                  * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
 294                  * fclk_div4, fclk_div3, fclk_div5
 295                  */
 296                 .parent_names = (const char *[]){ "fclk_div3", "fclk_div4",
 297                         "fclk_div5" },
 298                 .num_parents = 3,
 299                 .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
 300         },
 301 };
 302
 303 struct clk_divider meson8b_mpeg_clk_div = {
 304         .reg = (void *)MESON8B_REG_HHI_MPEG,
 305         .shift = 0,
 306         .width = 7,
 307         .lock = &clk_lock,
 308         .hw.init = &(struct clk_init_data){
 309                 .name = "mpeg_clk_div",
 310                 .ops = &clk_divider_ops,
 311                 .parent_names = (const char *[]){ "mpeg_clk_sel" },
 312                 .num_parents = 1,
 313                 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
 314         },
 315 };
 316
 317 struct clk_gate meson8b_clk81 = {
 318         .reg = (void *)MESON8B_REG_HHI_MPEG,
 319         .bit_idx = 7,
 320         .lock = &clk_lock,
 321         .hw.init = &(struct clk_init_data){
 322                 .name = "clk81",
 323                 .ops = &clk_gate_ops,
 324                 .parent_names = (const char *[]){ "mpeg_clk_div" },
 325                 .num_parents = 1,
 326                 .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
 327         },
 328 };
 329
 330 static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
 331         .hws = {
 332                 [CLKID_XTAL] = &meson8b_xtal.hw,
 333                 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
 334                 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
 335                 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
 336                 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
 337                 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
 338                 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
 339                 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
 340                 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
 341                 [CLKID_CPUCLK] = &meson8b_cpu_clk.hw,
 342                 [CLKID_MPEG_SEL] = &meson8b_mpeg_clk_sel.hw,
 343                 [CLKID_MPEG_DIV] = &meson8b_mpeg_clk_div.hw,
 344                 [CLKID_CLK81] = &meson8b_clk81.hw,
 345         },
 346         .num = CLK_NR_CLKS,
 347 };
 348
 349 static struct meson_clk_pll *const meson8b_clk_plls[] = {
 350         &meson8b_fixed_pll,
 351         &meson8b_vid_pll,
 352         &meson8b_sys_pll,
 353 };
 354
 355 static int meson8b_clkc_probe(struct platform_device *pdev)
 356 {
 357         void __iomem *clk_base;
 358         int ret, clkid, i;
 359         struct clk_hw *parent_hw;
 360         struct clk *parent_clk;
 361         struct device *dev = &pdev->dev;
 362
 363         /*  Generic clocks and PLLs */
 364         clk_base = of_iomap(dev->of_node, 1);
 365         if (!clk_base) {
 366                 pr_err("%s: Unable to map clk base\n", __func__);
 367                 return -ENXIO;
 368         }
 369
 370         /* Populate base address for PLLs */
 371         for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++)
 372                 meson8b_clk_plls[i]->base = clk_base;
 373
 374         /* Populate the base address for CPU clk */
 375         meson8b_cpu_clk.base = clk_base;
 376
 377         /* Populate the base address for the MPEG clks */
 378         meson8b_mpeg_clk_sel.reg = clk_base + (u32)meson8b_mpeg_clk_sel.reg;
 379         meson8b_mpeg_clk_div.reg = clk_base + (u32)meson8b_mpeg_clk_div.reg;
 380         meson8b_clk81.reg = clk_base + (u32)meson8b_clk81.reg;
 381
 382         /*
 383          * register all clks
 384          * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
 385          */
 386         for (clkid = CLKID_XTAL; clkid < CLK_NR_CLKS; clkid++) {
 387                 /* array might be sparse */
 388                 if (!meson8b_hw_onecell_data.hws[clkid])
 389                         continue;
 390
 391                 /* FIXME convert to devm_clk_register */
 392                 ret = devm_clk_hw_register(dev, meson8b_hw_onecell_data.hws[clkid]);
 393                 if (ret)
 394                         goto iounmap;
 395         }
 396
 397         /*
 398          * Register CPU clk notifier
 399          *
 400          * FIXME this is wrong for a lot of reasons. First, the muxes should be
 401          * struct clk_hw objects. Second, we shouldn't program the muxes in
 402          * notifier handlers. The tricky programming sequence will be handled
 403          * by the forthcoming coordinated clock rates mechanism once that
 404          * feature is released.
 405          *
 406          * Furthermore, looking up the parent this way is terrible. At some
 407          * point we will stop allocating a default struct clk when registering
 408          * a new clk_hw, and this hack will no longer work. Releasing the ccr
 409          * feature before that time solves the problem :-)
 410          */
 411         parent_hw = clk_hw_get_parent(&meson8b_cpu_clk.hw);
 412         parent_clk = parent_hw->clk;
 413         ret = clk_notifier_register(parent_clk, &meson8b_cpu_clk.clk_nb);
 414         if (ret) {
 415                 pr_err("%s: failed to register clock notifier for cpu_clk\n",
 416                                 __func__);
 417                 goto iounmap;
 418         }
 419
 420         return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
 421                         &meson8b_hw_onecell_data);
 422
 423 iounmap:
 424         iounmap(clk_base);
 425         return ret;
 426 }
 427
 428 static const struct of_device_id meson8b_clkc_match_table[] = {
 429         { .compatible = "amlogic,meson8b-clkc" },
 430         { }
 431 };
 432 MODULE_DEVICE_TABLE(of, meson8b_match_table);
 433
 434 static struct platform_driver meson8b_driver = {
 435         .probe          = meson8b_clkc_probe,
 436         .driver         = {
 437                 .name   = "meson8b-clkc",
 438                 .of_match_table = meson8b_clkc_match_table,
 439         },
 440 };
 441
 442 static int __init meson8b_clkc_init(void)
 443 {
 444         return platform_driver_register(&meson8b_driver);
 445 }
 446 module_init(meson8b_clkc_init);
 447
 448 static void __exit meson8b_clkc_exit(void)
 449 {
 450         platform_driver_unregister(&meson8b_driver);
 451 }
 452 module_exit(meson8b_clkc_exit);
 453
 454 MODULE_DESCRIPTION("AmLogic S805 / Meson8b Clock Controller Driver");
 455 MODULE_LICENSE("GPL v2");
 456 MODULE_ALIAS("platform:meson8b-clkc");
 457 MODULE_AUTHOR("Michael Turquette <mturquette@baylibre.com>");
 458 MODULE_AUTHOR("Carlo Caione <carlo@endlessm.com>");