drivers/clk/rockchip/clk-pll.c

   1 /*
   2  * Copyright (c) 2014 MundoReader S.L.
   3  * Author: Heiko Stuebner <heiko@sntech.de>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <asm/div64.h>
  17 #include <linux/slab.h>
  18 #include <linux/io.h>
  19 #include <linux/delay.h>
  20 #include <linux/clk.h>
  21 #include <linux/clk-provider.h>
  22 #include <linux/regmap.h>
  23 #include "clk.h"
  24
  25 #define PLL_MODE_MASK           0x3
  26 #define PLL_MODE_SLOW           0x0
  27 #define PLL_MODE_NORM           0x1
  28 #define PLL_MODE_DEEP           0x2
  29
  30 struct rockchip_clk_pll {
  31         struct clk_hw           hw;
  32
  33         struct clk_mux          pll_mux;
  34         const struct clk_ops    *pll_mux_ops;
  35
  36         struct notifier_block   clk_nb;
  37
  38         void __iomem            *reg_base;
  39         int                     lock_offset;
  40         unsigned int            lock_shift;
  41         enum rockchip_pll_type  type;
  42         u8                      flags;
  43         const struct rockchip_pll_rate_table *rate_table;
  44         unsigned int            rate_count;
  45         spinlock_t              *lock;
  46 };
  47
  48 #define to_rockchip_clk_pll(_hw) container_of(_hw, struct rockchip_clk_pll, hw)
  49 #define to_rockchip_clk_pll_nb(nb) \
  50                         container_of(nb, struct rockchip_clk_pll, clk_nb)
  51
  52 static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
  53                             struct rockchip_clk_pll *pll, unsigned long rate)
  54 {
  55         const struct rockchip_pll_rate_table  *rate_table = pll->rate_table;
  56         int i;
  57
  58         for (i = 0; i < pll->rate_count; i++) {
  59                 if (rate == rate_table[i].rate)
  60                         return &rate_table[i];
  61         }
  62
  63         return NULL;
  64 }
  65
  66 static long rockchip_pll_round_rate(struct clk_hw *hw,
  67                             unsigned long drate, unsigned long *prate)
  68 {
  69         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
  70         const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
  71         int i;
  72
  73         /* Assumming rate_table is in descending order */
  74         for (i = 0; i < pll->rate_count; i++) {
  75                 if (drate >= rate_table[i].rate)
  76                         return rate_table[i].rate;
  77         }
  78
  79         /* return minimum supported value */
  80         return rate_table[i - 1].rate;
  81 }
  82
  83 /*
  84  * Wait for the pll to reach the locked state.
  85  * The calling set_rate function is responsible for making sure the
  86  * grf regmap is available.
  87  */
  88 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
  89 {
  90         struct regmap *grf = rockchip_clk_get_grf();
  91         unsigned int val;
  92         int delay = 24000000, ret;
  93
  94         while (delay > 0) {
  95                 ret = regmap_read(grf, pll->lock_offset, &val);
  96                 if (ret) {
  97                         pr_err("%s: failed to read pll lock status: %d\n",
  98                                __func__, ret);
  99                         return ret;
 100                 }
 101
 102                 if (val & BIT(pll->lock_shift))
 103                         return 0;
 104                 delay--;
 105         }
 106
 107         pr_err("%s: timeout waiting for pll to lock\n", __func__);
 108         return -ETIMEDOUT;
 109 }
 110
 111 /**
 112  * PLL used in RK3066, RK3188 and RK3288
 113  */
 114
 115 #define RK3066_PLL_RESET_DELAY(nr)      ((nr * 500) / 24 + 1)
 116
 117 #define RK3066_PLLCON(i)                (i * 0x4)
 118 #define RK3066_PLLCON0_OD_MASK          0xf
 119 #define RK3066_PLLCON0_OD_SHIFT         0
 120 #define RK3066_PLLCON0_NR_MASK          0x3f
 121 #define RK3066_PLLCON0_NR_SHIFT         8
 122 #define RK3066_PLLCON1_NF_MASK          0x1fff
 123 #define RK3066_PLLCON1_NF_SHIFT         0
 124 #define RK3066_PLLCON2_BWADJ_MASK       0xfff
 125 #define RK3066_PLLCON2_BWADJ_SHIFT      0
 126 #define RK3066_PLLCON3_RESET            (1 << 5)
 127 #define RK3066_PLLCON3_PWRDOWN          (1 << 1)
 128 #define RK3066_PLLCON3_BYPASS           (1 << 0)
 129
 130 static unsigned long rockchip_rk3066_pll_recalc_rate(struct clk_hw *hw,
 131                                                      unsigned long prate)
 132 {
 133         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 134         u64 nf, nr, no, rate64 = prate;
 135         u32 pllcon;
 136
 137         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));
 138         if (pllcon & RK3066_PLLCON3_BYPASS) {
 139                 pr_debug("%s: pll %s is bypassed\n", __func__,
 140                         __clk_get_name(hw->clk));
 141                 return prate;
 142         }
 143
 144         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));
 145         nf = (pllcon >> RK3066_PLLCON1_NF_SHIFT) & RK3066_PLLCON1_NF_MASK;
 146
 147         pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));
 148         nr = (pllcon >> RK3066_PLLCON0_NR_SHIFT) & RK3066_PLLCON0_NR_MASK;
 149         no = (pllcon >> RK3066_PLLCON0_OD_SHIFT) & RK3066_PLLCON0_OD_MASK;
 150
 151         rate64 *= (nf + 1);
 152         do_div(rate64, nr + 1);
 153         do_div(rate64, no + 1);
 154
 155         return (unsigned long)rate64;
 156 }
 157
 158 static int rockchip_rk3066_pll_set_rate(struct clk_hw *hw, unsigned long drate,
 159                                         unsigned long prate)
 160 {
 161         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 162         const struct rockchip_pll_rate_table *rate;
 163         unsigned long old_rate = rockchip_rk3066_pll_recalc_rate(hw, prate);
 164         struct regmap *grf = rockchip_clk_get_grf();
 165         struct clk_mux *pll_mux = &pll->pll_mux;
 166         const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
 167         int rate_change_remuxed = 0;
 168         int cur_parent;
 169         int ret;
 170
 171         if (IS_ERR(grf)) {
 172                 pr_debug("%s: grf regmap not available, aborting rate change\n",
 173                          __func__);
 174                 return PTR_ERR(grf);
 175         }
 176
 177         pr_debug("%s: changing %s from %lu to %lu with a parent rate of %lu\n",
 178                  __func__, __clk_get_name(hw->clk), old_rate, drate, prate);
 179
 180         /* Get required rate settings from table */
 181         rate = rockchip_get_pll_settings(pll, drate);
 182         if (!rate) {
 183                 pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
 184                         drate, __clk_get_name(hw->clk));
 185                 return -EINVAL;
 186         }
 187
 188         pr_debug("%s: rate settings for %lu (nr, no, nf): (%d, %d, %d)\n",
 189                  __func__, rate->rate, rate->nr, rate->no, rate->nf);
 190
 191         cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
 192         if (cur_parent == PLL_MODE_NORM) {
 193                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
 194                 rate_change_remuxed = 1;
 195         }
 196
 197         /* enter reset mode */
 198         writel(HIWORD_UPDATE(RK3066_PLLCON3_RESET, RK3066_PLLCON3_RESET, 0),
 199                pll->reg_base + RK3066_PLLCON(3));
 200
 201         /* update pll values */
 202         writel(HIWORD_UPDATE(rate->nr - 1, RK3066_PLLCON0_NR_MASK,
 203                                            RK3066_PLLCON0_NR_SHIFT) |
 204                HIWORD_UPDATE(rate->no - 1, RK3066_PLLCON0_OD_MASK,
 205                                            RK3066_PLLCON0_OD_SHIFT),
 206                pll->reg_base + RK3066_PLLCON(0));
 207
 208         writel_relaxed(HIWORD_UPDATE(rate->nf - 1, RK3066_PLLCON1_NF_MASK,
 209                                                    RK3066_PLLCON1_NF_SHIFT),
 210                        pll->reg_base + RK3066_PLLCON(1));
 211         writel_relaxed(HIWORD_UPDATE(rate->bwadj, RK3066_PLLCON2_BWADJ_MASK,
 212                                                   RK3066_PLLCON2_BWADJ_SHIFT),
 213                        pll->reg_base + RK3066_PLLCON(2));
 214
 215         /* leave reset and wait the reset_delay */
 216         writel(HIWORD_UPDATE(0, RK3066_PLLCON3_RESET, 0),
 217                pll->reg_base + RK3066_PLLCON(3));
 218         udelay(RK3066_PLL_RESET_DELAY(rate->nr));
 219
 220         /* wait for the pll to lock */
 221         ret = rockchip_pll_wait_lock(pll);
 222         if (ret) {
 223                 pr_warn("%s: pll did not lock, trying to restore old rate %lu\n",
 224                         __func__, old_rate);
 225                 rockchip_rk3066_pll_set_rate(hw, old_rate, prate);
 226         }
 227
 228         if (rate_change_remuxed)
 229                 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 230
 231         return ret;
 232 }
 233
 234 static int rockchip_rk3066_pll_enable(struct clk_hw *hw)
 235 {
 236         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 237
 238         writel(HIWORD_UPDATE(0, RK3066_PLLCON3_PWRDOWN, 0),
 239                pll->reg_base + RK3066_PLLCON(3));
 240
 241         return 0;
 242 }
 243
 244 static void rockchip_rk3066_pll_disable(struct clk_hw *hw)
 245 {
 246         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 247
 248         writel(HIWORD_UPDATE(RK3066_PLLCON3_PWRDOWN,
 249                              RK3066_PLLCON3_PWRDOWN, 0),
 250                pll->reg_base + RK3066_PLLCON(3));
 251 }
 252
 253 static int rockchip_rk3066_pll_is_enabled(struct clk_hw *hw)
 254 {
 255         struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
 256         u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));
 257
 258         return !(pllcon & RK3066_PLLCON3_PWRDOWN);
 259 }
 260
 261 static const struct clk_ops rockchip_rk3066_pll_clk_norate_ops = {
 262         .recalc_rate = rockchip_rk3066_pll_recalc_rate,
 263         .enable = rockchip_rk3066_pll_enable,
 264         .disable = rockchip_rk3066_pll_disable,
 265         .is_enabled = rockchip_rk3066_pll_is_enabled,
 266 };
 267
 268 static const struct clk_ops rockchip_rk3066_pll_clk_ops = {
 269         .recalc_rate = rockchip_rk3066_pll_recalc_rate,
 270         .round_rate = rockchip_pll_round_rate,
 271         .set_rate = rockchip_rk3066_pll_set_rate,
 272         .enable = rockchip_rk3066_pll_enable,
 273         .disable = rockchip_rk3066_pll_disable,
 274         .is_enabled = rockchip_rk3066_pll_is_enabled,
 275 };
 276
 277 /*
 278  * Common registering of pll clocks
 279  */
 280
 281 struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type,
 282                 const char *name, const char **parent_names, u8 num_parents,
 283                 void __iomem *base, int con_offset, int grf_lock_offset,
 284                 int lock_shift, int mode_offset, int mode_shift,
 285                 struct rockchip_pll_rate_table *rate_table,
 286                 u8 clk_pll_flags, spinlock_t *lock)
 287 {
 288         const char *pll_parents[3];
 289         struct clk_init_data init;
 290         struct rockchip_clk_pll *pll;
 291         struct clk_mux *pll_mux;
 292         struct clk *pll_clk, *mux_clk;
 293         char pll_name[20];
 294
 295         if (num_parents != 2) {
 296                 pr_err("%s: needs two parent clocks\n", __func__);
 297                 return ERR_PTR(-EINVAL);
 298         }
 299
 300         /* name the actual pll */
 301         snprintf(pll_name, sizeof(pll_name), "pll_%s", name);
 302
 303         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
 304         if (!pll)
 305                 return ERR_PTR(-ENOMEM);
 306
 307         init.name = pll_name;
 308
 309         /* keep all plls untouched for now */
 310         init.flags = CLK_IGNORE_UNUSED;
 311
 312         init.parent_names = &parent_names[0];
 313         init.num_parents = 1;
 314
 315         if (rate_table) {
 316                 int len;
 317
 318                 /* find count of rates in rate_table */
 319                 for (len = 0; rate_table[len].rate != 0; )
 320                         len++;
 321
 322                 pll->rate_count = len;
 323                 pll->rate_table = kmemdup(rate_table,
 324                                         pll->rate_count *
 325                                         sizeof(struct rockchip_pll_rate_table),
 326                                         GFP_KERNEL);
 327                 WARN(!pll->rate_table,
 328                         "%s: could not allocate rate table for %s\n",
 329                         __func__, name);
 330         }
 331
 332         switch (pll_type) {
 333         case pll_rk3066:
 334                 if (!pll->rate_table)
 335                         init.ops = &rockchip_rk3066_pll_clk_norate_ops;
 336                 else
 337                         init.ops = &rockchip_rk3066_pll_clk_ops;
 338                 break;
 339         default:
 340                 pr_warn("%s: Unknown pll type for pll clk %s\n",
 341                         __func__, name);
 342         }
 343
 344         pll->hw.init = &init;
 345         pll->type = pll_type;
 346         pll->reg_base = base + con_offset;
 347         pll->lock_offset = grf_lock_offset;
 348         pll->lock_shift = lock_shift;
 349         pll->flags = clk_pll_flags;
 350         pll->lock = lock;
 351
 352         pll_clk = clk_register(NULL, &pll->hw);
 353         if (IS_ERR(pll_clk)) {
 354                 pr_err("%s: failed to register pll clock %s : %ld\n",
 355                         __func__, name, PTR_ERR(pll_clk));
 356                 mux_clk = pll_clk;
 357                 goto err_pll;
 358         }
 359
 360         /* create the mux on top of the real pll */
 361         pll->pll_mux_ops = &clk_mux_ops;
 362         pll_mux = &pll->pll_mux;
 363
 364         /* the actual muxing is xin24m, pll-output, xin32k */
 365         pll_parents[0] = parent_names[0];
 366         pll_parents[1] = pll_name;
 367         pll_parents[2] = parent_names[1];
 368
 369         init.name = name;
 370         init.flags = CLK_SET_RATE_PARENT;
 371         init.ops = pll->pll_mux_ops;
 372         init.parent_names = pll_parents;
 373         init.num_parents = ARRAY_SIZE(pll_parents);
 374
 375         pll_mux->reg = base + mode_offset;
 376         pll_mux->shift = mode_shift;
 377         pll_mux->mask = PLL_MODE_MASK;
 378         pll_mux->flags = 0;
 379         pll_mux->lock = lock;
 380         pll_mux->hw.init = &init;
 381
 382         if (pll_type == pll_rk3066)
 383                 pll_mux->flags |= CLK_MUX_HIWORD_MASK;
 384
 385         mux_clk = clk_register(NULL, &pll_mux->hw);
 386         if (IS_ERR(mux_clk))
 387                 goto err_mux;
 388
 389         return mux_clk;
 390
 391 err_mux:
 392         clk_unregister(pll_clk);
 393 err_pll:
 394         kfree(pll);
 395         return mux_clk;
 396 }