2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
8 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
9 * Copyright (c) 2013 Linaro Ltd.
10 * Author: Thomas Abraham <thomas.ab@samsung.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
23 #ifndef CLK_ROCKCHIP_CLK_H
24 #define CLK_ROCKCHIP_CLK_H
27 #include <linux/clk.h>
28 #include <linux/clk-provider.h>
30 #define HIWORD_UPDATE(val, mask, shift) \
31 ((val) << (shift) | (mask) << ((shift) + 16))
33 /* register positions shared by RK2928, RK3066 and RK3188 */
34 #define RK2928_PLL_CON(x) (x * 0x4)
35 #define RK2928_MODE_CON 0x40
36 #define RK2928_CLKSEL_CON(x) (x * 0x4 + 0x44)
37 #define RK2928_CLKGATE_CON(x) (x * 0x4 + 0xd0)
38 #define RK2928_GLB_SRST_FST 0x100
39 #define RK2928_GLB_SRST_SND 0x104
40 #define RK2928_SOFTRST_CON(x) (x * 0x4 + 0x110)
41 #define RK2928_MISC_CON 0x134
43 #define RK3288_PLL_CON(x) RK2928_PLL_CON(x)
44 #define RK3288_MODE_CON 0x50
45 #define RK3288_CLKSEL_CON(x) (x * 0x4 + 0x60)
46 #define RK3288_CLKGATE_CON(x) (x * 0x4 + 0x160)
47 #define RK3288_GLB_SRST_FST 0x1b0
48 #define RK3288_GLB_SRST_SND 0x1b4
49 #define RK3288_SOFTRST_CON(x) (x * 0x4 + 0x1b8)
50 #define RK3288_MISC_CON 0x1e8
52 enum rockchip_pll_type
{
56 #define RK3066_PLL_RATE(_rate, _nr, _nf, _no) \
62 .bwadj = (_nf >> 1), \
65 struct rockchip_pll_rate_table
{
74 * struct rockchip_pll_clock: information about pll clock
75 * @id: platform specific id of the clock.
76 * @name: name of this pll clock.
77 * @parent_name: name of the parent clock.
78 * @flags: optional flags for basic clock.
79 * @con_offset: offset of the register for configuring the PLL.
80 * @mode_offset: offset of the register for configuring the PLL-mode.
81 * @mode_shift: offset inside the mode-register for the mode of this pll.
82 * @lock_shift: offset inside the lock register for the lock status.
83 * @type: Type of PLL to be registered.
84 * @rate_table: Table of usable pll rates
86 struct rockchip_pll_clock
{
89 const char **parent_names
;
96 enum rockchip_pll_type type
;
97 struct rockchip_pll_rate_table
*rate_table
;
100 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \
106 .parent_names = _pnames, \
107 .num_parents = ARRAY_SIZE(_pnames), \
108 .flags = CLK_GET_RATE_NOCACHE | _flags, \
109 .con_offset = _con, \
110 .mode_offset = _mode, \
111 .mode_shift = _mshift, \
112 .lock_shift = _lshift, \
113 .rate_table = _rtable, \
116 struct clk
*rockchip_clk_register_pll(enum rockchip_pll_type pll_type
,
117 const char *name
, const char **parent_names
, u8 num_parents
,
118 void __iomem
*base
, int con_offset
, int grf_lock_offset
,
119 int lock_shift
, int reg_mode
, int mode_shift
,
120 struct rockchip_pll_rate_table
*rate_table
,
123 #define PNAME(x) static const char *x[] __initconst
125 enum rockchip_clk_branch_type
{
129 branch_fraction_divider
,
133 struct rockchip_clk_branch
{
135 enum rockchip_clk_branch_type branch_type
;
137 const char **parent_names
;
147 struct clk_div_table
*div_table
;
153 #define COMPOSITE(_id, cname, pnames, f, mo, ms, mw, mf, ds, dw,\
157 .branch_type = branch_composite, \
159 .parent_names = pnames, \
160 .num_parents = ARRAY_SIZE(pnames), \
162 .muxdiv_offset = mo, \
174 #define COMPOSITE_NOMUX(_id, cname, pname, f, mo, ds, dw, df, \
178 .branch_type = branch_composite, \
180 .parent_names = (const char *[]){ pname }, \
183 .muxdiv_offset = mo, \
192 #define COMPOSITE_NOMUX_DIVTBL(_id, cname, pname, f, mo, ds, dw,\
193 df, dt, go, gs, gf) \
196 .branch_type = branch_composite, \
198 .parent_names = (const char *[]){ pname }, \
201 .muxdiv_offset = mo, \
211 #define COMPOSITE_NODIV(_id, cname, pnames, f, mo, ms, mw, mf, \
215 .branch_type = branch_composite, \
217 .parent_names = pnames, \
218 .num_parents = ARRAY_SIZE(pnames), \
220 .muxdiv_offset = mo, \
229 #define COMPOSITE_NOGATE(_id, cname, pnames, f, mo, ms, mw, mf, \
233 .branch_type = branch_composite, \
235 .parent_names = pnames, \
236 .num_parents = ARRAY_SIZE(pnames), \
238 .muxdiv_offset = mo, \
248 #define COMPOSITE_FRAC(_id, cname, pname, f, mo, df, go, gs, gf)\
251 .branch_type = branch_fraction_divider, \
253 .parent_names = (const char *[]){ pname }, \
256 .muxdiv_offset = mo, \
265 #define MUX(_id, cname, pnames, f, o, s, w, mf) \
268 .branch_type = branch_mux, \
270 .parent_names = pnames, \
271 .num_parents = ARRAY_SIZE(pnames), \
273 .muxdiv_offset = o, \
280 #define DIV(_id, cname, pname, f, o, s, w, df) \
283 .branch_type = branch_divider, \
285 .parent_names = (const char *[]){ pname }, \
288 .muxdiv_offset = o, \
295 #define DIVTBL(_id, cname, pname, f, o, s, w, df, dt) \
298 .branch_type = branch_divider, \
300 .parent_names = (const char *[]){ pname }, \
303 .muxdiv_offset = o, \
310 #define GATE(_id, cname, pname, f, o, b, gf) \
313 .branch_type = branch_gate, \
315 .parent_names = (const char *[]){ pname }, \
324 void rockchip_clk_init(struct device_node
*np
, void __iomem
*base
,
325 unsigned long nr_clks
);
326 struct regmap
*rockchip_clk_get_grf(void);
327 void rockchip_clk_add_lookup(struct clk
*clk
, unsigned int id
);
328 void rockchip_clk_register_branches(struct rockchip_clk_branch
*clk_list
,
329 unsigned int nr_clk
);
330 void rockchip_clk_register_plls(struct rockchip_pll_clock
*pll_list
,
331 unsigned int nr_pll
, int grf_lock_offset
);
332 void rockchip_clk_protect_critical(const char *clocks
[], int nclocks
);
334 #define ROCKCHIP_SOFTRST_HIWORD_MASK BIT(0)
336 #ifdef CONFIG_RESET_CONTROLLER
337 void rockchip_register_softrst(struct device_node
*np
,
338 unsigned int num_regs
,
339 void __iomem
*base
, u8 flags
);
341 static inline void rockchip_register_softrst(struct device_node
*np
,
342 unsigned int num_regs
,
343 void __iomem
*base
, u8 flags
)