drivers/clk/tegra/clk.h

   1         /*
   2  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #ifndef __TEGRA_CLK_H
  18 #define __TEGRA_CLK_H
  19
  20 #include <linux/clk-provider.h>
  21 #include <linux/clkdev.h>
  22
  23 /**
  24  * struct tegra_clk_sync_source - external clock source from codec
  25  *
  26  * @hw: handle between common and hardware-specific interfaces
  27  * @rate: input frequency from source
  28  * @max_rate: max rate allowed
  29  */
  30 struct tegra_clk_sync_source {
  31         struct          clk_hw hw;
  32         unsigned long   rate;
  33         unsigned long   max_rate;
  34 };
  35
  36 #define to_clk_sync_source(_hw)                                 \
  37         container_of(_hw, struct tegra_clk_sync_source, hw)
  38
  39 extern const struct clk_ops tegra_clk_sync_source_ops;
  40 extern int *periph_clk_enb_refcnt;
  41
  42 struct clk *tegra_clk_register_sync_source(const char *name,
  43                 unsigned long fixed_rate, unsigned long max_rate);
  44
  45 /**
  46  * struct tegra_clk_frac_div - fractional divider clock
  47  *
  48  * @hw:         handle between common and hardware-specific interfaces
  49  * @reg:        register containing divider
  50  * @flags:      hardware-specific flags
  51  * @shift:      shift to the divider bit field
  52  * @width:      width of the divider bit field
  53  * @frac_width: width of the fractional bit field
  54  * @lock:       register lock
  55  *
  56  * Flags:
  57  * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
  58  * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
  59  *      flag indicates that this divider is for fixed rate PLL.
  60  * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
  61  *      fraction bit is set. This flags indicates to calculate divider for which
  62  *      fracton bit will be zero.
  63  * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is
  64  *      set when divider value is not 0. This flags indicates that the divider
  65  *      is for UART module.
  66  */
  67 struct tegra_clk_frac_div {
  68         struct clk_hw   hw;
  69         void __iomem    *reg;
  70         u8              flags;
  71         u8              shift;
  72         u8              width;
  73         u8              frac_width;
  74         spinlock_t      *lock;
  75 };
  76
  77 #define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw)
  78
  79 #define TEGRA_DIVIDER_ROUND_UP BIT(0)
  80 #define TEGRA_DIVIDER_FIXED BIT(1)
  81 #define TEGRA_DIVIDER_INT BIT(2)
  82 #define TEGRA_DIVIDER_UART BIT(3)
  83
  84 extern const struct clk_ops tegra_clk_frac_div_ops;
  85 struct clk *tegra_clk_register_divider(const char *name,
  86                 const char *parent_name, void __iomem *reg,
  87                 unsigned long flags, u8 clk_divider_flags, u8 shift, u8 width,
  88                 u8 frac_width, spinlock_t *lock);
  89 struct clk *tegra_clk_register_mc(const char *name, const char *parent_name,
  90                                   void __iomem *reg, spinlock_t *lock);
  91
  92 /*
  93  * Tegra PLL:
  94  *
  95  * In general, there are 3 requirements for each PLL
  96  * that SW needs to be comply with.
  97  * (1) Input frequency range (REF).
  98  * (2) Comparison frequency range (CF). CF = REF/DIVM.
  99  * (3) VCO frequency range (VCO).  VCO = CF * DIVN.
 100  *
 101  * The final PLL output frequency (FO) = VCO >> DIVP.
 102  */
 103
 104 /**
 105  * struct tegra_clk_pll_freq_table - PLL frequecy table
 106  *
 107  * @input_rate:         input rate from source
 108  * @output_rate:        output rate from PLL for the input rate
 109  * @n:                  feedback divider
 110  * @m:                  input divider
 111  * @p:                  post divider
 112  * @cpcon:              charge pump current
 113  */
 114 struct tegra_clk_pll_freq_table {
 115         unsigned long   input_rate;
 116         unsigned long   output_rate;
 117         u16             n;
 118         u16             m;
 119         u8              p;
 120         u8              cpcon;
 121 };
 122
 123 /**
 124  * struct pdiv_map - map post divider to hw value
 125  *
 126  * @pdiv:               post divider
 127  * @hw_val:             value to be written to the PLL hw
 128  */
 129 struct pdiv_map {
 130         u8 pdiv;
 131         u8 hw_val;
 132 };
 133
 134 /**
 135  * struct div_nmp - offset and width of m,n and p fields
 136  *
 137  * @divn_shift: shift to the feedback divider bit field
 138  * @divn_width: width of the feedback divider bit field
 139  * @divm_shift: shift to the input divider bit field
 140  * @divm_width: width of the input divider bit field
 141  * @divp_shift: shift to the post divider bit field
 142  * @divp_width: width of the post divider bit field
 143  * @override_divn_shift: shift to the feedback divider bitfield in override reg
 144  * @override_divm_shift: shift to the input divider bitfield in override reg
 145  * @override_divp_shift: shift to the post divider bitfield in override reg
 146  */
 147 struct div_nmp {
 148         u8              divn_shift;
 149         u8              divn_width;
 150         u8              divm_shift;
 151         u8              divm_width;
 152         u8              divp_shift;
 153         u8              divp_width;
 154         u8              override_divn_shift;
 155         u8              override_divm_shift;
 156         u8              override_divp_shift;
 157 };
 158
 159 /**
 160  * struct tegra_clk_pll_params - PLL parameters
 161  *
 162  * @input_min:                  Minimum input frequency
 163  * @input_max:                  Maximum input frequency
 164  * @cf_min:                     Minimum comparison frequency
 165  * @cf_max:                     Maximum comparison frequency
 166  * @vco_min:                    Minimum VCO frequency
 167  * @vco_max:                    Maximum VCO frequency
 168  * @base_reg:                   PLL base reg offset
 169  * @misc_reg:                   PLL misc reg offset
 170  * @lock_reg:                   PLL lock reg offset
 171  * @lock_mask:                  Bitmask for PLL lock status
 172  * @lock_enable_bit_idx:        Bit index to enable PLL lock
 173  * @iddq_reg:                   PLL IDDQ register offset
 174  * @iddq_bit_idx:               Bit index to enable PLL IDDQ
 175  * @aux_reg:                    AUX register offset
 176  * @dyn_ramp_reg:               Dynamic ramp control register offset
 177  * @ext_misc_reg:               Miscellaneous control register offsets
 178  * @pmc_divnm_reg:              n, m divider PMC override register offset (PLLM)
 179  * @pmc_divp_reg:               p divider PMC override register offset (PLLM)
 180  * @flags:                      PLL flags
 181  * @stepa_shift:                Dynamic ramp step A field shift
 182  * @stepb_shift:                Dynamic ramp step B field shift
 183  * @lock_delay:                 Delay in us if PLL lock is not used
 184  * @max_p:                      maximum value for the p divider
 185  * @pdiv_tohw:                  mapping of p divider to register values
 186  * @div_nmp:                    offsets and widths on n, m and p fields
 187  * @freq_table:                 array of frequencies supported by PLL
 188  * @fixed_rate:                 PLL rate if it is fixed
 189  *
 190  * Flags:
 191  * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
 192  *     PLL locking. If not set it will use lock_delay value to wait.
 193  * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
 194  *     to be programmed to change output frequency of the PLL.
 195  * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
 196  *     to be programmed to change output frequency of the PLL.
 197  * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
 198  *     to be programmed to change output frequency of the PLL.
 199  * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
 200  *     that it is PLLU and invert post divider value.
 201  * TEGRA_PLLM - PLLM has additional override settings in PMC. This
 202  *     flag indicates that it is PLLM and use override settings.
 203  * TEGRA_PLL_FIXED - We are not supposed to change output frequency
 204  *     of some plls.
 205  * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
 206  * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
 207  *     base register.
 208  * TEGRA_PLL_BYPASS - PLL has bypass bit
 209  * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
 210  */
 211 struct tegra_clk_pll_params {
 212         unsigned long   input_min;
 213         unsigned long   input_max;
 214         unsigned long   cf_min;
 215         unsigned long   cf_max;
 216         unsigned long   vco_min;
 217         unsigned long   vco_max;
 218
 219         u32             base_reg;
 220         u32             misc_reg;
 221         u32             lock_reg;
 222         u32             lock_mask;
 223         u32             lock_enable_bit_idx;
 224         u32             iddq_reg;
 225         u32             iddq_bit_idx;
 226         u32             aux_reg;
 227         u32             dyn_ramp_reg;
 228         u32             ext_misc_reg[3];
 229         u32             pmc_divnm_reg;
 230         u32             pmc_divp_reg;
 231         u32             flags;
 232         int             stepa_shift;
 233         int             stepb_shift;
 234         int             lock_delay;
 235         int             max_p;
 236         struct pdiv_map *pdiv_tohw;
 237         struct div_nmp  *div_nmp;
 238         struct tegra_clk_pll_freq_table *freq_table;
 239         unsigned long   fixed_rate;
 240 };
 241
 242 #define TEGRA_PLL_USE_LOCK BIT(0)
 243 #define TEGRA_PLL_HAS_CPCON BIT(1)
 244 #define TEGRA_PLL_SET_LFCON BIT(2)
 245 #define TEGRA_PLL_SET_DCCON BIT(3)
 246 #define TEGRA_PLLU BIT(4)
 247 #define TEGRA_PLLM BIT(5)
 248 #define TEGRA_PLL_FIXED BIT(6)
 249 #define TEGRA_PLLE_CONFIGURE BIT(7)
 250 #define TEGRA_PLL_LOCK_MISC BIT(8)
 251 #define TEGRA_PLL_BYPASS BIT(9)
 252 #define TEGRA_PLL_HAS_LOCK_ENABLE BIT(10)
 253
 254 /**
 255  * struct tegra_clk_pll - Tegra PLL clock
 256  *
 257  * @hw:         handle between common and hardware-specifix interfaces
 258  * @clk_base:   address of CAR controller
 259  * @pmc:        address of PMC, required to read override bits
 260  * @lock:       register lock
 261  * @params:     PLL parameters
 262  */
 263 struct tegra_clk_pll {
 264         struct clk_hw   hw;
 265         void __iomem    *clk_base;
 266         void __iomem    *pmc;
 267         spinlock_t      *lock;
 268         struct tegra_clk_pll_params     *params;
 269 };
 270
 271 #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw)
 272
 273 /**
 274  * struct tegra_audio_clk_info - Tegra Audio Clk Information
 275  *
 276  * @name:       name for the audio pll
 277  * @pll_params: pll_params for audio pll
 278  * @clk_id:     clk_ids for the audio pll
 279  * @parent:     name of the parent of the audio pll
 280  */
 281 struct tegra_audio_clk_info {
 282         char *name;
 283         struct tegra_clk_pll_params *pll_params;
 284         int clk_id;
 285         char *parent;
 286 };
 287
 288 extern const struct clk_ops tegra_clk_pll_ops;
 289 extern const struct clk_ops tegra_clk_plle_ops;
 290 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name,
 291                 void __iomem *clk_base, void __iomem *pmc,
 292                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
 293                 spinlock_t *lock);
 294
 295 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name,
 296                 void __iomem *clk_base, void __iomem *pmc,
 297                 unsigned long flags, struct tegra_clk_pll_params *pll_params,
 298                 spinlock_t *lock);
 299
 300 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
 301                             void __iomem *clk_base, void __iomem *pmc,
 302                             unsigned long flags,
 303                             struct tegra_clk_pll_params *pll_params,
 304                             spinlock_t *lock);
 305
 306 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
 307                            void __iomem *clk_base, void __iomem *pmc,
 308                            unsigned long flags,
 309                            struct tegra_clk_pll_params *pll_params,
 310                            spinlock_t *lock);
 311
 312 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name,
 313                            void __iomem *clk_base, void __iomem *pmc,
 314                            unsigned long flags,
 315                            struct tegra_clk_pll_params *pll_params,
 316                            spinlock_t *lock);
 317
 318 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
 319                            void __iomem *clk_base, void __iomem *pmc,
 320                            unsigned long flags,
 321                            struct tegra_clk_pll_params *pll_params,
 322                            spinlock_t *lock, unsigned long parent_rate);
 323
 324 struct clk *tegra_clk_register_plle_tegra114(const char *name,
 325                                 const char *parent_name,
 326                                 void __iomem *clk_base, unsigned long flags,
 327                                 struct tegra_clk_pll_params *pll_params,
 328                                 spinlock_t *lock);
 329
 330 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
 331                            void __iomem *clk_base, unsigned long flags,
 332                            struct tegra_clk_pll_params *pll_params,
 333                            spinlock_t *lock);
 334
 335 /**
 336  * struct tegra_clk_pll_out - PLL divider down clock
 337  *
 338  * @hw:                 handle between common and hardware-specific interfaces
 339  * @reg:                register containing the PLL divider
 340  * @enb_bit_idx:        bit to enable/disable PLL divider
 341  * @rst_bit_idx:        bit to reset PLL divider
 342  * @lock:               register lock
 343  * @flags:              hardware-specific flags
 344  */
 345 struct tegra_clk_pll_out {
 346         struct clk_hw   hw;
 347         void __iomem    *reg;
 348         u8              enb_bit_idx;
 349         u8              rst_bit_idx;
 350         spinlock_t      *lock;
 351         u8              flags;
 352 };
 353
 354 #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw)
 355
 356 extern const struct clk_ops tegra_clk_pll_out_ops;
 357 struct clk *tegra_clk_register_pll_out(const char *name,
 358                 const char *parent_name, void __iomem *reg, u8 enb_bit_idx,
 359                 u8 rst_bit_idx, unsigned long flags, u8 pll_div_flags,
 360                 spinlock_t *lock);
 361
 362 /**
 363  * struct tegra_clk_periph_regs -  Registers controlling peripheral clock
 364  *
 365  * @enb_reg:            read the enable status
 366  * @enb_set_reg:        write 1 to enable clock
 367  * @enb_clr_reg:        write 1 to disable clock
 368  * @rst_reg:            read the reset status
 369  * @rst_set_reg:        write 1 to assert the reset of peripheral
 370  * @rst_clr_reg:        write 1 to deassert the reset of peripheral
 371  */
 372 struct tegra_clk_periph_regs {
 373         u32 enb_reg;
 374         u32 enb_set_reg;
 375         u32 enb_clr_reg;
 376         u32 rst_reg;
 377         u32 rst_set_reg;
 378         u32 rst_clr_reg;
 379 };
 380
 381 /**
 382  * struct tegra_clk_periph_gate - peripheral gate clock
 383  *
 384  * @magic:              magic number to validate type
 385  * @hw:                 handle between common and hardware-specific interfaces
 386  * @clk_base:           address of CAR controller
 387  * @regs:               Registers to control the peripheral
 388  * @flags:              hardware-specific flags
 389  * @clk_num:            Clock number
 390  * @enable_refcnt:      array to maintain reference count of the clock
 391  *
 392  * Flags:
 393  * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed
 394  *     for this module.
 395  * TEGRA_PERIPH_MANUAL_RESET - This flag indicates not to reset module
 396  *     after clock enable and driver for the module is responsible for
 397  *     doing reset.
 398  * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
 399  *     bus to flush the write operation in apb bus. This flag indicates
 400  *     that this peripheral is in apb bus.
 401  * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug
 402  */
 403 struct tegra_clk_periph_gate {
 404         u32                     magic;
 405         struct clk_hw           hw;
 406         void __iomem            *clk_base;
 407         u8                      flags;
 408         int                     clk_num;
 409         int                     *enable_refcnt;
 410         struct tegra_clk_periph_regs    *regs;
 411 };
 412
 413 #define to_clk_periph_gate(_hw)                                 \
 414         container_of(_hw, struct tegra_clk_periph_gate, hw)
 415
 416 #define TEGRA_CLK_PERIPH_GATE_MAGIC 0x17760309
 417
 418 #define TEGRA_PERIPH_NO_RESET BIT(0)
 419 #define TEGRA_PERIPH_MANUAL_RESET BIT(1)
 420 #define TEGRA_PERIPH_ON_APB BIT(2)
 421 #define TEGRA_PERIPH_WAR_1005168 BIT(3)
 422 #define TEGRA_PERIPH_NO_DIV BIT(4)
 423 #define TEGRA_PERIPH_NO_GATE BIT(5)
 424
 425 extern const struct clk_ops tegra_clk_periph_gate_ops;
 426 struct clk *tegra_clk_register_periph_gate(const char *name,
 427                 const char *parent_name, u8 gate_flags, void __iomem *clk_base,
 428                 unsigned long flags, int clk_num, int *enable_refcnt);
 429
 430 /**
 431  * struct clk-periph - peripheral clock
 432  *
 433  * @magic:      magic number to validate type
 434  * @hw:         handle between common and hardware-specific interfaces
 435  * @mux:        mux clock
 436  * @divider:    divider clock
 437  * @gate:       gate clock
 438  * @mux_ops:    mux clock ops
 439  * @div_ops:    divider clock ops
 440  * @gate_ops:   gate clock ops
 441  */
 442 struct tegra_clk_periph {
 443         u32                     magic;
 444         struct clk_hw           hw;
 445         struct clk_mux          mux;
 446         struct tegra_clk_frac_div       divider;
 447         struct tegra_clk_periph_gate    gate;
 448
 449         const struct clk_ops    *mux_ops;
 450         const struct clk_ops    *div_ops;
 451         const struct clk_ops    *gate_ops;
 452 };
 453
 454 #define to_clk_periph(_hw) container_of(_hw, struct tegra_clk_periph, hw)
 455
 456 #define TEGRA_CLK_PERIPH_MAGIC 0x18221223
 457
 458 extern const struct clk_ops tegra_clk_periph_ops;
 459 struct clk *tegra_clk_register_periph(const char *name,
 460                 const char **parent_names, int num_parents,
 461                 struct tegra_clk_periph *periph, void __iomem *clk_base,
 462                 u32 offset, unsigned long flags);
 463 struct clk *tegra_clk_register_periph_nodiv(const char *name,
 464                 const char **parent_names, int num_parents,
 465                 struct tegra_clk_periph *periph, void __iomem *clk_base,
 466                 u32 offset);
 467
 468 #define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags,             \
 469                          _div_shift, _div_width, _div_frac_width,       \
 470                          _div_flags, _clk_num,\
 471                          _gate_flags, _table, _lock)                    \
 472         {                                                               \
 473                 .mux = {                                                \
 474                         .flags = _mux_flags,                            \
 475                         .shift = _mux_shift,                            \
 476                         .mask = _mux_mask,                              \
 477                         .table = _table,                                \
 478                         .lock = _lock,                                  \
 479                 },                                                      \
 480                 .divider = {                                            \
 481                         .flags = _div_flags,                            \
 482                         .shift = _div_shift,                            \
 483                         .width = _div_width,                            \
 484                         .frac_width = _div_frac_width,                  \
 485                         .lock = _lock,                                  \
 486                 },                                                      \
 487                 .gate = {                                               \
 488                         .flags = _gate_flags,                           \
 489                         .clk_num = _clk_num,                            \
 490                 },                                                      \
 491                 .mux_ops = &clk_mux_ops,                                \
 492                 .div_ops = &tegra_clk_frac_div_ops,                     \
 493                 .gate_ops = &tegra_clk_periph_gate_ops,                 \
 494         }
 495
 496 struct tegra_periph_init_data {
 497         const char *name;
 498         int clk_id;
 499         union {
 500                 const char **parent_names;
 501                 const char *parent_name;
 502         } p;
 503         int num_parents;
 504         struct tegra_clk_periph periph;
 505         u32 offset;
 506         const char *con_id;
 507         const char *dev_id;
 508         unsigned long flags;
 509 };
 510
 511 #define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
 512                         _mux_shift, _mux_mask, _mux_flags, _div_shift,  \
 513                         _div_width, _div_frac_width, _div_flags,        \
 514                         _clk_num, _gate_flags, _clk_id, _table,         \
 515                         _flags, _lock) \
 516         {                                                               \
 517                 .name = _name,                                          \
 518                 .clk_id = _clk_id,                                      \
 519                 .p.parent_names = _parent_names,                        \
 520                 .num_parents = ARRAY_SIZE(_parent_names),               \
 521                 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask,       \
 522                                            _mux_flags, _div_shift,      \
 523                                            _div_width, _div_frac_width, \
 524                                            _div_flags, _clk_num,        \
 525                                            _gate_flags, _table, _lock), \
 526                 .offset = _offset,                                      \
 527                 .con_id = _con_id,                                      \
 528                 .dev_id = _dev_id,                                      \
 529                 .flags = _flags                                         \
 530         }
 531
 532 #define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\
 533                         _mux_shift, _mux_width, _mux_flags, _div_shift, \
 534                         _div_width, _div_frac_width, _div_flags, \
 535                         _clk_num, _gate_flags, _clk_id) \
 536         TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
 537                         _mux_shift, BIT(_mux_width) - 1, _mux_flags,    \
 538                         _div_shift, _div_width, _div_frac_width, _div_flags, \
 539                         _clk_num, _gate_flags, _clk_id,\
 540                         NULL, 0, NULL)
 541
 542 /**
 543  * struct clk_super_mux - super clock
 544  *
 545  * @hw:         handle between common and hardware-specific interfaces
 546  * @reg:        register controlling multiplexer
 547  * @width:      width of the multiplexer bit field
 548  * @flags:      hardware-specific flags
 549  * @div2_index: bit controlling divide-by-2
 550  * @pllx_index: PLLX index in the parent list
 551  * @lock:       register lock
 552  *
 553  * Flags:
 554  * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates
 555  *     that this is LP cluster clock.
 556  */
 557 struct tegra_clk_super_mux {
 558         struct clk_hw   hw;
 559         void __iomem    *reg;
 560         u8              width;
 561         u8              flags;
 562         u8              div2_index;
 563         u8              pllx_index;
 564         spinlock_t      *lock;
 565 };
 566
 567 #define to_clk_super_mux(_hw) container_of(_hw, struct tegra_clk_super_mux, hw)
 568
 569 #define TEGRA_DIVIDER_2 BIT(0)
 570
 571 extern const struct clk_ops tegra_clk_super_ops;
 572 struct clk *tegra_clk_register_super_mux(const char *name,
 573                 const char **parent_names, u8 num_parents,
 574                 unsigned long flags, void __iomem *reg, u8 clk_super_flags,
 575                 u8 width, u8 pllx_index, u8 div2_index, spinlock_t *lock);
 576
 577 /**
 578  * struct clk_init_table - clock initialization table
 579  * @clk_id:     clock id as mentioned in device tree bindings
 580  * @parent_id:  parent clock id as mentioned in device tree bindings
 581  * @rate:       rate to set
 582  * @state:      enable/disable
 583  */
 584 struct tegra_clk_init_table {
 585         unsigned int    clk_id;
 586         unsigned int    parent_id;
 587         unsigned long   rate;
 588         int             state;
 589 };
 590
 591 /**
 592  * struct clk_duplicate - duplicate clocks
 593  * @clk_id:     clock id as mentioned in device tree bindings
 594  * @lookup:     duplicate lookup entry for the clock
 595  */
 596 struct tegra_clk_duplicate {
 597         int                     clk_id;
 598         struct clk_lookup       lookup;
 599 };
 600
 601 #define TEGRA_CLK_DUPLICATE(_clk_id, _dev, _con) \
 602         {                                       \
 603                 .clk_id = _clk_id,              \
 604                 .lookup = {                     \
 605                         .dev_id = _dev,         \
 606                         .con_id = _con,         \
 607                 },                              \
 608         }
 609
 610 struct tegra_clk {
 611         int                     dt_id;
 612         bool                    present;
 613 };
 614
 615 struct tegra_devclk {
 616         int             dt_id;
 617         char            *dev_id;
 618         char            *con_id;
 619 };
 620
 621 void tegra_init_special_resets(unsigned int num, int (*assert)(unsigned long),
 622                                int (*deassert)(unsigned long));
 623
 624 void tegra_init_from_table(struct tegra_clk_init_table *tbl,
 625                 struct clk *clks[], int clk_max);
 626
 627 void tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
 628                 struct clk *clks[], int clk_max);
 629
 630 struct tegra_clk_periph_regs *get_reg_bank(int clkid);
 631 struct clk **tegra_clk_init(void __iomem *clk_base, int num, int periph_banks);
 632
 633 struct clk **tegra_lookup_dt_id(int clk_id, struct tegra_clk *tegra_clk);
 634
 635 void tegra_add_of_provider(struct device_node *np);
 636 void tegra_register_devclks(struct tegra_devclk *dev_clks, int num);
 637
 638 void tegra_audio_clk_init(void __iomem *clk_base,
 639                         void __iomem *pmc_base, struct tegra_clk *tegra_clks,
 640                         struct tegra_audio_clk_info *audio_info,
 641                         unsigned int num_plls);
 642
 643 void tegra_periph_clk_init(void __iomem *clk_base, void __iomem *pmc_base,
 644                         struct tegra_clk *tegra_clks,
 645                         struct tegra_clk_pll_params *pll_params);
 646
 647 void tegra_pmc_clk_init(void __iomem *pmc_base, struct tegra_clk *tegra_clks);
 648 void tegra_fixed_clk_init(struct tegra_clk *tegra_clks);
 649 int tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
 650                        unsigned long *input_freqs, unsigned int num,
 651                        unsigned int clk_m_div, unsigned long *osc_freq,
 652                        unsigned long *pll_ref_freq);
 653 void tegra_super_clk_gen4_init(void __iomem *clk_base,
 654                         void __iomem *pmc_base, struct tegra_clk *tegra_clks,
 655                         struct tegra_clk_pll_params *pll_params);
 656
 657 #ifdef CONFIG_TEGRA_CLK_EMC
 658 struct clk *tegra_clk_register_emc(void __iomem *base, struct device_node *np,
 659                                    spinlock_t *lock);
 660 #else
 661 static inline struct clk *tegra_clk_register_emc(void __iomem *base,
 662                                                  struct device_node *np,
 663                                                  spinlock_t *lock)
 664 {
 665         return NULL;
 666 }
 667 #endif
 668
 669 void tegra114_clock_tune_cpu_trimmers_high(void);
 670 void tegra114_clock_tune_cpu_trimmers_low(void);
 671 void tegra114_clock_tune_cpu_trimmers_init(void);
 672 void tegra114_clock_assert_dfll_dvco_reset(void);
 673 void tegra114_clock_deassert_dfll_dvco_reset(void);
 674
 675 typedef void (*tegra_clk_apply_init_table_func)(void);
 676 extern tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
 677
 678 #endif /* TEGRA_CLK_H */