2 * Zynq clock controller
4 * Copyright (C) 2012 - 2013 Xilinx
6 * Sören Brinkmann <soren.brinkmann@xilinx.com>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License v2 as published by
10 * the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/clk/zynq.h>
22 #include <linux/clk-provider.h>
24 #include <linux/slab.h>
25 #include <linux/string.h>
28 static void __iomem
*zynq_slcr_base_priv
;
30 #define SLCR_ARMPLL_CTRL (zynq_slcr_base_priv + 0x100)
31 #define SLCR_DDRPLL_CTRL (zynq_slcr_base_priv + 0x104)
32 #define SLCR_IOPLL_CTRL (zynq_slcr_base_priv + 0x108)
33 #define SLCR_PLL_STATUS (zynq_slcr_base_priv + 0x10c)
34 #define SLCR_ARM_CLK_CTRL (zynq_slcr_base_priv + 0x120)
35 #define SLCR_DDR_CLK_CTRL (zynq_slcr_base_priv + 0x124)
36 #define SLCR_DCI_CLK_CTRL (zynq_slcr_base_priv + 0x128)
37 #define SLCR_APER_CLK_CTRL (zynq_slcr_base_priv + 0x12c)
38 #define SLCR_GEM0_CLK_CTRL (zynq_slcr_base_priv + 0x140)
39 #define SLCR_GEM1_CLK_CTRL (zynq_slcr_base_priv + 0x144)
40 #define SLCR_SMC_CLK_CTRL (zynq_slcr_base_priv + 0x148)
41 #define SLCR_LQSPI_CLK_CTRL (zynq_slcr_base_priv + 0x14c)
42 #define SLCR_SDIO_CLK_CTRL (zynq_slcr_base_priv + 0x150)
43 #define SLCR_UART_CLK_CTRL (zynq_slcr_base_priv + 0x154)
44 #define SLCR_SPI_CLK_CTRL (zynq_slcr_base_priv + 0x158)
45 #define SLCR_CAN_CLK_CTRL (zynq_slcr_base_priv + 0x15c)
46 #define SLCR_CAN_MIOCLK_CTRL (zynq_slcr_base_priv + 0x160)
47 #define SLCR_DBG_CLK_CTRL (zynq_slcr_base_priv + 0x164)
48 #define SLCR_PCAP_CLK_CTRL (zynq_slcr_base_priv + 0x168)
49 #define SLCR_FPGA0_CLK_CTRL (zynq_slcr_base_priv + 0x170)
50 #define SLCR_621_TRUE (zynq_slcr_base_priv + 0x1c4)
51 #define SLCR_SWDT_CLK_SEL (zynq_slcr_base_priv + 0x304)
53 #define NUM_MIO_PINS 54
56 armpll
, ddrpll
, iopll
,
57 cpu_6or4x
, cpu_3or2x
, cpu_2x
, cpu_1x
,
59 lqspi
, smc
, pcap
, gem0
, gem1
, fclk0
, fclk1
, fclk2
, fclk3
, can0
, can1
,
60 sdio0
, sdio1
, uart0
, uart1
, spi0
, spi1
, dma
,
61 usb0_aper
, usb1_aper
, gem0_aper
, gem1_aper
,
62 sdio0_aper
, sdio1_aper
, spi0_aper
, spi1_aper
, can0_aper
, can1_aper
,
63 i2c0_aper
, i2c1_aper
, uart0_aper
, uart1_aper
, gpio_aper
, lqspi_aper
,
64 smc_aper
, swdt
, dbg_trc
, dbg_apb
, clk_max
};
66 static struct clk
*ps_clk
;
67 static struct clk
*clks
[clk_max
];
68 static struct clk_onecell_data clk_data
;
70 static DEFINE_SPINLOCK(armpll_lock
);
71 static DEFINE_SPINLOCK(ddrpll_lock
);
72 static DEFINE_SPINLOCK(iopll_lock
);
73 static DEFINE_SPINLOCK(armclk_lock
);
74 static DEFINE_SPINLOCK(swdtclk_lock
);
75 static DEFINE_SPINLOCK(ddrclk_lock
);
76 static DEFINE_SPINLOCK(dciclk_lock
);
77 static DEFINE_SPINLOCK(gem0clk_lock
);
78 static DEFINE_SPINLOCK(gem1clk_lock
);
79 static DEFINE_SPINLOCK(canclk_lock
);
80 static DEFINE_SPINLOCK(canmioclk_lock
);
81 static DEFINE_SPINLOCK(dbgclk_lock
);
82 static DEFINE_SPINLOCK(aperclk_lock
);
84 static const char dummy_nm
[] __initconst
= "dummy_name";
86 static const char *armpll_parents
[] __initdata
= {"armpll_int", "ps_clk"};
87 static const char *ddrpll_parents
[] __initdata
= {"ddrpll_int", "ps_clk"};
88 static const char *iopll_parents
[] __initdata
= {"iopll_int", "ps_clk"};
89 static const char *gem0_mux_parents
[] __initdata
= {"gem0_div1", dummy_nm
};
90 static const char *gem1_mux_parents
[] __initdata
= {"gem1_div1", dummy_nm
};
91 static const char *can0_mio_mux2_parents
[] __initdata
= {"can0_gate",
93 static const char *can1_mio_mux2_parents
[] __initdata
= {"can1_gate",
95 static const char *dbg_emio_mux_parents
[] __initdata
= {"dbg_div",
98 static const char *dbgtrc_emio_input_names
[] __initdata
= {"trace_emio_clk"};
99 static const char *gem0_emio_input_names
[] __initdata
= {"gem0_emio_clk"};
100 static const char *gem1_emio_input_names
[] __initdata
= {"gem1_emio_clk"};
101 static const char *swdt_ext_clk_input_names
[] __initdata
= {"swdt_ext_clk"};
103 static void __init
zynq_clk_register_fclk(enum zynq_clk fclk
,
104 const char *clk_name
, void __iomem
*fclk_ctrl_reg
,
105 const char **parents
)
111 spinlock_t
*fclk_lock
;
112 spinlock_t
*fclk_gate_lock
;
113 void __iomem
*fclk_gate_reg
= fclk_ctrl_reg
+ 8;
115 fclk_lock
= kmalloc(sizeof(*fclk_lock
), GFP_KERNEL
);
118 fclk_gate_lock
= kmalloc(sizeof(*fclk_gate_lock
), GFP_KERNEL
);
121 spin_lock_init(fclk_lock
);
122 spin_lock_init(fclk_gate_lock
);
124 mux_name
= kasprintf(GFP_KERNEL
, "%s_mux", clk_name
);
125 div0_name
= kasprintf(GFP_KERNEL
, "%s_div0", clk_name
);
126 div1_name
= kasprintf(GFP_KERNEL
, "%s_div1", clk_name
);
128 clk
= clk_register_mux(NULL
, mux_name
, parents
, 4, 0,
129 fclk_ctrl_reg
, 4, 2, 0, fclk_lock
);
131 clk
= clk_register_divider(NULL
, div0_name
, mux_name
,
132 0, fclk_ctrl_reg
, 8, 6, CLK_DIVIDER_ONE_BASED
|
133 CLK_DIVIDER_ALLOW_ZERO
, fclk_lock
);
135 clk
= clk_register_divider(NULL
, div1_name
, div0_name
,
136 CLK_SET_RATE_PARENT
, fclk_ctrl_reg
, 20, 6,
137 CLK_DIVIDER_ONE_BASED
| CLK_DIVIDER_ALLOW_ZERO
,
140 clks
[fclk
] = clk_register_gate(NULL
, clk_name
,
141 div1_name
, CLK_SET_RATE_PARENT
, fclk_gate_reg
,
142 0, CLK_GATE_SET_TO_DISABLE
, fclk_gate_lock
);
150 clks
[fclk
] = ERR_PTR(-ENOMEM
);
153 static void __init
zynq_clk_register_periph_clk(enum zynq_clk clk0
,
154 enum zynq_clk clk1
, const char *clk_name0
,
155 const char *clk_name1
, void __iomem
*clk_ctrl
,
156 const char **parents
, unsigned int two_gates
)
163 lock
= kmalloc(sizeof(*lock
), GFP_KERNEL
);
166 spin_lock_init(lock
);
168 mux_name
= kasprintf(GFP_KERNEL
, "%s_mux", clk_name0
);
169 div_name
= kasprintf(GFP_KERNEL
, "%s_div", clk_name0
);
171 clk
= clk_register_mux(NULL
, mux_name
, parents
, 4, 0,
172 clk_ctrl
, 4, 2, 0, lock
);
174 clk
= clk_register_divider(NULL
, div_name
, mux_name
, 0, clk_ctrl
, 8, 6,
175 CLK_DIVIDER_ONE_BASED
| CLK_DIVIDER_ALLOW_ZERO
, lock
);
177 clks
[clk0
] = clk_register_gate(NULL
, clk_name0
, div_name
,
178 CLK_SET_RATE_PARENT
, clk_ctrl
, 0, 0, lock
);
180 clks
[clk1
] = clk_register_gate(NULL
, clk_name1
, div_name
,
181 CLK_SET_RATE_PARENT
, clk_ctrl
, 1, 0, lock
);
189 clks
[clk0
] = ERR_PTR(-ENOMEM
);
191 clks
[clk1
] = ERR_PTR(-ENOMEM
);
194 static void __init
zynq_clk_setup(struct device_node
*np
)
201 const char *clk_output_name
[clk_max
];
202 const char *cpu_parents
[4];
203 const char *periph_parents
[4];
204 const char *swdt_ext_clk_mux_parents
[2];
205 const char *can_mio_mux_parents
[NUM_MIO_PINS
];
207 pr_info("Zynq clock init\n");
209 /* get clock output names from DT */
210 for (i
= 0; i
< clk_max
; i
++) {
211 if (of_property_read_string_index(np
, "clock-output-names",
212 i
, &clk_output_name
[i
])) {
213 pr_err("%s: clock output name not in DT\n", __func__
);
217 cpu_parents
[0] = clk_output_name
[armpll
];
218 cpu_parents
[1] = clk_output_name
[armpll
];
219 cpu_parents
[2] = clk_output_name
[ddrpll
];
220 cpu_parents
[3] = clk_output_name
[iopll
];
221 periph_parents
[0] = clk_output_name
[iopll
];
222 periph_parents
[1] = clk_output_name
[iopll
];
223 periph_parents
[2] = clk_output_name
[armpll
];
224 periph_parents
[3] = clk_output_name
[ddrpll
];
227 ret
= of_property_read_u32(np
, "ps-clk-frequency", &tmp
);
229 pr_warn("ps_clk frequency not specified, using 33 MHz.\n");
232 ps_clk
= clk_register_fixed_rate(NULL
, "ps_clk", NULL
, CLK_IS_ROOT
,
236 clk
= clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL
,
237 SLCR_PLL_STATUS
, 0, &armpll_lock
);
238 clks
[armpll
] = clk_register_mux(NULL
, clk_output_name
[armpll
],
239 armpll_parents
, 2, 0, SLCR_ARMPLL_CTRL
, 4, 1, 0,
242 clk
= clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL
,
243 SLCR_PLL_STATUS
, 1, &ddrpll_lock
);
244 clks
[ddrpll
] = clk_register_mux(NULL
, clk_output_name
[ddrpll
],
245 ddrpll_parents
, 2, 0, SLCR_DDRPLL_CTRL
, 4, 1, 0,
248 clk
= clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL
,
249 SLCR_PLL_STATUS
, 2, &iopll_lock
);
250 clks
[iopll
] = clk_register_mux(NULL
, clk_output_name
[iopll
],
251 iopll_parents
, 2, 0, SLCR_IOPLL_CTRL
, 4, 1, 0,
255 tmp
= readl(SLCR_621_TRUE
) & 1;
256 clk
= clk_register_mux(NULL
, "cpu_mux", cpu_parents
, 4, 0,
257 SLCR_ARM_CLK_CTRL
, 4, 2, 0, &armclk_lock
);
258 clk
= clk_register_divider(NULL
, "cpu_div", "cpu_mux", 0,
259 SLCR_ARM_CLK_CTRL
, 8, 6, CLK_DIVIDER_ONE_BASED
|
260 CLK_DIVIDER_ALLOW_ZERO
, &armclk_lock
);
262 clks
[cpu_6or4x
] = clk_register_gate(NULL
, clk_output_name
[cpu_6or4x
],
263 "cpu_div", CLK_SET_RATE_PARENT
| CLK_IGNORE_UNUSED
,
264 SLCR_ARM_CLK_CTRL
, 24, 0, &armclk_lock
);
266 clk
= clk_register_fixed_factor(NULL
, "cpu_3or2x_div", "cpu_div", 0,
268 clks
[cpu_3or2x
] = clk_register_gate(NULL
, clk_output_name
[cpu_3or2x
],
269 "cpu_3or2x_div", CLK_IGNORE_UNUSED
,
270 SLCR_ARM_CLK_CTRL
, 25, 0, &armclk_lock
);
272 clk
= clk_register_fixed_factor(NULL
, "cpu_2x_div", "cpu_div", 0, 1,
274 clks
[cpu_2x
] = clk_register_gate(NULL
, clk_output_name
[cpu_2x
],
275 "cpu_2x_div", CLK_IGNORE_UNUSED
, SLCR_ARM_CLK_CTRL
,
276 26, 0, &armclk_lock
);
278 clk
= clk_register_fixed_factor(NULL
, "cpu_1x_div", "cpu_div", 0, 1,
280 clks
[cpu_1x
] = clk_register_gate(NULL
, clk_output_name
[cpu_1x
],
281 "cpu_1x_div", CLK_IGNORE_UNUSED
, SLCR_ARM_CLK_CTRL
, 27,
285 swdt_ext_clk_mux_parents
[0] = clk_output_name
[cpu_1x
];
286 for (i
= 0; i
< ARRAY_SIZE(swdt_ext_clk_input_names
); i
++) {
287 int idx
= of_property_match_string(np
, "clock-names",
288 swdt_ext_clk_input_names
[i
]);
290 swdt_ext_clk_mux_parents
[i
+ 1] =
291 of_clk_get_parent_name(np
, idx
);
293 swdt_ext_clk_mux_parents
[i
+ 1] = dummy_nm
;
295 clks
[swdt
] = clk_register_mux(NULL
, clk_output_name
[swdt
],
296 swdt_ext_clk_mux_parents
, 2, CLK_SET_RATE_PARENT
,
297 SLCR_SWDT_CLK_SEL
, 0, 1, 0, &swdtclk_lock
);
300 clk
= clk_register_divider(NULL
, "ddr2x_div", "ddrpll", 0,
301 SLCR_DDR_CLK_CTRL
, 26, 6, CLK_DIVIDER_ONE_BASED
|
302 CLK_DIVIDER_ALLOW_ZERO
, &ddrclk_lock
);
303 clks
[ddr2x
] = clk_register_gate(NULL
, clk_output_name
[ddr2x
],
304 "ddr2x_div", 0, SLCR_DDR_CLK_CTRL
, 1, 0, &ddrclk_lock
);
305 clk_prepare_enable(clks
[ddr2x
]);
306 clk
= clk_register_divider(NULL
, "ddr3x_div", "ddrpll", 0,
307 SLCR_DDR_CLK_CTRL
, 20, 6, CLK_DIVIDER_ONE_BASED
|
308 CLK_DIVIDER_ALLOW_ZERO
, &ddrclk_lock
);
309 clks
[ddr3x
] = clk_register_gate(NULL
, clk_output_name
[ddr3x
],
310 "ddr3x_div", 0, SLCR_DDR_CLK_CTRL
, 0, 0, &ddrclk_lock
);
311 clk_prepare_enable(clks
[ddr3x
]);
313 clk
= clk_register_divider(NULL
, "dci_div0", "ddrpll", 0,
314 SLCR_DCI_CLK_CTRL
, 8, 6, CLK_DIVIDER_ONE_BASED
|
315 CLK_DIVIDER_ALLOW_ZERO
, &dciclk_lock
);
316 clk
= clk_register_divider(NULL
, "dci_div1", "dci_div0",
317 CLK_SET_RATE_PARENT
, SLCR_DCI_CLK_CTRL
, 20, 6,
318 CLK_DIVIDER_ONE_BASED
| CLK_DIVIDER_ALLOW_ZERO
,
320 clks
[dci
] = clk_register_gate(NULL
, clk_output_name
[dci
], "dci_div1",
321 CLK_SET_RATE_PARENT
, SLCR_DCI_CLK_CTRL
, 0, 0,
323 clk_prepare_enable(clks
[dci
]);
325 /* Peripheral clocks */
326 for (i
= fclk0
; i
<= fclk3
; i
++)
327 zynq_clk_register_fclk(i
, clk_output_name
[i
],
328 SLCR_FPGA0_CLK_CTRL
+ 0x10 * (i
- fclk0
),
331 zynq_clk_register_periph_clk(lqspi
, 0, clk_output_name
[lqspi
], NULL
,
332 SLCR_LQSPI_CLK_CTRL
, periph_parents
, 0);
334 zynq_clk_register_periph_clk(smc
, 0, clk_output_name
[smc
], NULL
,
335 SLCR_SMC_CLK_CTRL
, periph_parents
, 0);
337 zynq_clk_register_periph_clk(pcap
, 0, clk_output_name
[pcap
], NULL
,
338 SLCR_PCAP_CLK_CTRL
, periph_parents
, 0);
340 zynq_clk_register_periph_clk(sdio0
, sdio1
, clk_output_name
[sdio0
],
341 clk_output_name
[sdio1
], SLCR_SDIO_CLK_CTRL
,
344 zynq_clk_register_periph_clk(uart0
, uart1
, clk_output_name
[uart0
],
345 clk_output_name
[uart1
], SLCR_UART_CLK_CTRL
,
348 zynq_clk_register_periph_clk(spi0
, spi1
, clk_output_name
[spi0
],
349 clk_output_name
[spi1
], SLCR_SPI_CLK_CTRL
,
352 for (i
= 0; i
< ARRAY_SIZE(gem0_emio_input_names
); i
++) {
353 int idx
= of_property_match_string(np
, "clock-names",
354 gem0_emio_input_names
[i
]);
356 gem0_mux_parents
[i
+ 1] = of_clk_get_parent_name(np
,
359 clk
= clk_register_mux(NULL
, "gem0_mux", periph_parents
, 4, 0,
360 SLCR_GEM0_CLK_CTRL
, 4, 2, 0, &gem0clk_lock
);
361 clk
= clk_register_divider(NULL
, "gem0_div0", "gem0_mux", 0,
362 SLCR_GEM0_CLK_CTRL
, 8, 6, CLK_DIVIDER_ONE_BASED
|
363 CLK_DIVIDER_ALLOW_ZERO
, &gem0clk_lock
);
364 clk
= clk_register_divider(NULL
, "gem0_div1", "gem0_div0",
365 CLK_SET_RATE_PARENT
, SLCR_GEM0_CLK_CTRL
, 20, 6,
366 CLK_DIVIDER_ONE_BASED
| CLK_DIVIDER_ALLOW_ZERO
,
368 clk
= clk_register_mux(NULL
, "gem0_emio_mux", gem0_mux_parents
, 2,
369 CLK_SET_RATE_PARENT
, SLCR_GEM0_CLK_CTRL
, 6, 1, 0,
371 clks
[gem0
] = clk_register_gate(NULL
, clk_output_name
[gem0
],
372 "gem0_emio_mux", CLK_SET_RATE_PARENT
,
373 SLCR_GEM0_CLK_CTRL
, 0, 0, &gem0clk_lock
);
375 for (i
= 0; i
< ARRAY_SIZE(gem1_emio_input_names
); i
++) {
376 int idx
= of_property_match_string(np
, "clock-names",
377 gem1_emio_input_names
[i
]);
379 gem1_mux_parents
[i
+ 1] = of_clk_get_parent_name(np
,
382 clk
= clk_register_mux(NULL
, "gem1_mux", periph_parents
, 4, 0,
383 SLCR_GEM1_CLK_CTRL
, 4, 2, 0, &gem1clk_lock
);
384 clk
= clk_register_divider(NULL
, "gem1_div0", "gem1_mux", 0,
385 SLCR_GEM1_CLK_CTRL
, 8, 6, CLK_DIVIDER_ONE_BASED
|
386 CLK_DIVIDER_ALLOW_ZERO
, &gem1clk_lock
);
387 clk
= clk_register_divider(NULL
, "gem1_div1", "gem1_div0",
388 CLK_SET_RATE_PARENT
, SLCR_GEM1_CLK_CTRL
, 20, 6,
389 CLK_DIVIDER_ONE_BASED
| CLK_DIVIDER_ALLOW_ZERO
,
391 clk
= clk_register_mux(NULL
, "gem1_emio_mux", gem1_mux_parents
, 2,
392 CLK_SET_RATE_PARENT
, SLCR_GEM1_CLK_CTRL
, 6, 1, 0,
394 clks
[gem1
] = clk_register_gate(NULL
, clk_output_name
[gem1
],
395 "gem1_emio_mux", CLK_SET_RATE_PARENT
,
396 SLCR_GEM1_CLK_CTRL
, 0, 0, &gem1clk_lock
);
398 tmp
= strlen("mio_clk_00x");
399 clk_name
= kmalloc(tmp
, GFP_KERNEL
);
400 for (i
= 0; i
< NUM_MIO_PINS
; i
++) {
403 snprintf(clk_name
, tmp
, "mio_clk_%2.2d", i
);
404 idx
= of_property_match_string(np
, "clock-names", clk_name
);
406 can_mio_mux_parents
[i
] = of_clk_get_parent_name(np
,
409 can_mio_mux_parents
[i
] = dummy_nm
;
412 clk
= clk_register_mux(NULL
, "can_mux", periph_parents
, 4, 0,
413 SLCR_CAN_CLK_CTRL
, 4, 2, 0, &canclk_lock
);
414 clk
= clk_register_divider(NULL
, "can_div0", "can_mux", 0,
415 SLCR_CAN_CLK_CTRL
, 8, 6, CLK_DIVIDER_ONE_BASED
|
416 CLK_DIVIDER_ALLOW_ZERO
, &canclk_lock
);
417 clk
= clk_register_divider(NULL
, "can_div1", "can_div0",
418 CLK_SET_RATE_PARENT
, SLCR_CAN_CLK_CTRL
, 20, 6,
419 CLK_DIVIDER_ONE_BASED
| CLK_DIVIDER_ALLOW_ZERO
,
421 clk
= clk_register_gate(NULL
, "can0_gate", "can_div1",
422 CLK_SET_RATE_PARENT
, SLCR_CAN_CLK_CTRL
, 0, 0,
424 clk
= clk_register_gate(NULL
, "can1_gate", "can_div1",
425 CLK_SET_RATE_PARENT
, SLCR_CAN_CLK_CTRL
, 1, 0,
427 clk
= clk_register_mux(NULL
, "can0_mio_mux",
428 can_mio_mux_parents
, 54, CLK_SET_RATE_PARENT
,
429 SLCR_CAN_MIOCLK_CTRL
, 0, 6, 0, &canmioclk_lock
);
430 clk
= clk_register_mux(NULL
, "can1_mio_mux",
431 can_mio_mux_parents
, 54, CLK_SET_RATE_PARENT
,
432 SLCR_CAN_MIOCLK_CTRL
, 16, 6, 0, &canmioclk_lock
);
433 clks
[can0
] = clk_register_mux(NULL
, clk_output_name
[can0
],
434 can0_mio_mux2_parents
, 2, CLK_SET_RATE_PARENT
,
435 SLCR_CAN_MIOCLK_CTRL
, 6, 1, 0, &canmioclk_lock
);
436 clks
[can1
] = clk_register_mux(NULL
, clk_output_name
[can1
],
437 can1_mio_mux2_parents
, 2, CLK_SET_RATE_PARENT
,
438 SLCR_CAN_MIOCLK_CTRL
, 22, 1, 0, &canmioclk_lock
);
440 for (i
= 0; i
< ARRAY_SIZE(dbgtrc_emio_input_names
); i
++) {
441 int idx
= of_property_match_string(np
, "clock-names",
442 dbgtrc_emio_input_names
[i
]);
444 dbg_emio_mux_parents
[i
+ 1] = of_clk_get_parent_name(np
,
447 clk
= clk_register_mux(NULL
, "dbg_mux", periph_parents
, 4, 0,
448 SLCR_DBG_CLK_CTRL
, 4, 2, 0, &dbgclk_lock
);
449 clk
= clk_register_divider(NULL
, "dbg_div", "dbg_mux", 0,
450 SLCR_DBG_CLK_CTRL
, 8, 6, CLK_DIVIDER_ONE_BASED
|
451 CLK_DIVIDER_ALLOW_ZERO
, &dbgclk_lock
);
452 clk
= clk_register_mux(NULL
, "dbg_emio_mux", dbg_emio_mux_parents
, 2, 0,
453 SLCR_DBG_CLK_CTRL
, 6, 1, 0, &dbgclk_lock
);
454 clks
[dbg_trc
] = clk_register_gate(NULL
, clk_output_name
[dbg_trc
],
455 "dbg_emio_mux", CLK_SET_RATE_PARENT
, SLCR_DBG_CLK_CTRL
,
457 clks
[dbg_apb
] = clk_register_gate(NULL
, clk_output_name
[dbg_apb
],
458 clk_output_name
[cpu_1x
], 0, SLCR_DBG_CLK_CTRL
, 1, 0,
461 /* One gated clock for all APER clocks. */
462 clks
[dma
] = clk_register_gate(NULL
, clk_output_name
[dma
],
463 clk_output_name
[cpu_2x
], 0, SLCR_APER_CLK_CTRL
, 0, 0,
465 clks
[usb0_aper
] = clk_register_gate(NULL
, clk_output_name
[usb0_aper
],
466 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 2, 0,
468 clks
[usb1_aper
] = clk_register_gate(NULL
, clk_output_name
[usb1_aper
],
469 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 3, 0,
471 clks
[gem0_aper
] = clk_register_gate(NULL
, clk_output_name
[gem0_aper
],
472 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 6, 0,
474 clks
[gem1_aper
] = clk_register_gate(NULL
, clk_output_name
[gem1_aper
],
475 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 7, 0,
477 clks
[sdio0_aper
] = clk_register_gate(NULL
, clk_output_name
[sdio0_aper
],
478 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 10, 0,
480 clks
[sdio1_aper
] = clk_register_gate(NULL
, clk_output_name
[sdio1_aper
],
481 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 11, 0,
483 clks
[spi0_aper
] = clk_register_gate(NULL
, clk_output_name
[spi0_aper
],
484 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 14, 0,
486 clks
[spi1_aper
] = clk_register_gate(NULL
, clk_output_name
[spi1_aper
],
487 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 15, 0,
489 clks
[can0_aper
] = clk_register_gate(NULL
, clk_output_name
[can0_aper
],
490 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 16, 0,
492 clks
[can1_aper
] = clk_register_gate(NULL
, clk_output_name
[can1_aper
],
493 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 17, 0,
495 clks
[i2c0_aper
] = clk_register_gate(NULL
, clk_output_name
[i2c0_aper
],
496 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 18, 0,
498 clks
[i2c1_aper
] = clk_register_gate(NULL
, clk_output_name
[i2c1_aper
],
499 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 19, 0,
501 clks
[uart0_aper
] = clk_register_gate(NULL
, clk_output_name
[uart0_aper
],
502 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 20, 0,
504 clks
[uart1_aper
] = clk_register_gate(NULL
, clk_output_name
[uart1_aper
],
505 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 21, 0,
507 clks
[gpio_aper
] = clk_register_gate(NULL
, clk_output_name
[gpio_aper
],
508 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 22, 0,
510 clks
[lqspi_aper
] = clk_register_gate(NULL
, clk_output_name
[lqspi_aper
],
511 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 23, 0,
513 clks
[smc_aper
] = clk_register_gate(NULL
, clk_output_name
[smc_aper
],
514 clk_output_name
[cpu_1x
], 0, SLCR_APER_CLK_CTRL
, 24, 0,
517 for (i
= 0; i
< ARRAY_SIZE(clks
); i
++) {
518 if (IS_ERR(clks
[i
])) {
519 pr_err("Zynq clk %d: register failed with %ld\n",
520 i
, PTR_ERR(clks
[i
]));
525 clk_data
.clks
= clks
;
526 clk_data
.clk_num
= ARRAY_SIZE(clks
);
527 of_clk_add_provider(np
, of_clk_src_onecell_get
, &clk_data
);
530 CLK_OF_DECLARE(zynq_clkc
, "xlnx,ps7-clkc", zynq_clk_setup
);
532 void __init
zynq_clock_init(void __iomem
*slcr_base
)
534 zynq_slcr_base_priv
= slcr_base
;