1 /* linux/arch/arm/mach-exynos4/mct.c
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * EXYNOS4 MCT(Multi-Core Timer) support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/sched.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/clockchips.h>
19 #include <linux/cpu.h>
20 #include <linux/platform_device.h>
21 #include <linux/delay.h>
22 #include <linux/percpu.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_address.h>
26 #include <linux/clocksource.h>
27 #include <linux/sched_clock.h>
29 #define EXYNOS4_MCTREG(x) (x)
30 #define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
31 #define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
32 #define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
33 #define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
34 #define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
35 #define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
36 #define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
37 #define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
38 #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
39 #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
40 #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
41 #define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
42 #define EXYNOS4_MCT_L_MASK (0xffffff00)
44 #define MCT_L_TCNTB_OFFSET (0x00)
45 #define MCT_L_ICNTB_OFFSET (0x08)
46 #define MCT_L_TCON_OFFSET (0x20)
47 #define MCT_L_INT_CSTAT_OFFSET (0x30)
48 #define MCT_L_INT_ENB_OFFSET (0x34)
49 #define MCT_L_WSTAT_OFFSET (0x40)
50 #define MCT_G_TCON_START (1 << 8)
51 #define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
52 #define MCT_G_TCON_COMP0_ENABLE (1 << 0)
53 #define MCT_L_TCON_INTERVAL_MODE (1 << 2)
54 #define MCT_L_TCON_INT_START (1 << 1)
55 #define MCT_L_TCON_TIMER_START (1 << 0)
57 #define TICK_BASE_CNT 1
80 static void __iomem
*reg_base
;
81 static unsigned long clk_rate
;
82 static unsigned int mct_int_type
;
83 static int mct_irqs
[MCT_NR_IRQS
];
85 struct mct_clock_event_device
{
86 struct clock_event_device evt
;
91 static void exynos4_mct_write(unsigned int value
, unsigned long offset
)
93 unsigned long stat_addr
;
97 __raw_writel(value
, reg_base
+ offset
);
99 if (likely(offset
>= EXYNOS4_MCT_L_BASE(0))) {
100 stat_addr
= (offset
& ~EXYNOS4_MCT_L_MASK
) + MCT_L_WSTAT_OFFSET
;
101 switch (offset
& EXYNOS4_MCT_L_MASK
) {
102 case MCT_L_TCON_OFFSET
:
103 mask
= 1 << 3; /* L_TCON write status */
105 case MCT_L_ICNTB_OFFSET
:
106 mask
= 1 << 1; /* L_ICNTB write status */
108 case MCT_L_TCNTB_OFFSET
:
109 mask
= 1 << 0; /* L_TCNTB write status */
116 case EXYNOS4_MCT_G_TCON
:
117 stat_addr
= EXYNOS4_MCT_G_WSTAT
;
118 mask
= 1 << 16; /* G_TCON write status */
120 case EXYNOS4_MCT_G_COMP0_L
:
121 stat_addr
= EXYNOS4_MCT_G_WSTAT
;
122 mask
= 1 << 0; /* G_COMP0_L write status */
124 case EXYNOS4_MCT_G_COMP0_U
:
125 stat_addr
= EXYNOS4_MCT_G_WSTAT
;
126 mask
= 1 << 1; /* G_COMP0_U write status */
128 case EXYNOS4_MCT_G_COMP0_ADD_INCR
:
129 stat_addr
= EXYNOS4_MCT_G_WSTAT
;
130 mask
= 1 << 2; /* G_COMP0_ADD_INCR w status */
132 case EXYNOS4_MCT_G_CNT_L
:
133 stat_addr
= EXYNOS4_MCT_G_CNT_WSTAT
;
134 mask
= 1 << 0; /* G_CNT_L write status */
136 case EXYNOS4_MCT_G_CNT_U
:
137 stat_addr
= EXYNOS4_MCT_G_CNT_WSTAT
;
138 mask
= 1 << 1; /* G_CNT_U write status */
145 /* Wait maximum 1 ms until written values are applied */
146 for (i
= 0; i
< loops_per_jiffy
/ 1000 * HZ
; i
++)
147 if (__raw_readl(reg_base
+ stat_addr
) & mask
) {
148 __raw_writel(mask
, reg_base
+ stat_addr
);
152 panic("MCT hangs after writing %d (offset:0x%lx)\n", value
, offset
);
155 /* Clocksource handling */
156 static void exynos4_mct_frc_start(void)
160 reg
= __raw_readl(reg_base
+ EXYNOS4_MCT_G_TCON
);
161 reg
|= MCT_G_TCON_START
;
162 exynos4_mct_write(reg
, EXYNOS4_MCT_G_TCON
);
165 static cycle_t notrace
_exynos4_frc_read(void)
168 u32 hi2
= __raw_readl(reg_base
+ EXYNOS4_MCT_G_CNT_U
);
172 lo
= __raw_readl(reg_base
+ EXYNOS4_MCT_G_CNT_L
);
173 hi2
= __raw_readl(reg_base
+ EXYNOS4_MCT_G_CNT_U
);
176 return ((cycle_t
)hi
<< 32) | lo
;
179 static cycle_t
exynos4_frc_read(struct clocksource
*cs
)
181 return _exynos4_frc_read();
184 static void exynos4_frc_resume(struct clocksource
*cs
)
186 exynos4_mct_frc_start();
189 struct clocksource mct_frc
= {
192 .read
= exynos4_frc_read
,
193 .mask
= CLOCKSOURCE_MASK(64),
194 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
195 .resume
= exynos4_frc_resume
,
198 static u64 notrace
exynos4_read_sched_clock(void)
200 return _exynos4_frc_read();
203 static struct delay_timer exynos4_delay_timer
;
205 static cycles_t
exynos4_read_current_timer(void)
207 return _exynos4_frc_read();
210 static void __init
exynos4_clocksource_init(void)
212 exynos4_mct_frc_start();
214 exynos4_delay_timer
.read_current_timer
= &exynos4_read_current_timer
;
215 exynos4_delay_timer
.freq
= clk_rate
;
216 register_current_timer_delay(&exynos4_delay_timer
);
218 if (clocksource_register_hz(&mct_frc
, clk_rate
))
219 panic("%s: can't register clocksource\n", mct_frc
.name
);
221 sched_clock_register(exynos4_read_sched_clock
, 64, clk_rate
);
224 static void exynos4_mct_comp0_stop(void)
228 tcon
= __raw_readl(reg_base
+ EXYNOS4_MCT_G_TCON
);
229 tcon
&= ~(MCT_G_TCON_COMP0_ENABLE
| MCT_G_TCON_COMP0_AUTO_INC
);
231 exynos4_mct_write(tcon
, EXYNOS4_MCT_G_TCON
);
232 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB
);
235 static void exynos4_mct_comp0_start(enum clock_event_mode mode
,
236 unsigned long cycles
)
241 tcon
= __raw_readl(reg_base
+ EXYNOS4_MCT_G_TCON
);
243 if (mode
== CLOCK_EVT_MODE_PERIODIC
) {
244 tcon
|= MCT_G_TCON_COMP0_AUTO_INC
;
245 exynos4_mct_write(cycles
, EXYNOS4_MCT_G_COMP0_ADD_INCR
);
248 comp_cycle
= exynos4_frc_read(&mct_frc
) + cycles
;
249 exynos4_mct_write((u32
)comp_cycle
, EXYNOS4_MCT_G_COMP0_L
);
250 exynos4_mct_write((u32
)(comp_cycle
>> 32), EXYNOS4_MCT_G_COMP0_U
);
252 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB
);
254 tcon
|= MCT_G_TCON_COMP0_ENABLE
;
255 exynos4_mct_write(tcon
, EXYNOS4_MCT_G_TCON
);
258 static int exynos4_comp_set_next_event(unsigned long cycles
,
259 struct clock_event_device
*evt
)
261 exynos4_mct_comp0_start(evt
->mode
, cycles
);
266 static void exynos4_comp_set_mode(enum clock_event_mode mode
,
267 struct clock_event_device
*evt
)
269 unsigned long cycles_per_jiffy
;
270 exynos4_mct_comp0_stop();
273 case CLOCK_EVT_MODE_PERIODIC
:
275 (((unsigned long long) NSEC_PER_SEC
/ HZ
* evt
->mult
) >> evt
->shift
);
276 exynos4_mct_comp0_start(mode
, cycles_per_jiffy
);
279 case CLOCK_EVT_MODE_ONESHOT
:
280 case CLOCK_EVT_MODE_UNUSED
:
281 case CLOCK_EVT_MODE_SHUTDOWN
:
282 case CLOCK_EVT_MODE_RESUME
:
287 static struct clock_event_device mct_comp_device
= {
289 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
,
291 .set_next_event
= exynos4_comp_set_next_event
,
292 .set_mode
= exynos4_comp_set_mode
,
295 static irqreturn_t
exynos4_mct_comp_isr(int irq
, void *dev_id
)
297 struct clock_event_device
*evt
= dev_id
;
299 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT
);
301 evt
->event_handler(evt
);
306 static struct irqaction mct_comp_event_irq
= {
307 .name
= "mct_comp_irq",
308 .flags
= IRQF_TIMER
| IRQF_IRQPOLL
,
309 .handler
= exynos4_mct_comp_isr
,
310 .dev_id
= &mct_comp_device
,
313 static void exynos4_clockevent_init(void)
315 mct_comp_device
.cpumask
= cpumask_of(0);
316 clockevents_config_and_register(&mct_comp_device
, clk_rate
,
318 setup_irq(mct_irqs
[MCT_G0_IRQ
], &mct_comp_event_irq
);
321 static DEFINE_PER_CPU(struct mct_clock_event_device
, percpu_mct_tick
);
323 /* Clock event handling */
324 static void exynos4_mct_tick_stop(struct mct_clock_event_device
*mevt
)
327 unsigned long mask
= MCT_L_TCON_INT_START
| MCT_L_TCON_TIMER_START
;
328 unsigned long offset
= mevt
->base
+ MCT_L_TCON_OFFSET
;
330 tmp
= __raw_readl(reg_base
+ offset
);
333 exynos4_mct_write(tmp
, offset
);
337 static void exynos4_mct_tick_start(unsigned long cycles
,
338 struct mct_clock_event_device
*mevt
)
342 exynos4_mct_tick_stop(mevt
);
344 tmp
= (1 << 31) | cycles
; /* MCT_L_UPDATE_ICNTB */
346 /* update interrupt count buffer */
347 exynos4_mct_write(tmp
, mevt
->base
+ MCT_L_ICNTB_OFFSET
);
349 /* enable MCT tick interrupt */
350 exynos4_mct_write(0x1, mevt
->base
+ MCT_L_INT_ENB_OFFSET
);
352 tmp
= __raw_readl(reg_base
+ mevt
->base
+ MCT_L_TCON_OFFSET
);
353 tmp
|= MCT_L_TCON_INT_START
| MCT_L_TCON_TIMER_START
|
354 MCT_L_TCON_INTERVAL_MODE
;
355 exynos4_mct_write(tmp
, mevt
->base
+ MCT_L_TCON_OFFSET
);
358 static int exynos4_tick_set_next_event(unsigned long cycles
,
359 struct clock_event_device
*evt
)
361 struct mct_clock_event_device
*mevt
= this_cpu_ptr(&percpu_mct_tick
);
363 exynos4_mct_tick_start(cycles
, mevt
);
368 static inline void exynos4_tick_set_mode(enum clock_event_mode mode
,
369 struct clock_event_device
*evt
)
371 struct mct_clock_event_device
*mevt
= this_cpu_ptr(&percpu_mct_tick
);
372 unsigned long cycles_per_jiffy
;
374 exynos4_mct_tick_stop(mevt
);
377 case CLOCK_EVT_MODE_PERIODIC
:
379 (((unsigned long long) NSEC_PER_SEC
/ HZ
* evt
->mult
) >> evt
->shift
);
380 exynos4_mct_tick_start(cycles_per_jiffy
, mevt
);
383 case CLOCK_EVT_MODE_ONESHOT
:
384 case CLOCK_EVT_MODE_UNUSED
:
385 case CLOCK_EVT_MODE_SHUTDOWN
:
386 case CLOCK_EVT_MODE_RESUME
:
391 static int exynos4_mct_tick_clear(struct mct_clock_event_device
*mevt
)
393 struct clock_event_device
*evt
= &mevt
->evt
;
396 * This is for supporting oneshot mode.
397 * Mct would generate interrupt periodically
398 * without explicit stopping.
400 if (evt
->mode
!= CLOCK_EVT_MODE_PERIODIC
)
401 exynos4_mct_tick_stop(mevt
);
403 /* Clear the MCT tick interrupt */
404 if (__raw_readl(reg_base
+ mevt
->base
+ MCT_L_INT_CSTAT_OFFSET
) & 1) {
405 exynos4_mct_write(0x1, mevt
->base
+ MCT_L_INT_CSTAT_OFFSET
);
412 static irqreturn_t
exynos4_mct_tick_isr(int irq
, void *dev_id
)
414 struct mct_clock_event_device
*mevt
= dev_id
;
415 struct clock_event_device
*evt
= &mevt
->evt
;
417 exynos4_mct_tick_clear(mevt
);
419 evt
->event_handler(evt
);
424 static int exynos4_local_timer_setup(struct clock_event_device
*evt
)
426 struct mct_clock_event_device
*mevt
;
427 unsigned int cpu
= smp_processor_id();
429 mevt
= container_of(evt
, struct mct_clock_event_device
, evt
);
431 mevt
->base
= EXYNOS4_MCT_L_BASE(cpu
);
432 snprintf(mevt
->name
, sizeof(mevt
->name
), "mct_tick%d", cpu
);
434 evt
->name
= mevt
->name
;
435 evt
->cpumask
= cpumask_of(cpu
);
436 evt
->set_next_event
= exynos4_tick_set_next_event
;
437 evt
->set_mode
= exynos4_tick_set_mode
;
438 evt
->features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
;
441 exynos4_mct_write(TICK_BASE_CNT
, mevt
->base
+ MCT_L_TCNTB_OFFSET
);
443 if (mct_int_type
== MCT_INT_SPI
) {
444 evt
->irq
= mct_irqs
[MCT_L0_IRQ
+ cpu
];
445 if (request_irq(evt
->irq
, exynos4_mct_tick_isr
,
446 IRQF_TIMER
| IRQF_NOBALANCING
,
448 pr_err("exynos-mct: cannot register IRQ %d\n",
452 irq_force_affinity(mct_irqs
[MCT_L0_IRQ
+ cpu
], cpumask_of(cpu
));
454 enable_percpu_irq(mct_irqs
[MCT_L0_IRQ
], 0);
456 clockevents_config_and_register(evt
, clk_rate
/ (TICK_BASE_CNT
+ 1),
462 static void exynos4_local_timer_stop(struct clock_event_device
*evt
)
464 evt
->set_mode(CLOCK_EVT_MODE_UNUSED
, evt
);
465 if (mct_int_type
== MCT_INT_SPI
)
466 free_irq(evt
->irq
, this_cpu_ptr(&percpu_mct_tick
));
468 disable_percpu_irq(mct_irqs
[MCT_L0_IRQ
]);
471 static int exynos4_mct_cpu_notify(struct notifier_block
*self
,
472 unsigned long action
, void *hcpu
)
474 struct mct_clock_event_device
*mevt
;
477 * Grab cpu pointer in each case to avoid spurious
478 * preemptible warnings
480 switch (action
& ~CPU_TASKS_FROZEN
) {
482 mevt
= this_cpu_ptr(&percpu_mct_tick
);
483 exynos4_local_timer_setup(&mevt
->evt
);
486 mevt
= this_cpu_ptr(&percpu_mct_tick
);
487 exynos4_local_timer_stop(&mevt
->evt
);
494 static struct notifier_block exynos4_mct_cpu_nb
= {
495 .notifier_call
= exynos4_mct_cpu_notify
,
498 static void __init
exynos4_timer_resources(struct device_node
*np
, void __iomem
*base
)
501 struct mct_clock_event_device
*mevt
= this_cpu_ptr(&percpu_mct_tick
);
502 struct clk
*mct_clk
, *tick_clk
;
504 tick_clk
= np
? of_clk_get_by_name(np
, "fin_pll") :
505 clk_get(NULL
, "fin_pll");
506 if (IS_ERR(tick_clk
))
507 panic("%s: unable to determine tick clock rate\n", __func__
);
508 clk_rate
= clk_get_rate(tick_clk
);
510 mct_clk
= np
? of_clk_get_by_name(np
, "mct") : clk_get(NULL
, "mct");
512 panic("%s: unable to retrieve mct clock instance\n", __func__
);
513 clk_prepare_enable(mct_clk
);
517 panic("%s: unable to ioremap mct address space\n", __func__
);
519 if (mct_int_type
== MCT_INT_PPI
) {
521 err
= request_percpu_irq(mct_irqs
[MCT_L0_IRQ
],
522 exynos4_mct_tick_isr
, "MCT",
524 WARN(err
, "MCT: can't request IRQ %d (%d)\n",
525 mct_irqs
[MCT_L0_IRQ
], err
);
527 irq_set_affinity(mct_irqs
[MCT_L0_IRQ
], cpumask_of(0));
530 err
= register_cpu_notifier(&exynos4_mct_cpu_nb
);
534 /* Immediately configure the timer on the boot CPU */
535 exynos4_local_timer_setup(&mevt
->evt
);
539 free_percpu_irq(mct_irqs
[MCT_L0_IRQ
], &percpu_mct_tick
);
542 void __init
mct_init(void __iomem
*base
, int irq_g0
, int irq_l0
, int irq_l1
)
544 mct_irqs
[MCT_G0_IRQ
] = irq_g0
;
545 mct_irqs
[MCT_L0_IRQ
] = irq_l0
;
546 mct_irqs
[MCT_L1_IRQ
] = irq_l1
;
547 mct_int_type
= MCT_INT_SPI
;
549 exynos4_timer_resources(NULL
, base
);
550 exynos4_clocksource_init();
551 exynos4_clockevent_init();
554 static void __init
mct_init_dt(struct device_node
*np
, unsigned int int_type
)
558 mct_int_type
= int_type
;
560 /* This driver uses only one global timer interrupt */
561 mct_irqs
[MCT_G0_IRQ
] = irq_of_parse_and_map(np
, MCT_G0_IRQ
);
564 * Find out the number of local irqs specified. The local
565 * timer irqs are specified after the four global timer
566 * irqs are specified.
569 nr_irqs
= of_irq_count(np
);
573 for (i
= MCT_L0_IRQ
; i
< nr_irqs
; i
++)
574 mct_irqs
[i
] = irq_of_parse_and_map(np
, i
);
576 exynos4_timer_resources(np
, of_iomap(np
, 0));
577 exynos4_clocksource_init();
578 exynos4_clockevent_init();
582 static void __init
mct_init_spi(struct device_node
*np
)
584 return mct_init_dt(np
, MCT_INT_SPI
);
587 static void __init
mct_init_ppi(struct device_node
*np
)
589 return mct_init_dt(np
, MCT_INT_PPI
);
591 CLOCKSOURCE_OF_DECLARE(exynos4210
, "samsung,exynos4210-mct", mct_init_spi
);
592 CLOCKSOURCE_OF_DECLARE(exynos4412
, "samsung,exynos4412-mct", mct_init_ppi
);