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Merge branch 'fixes' of git://ftp.arm.linux.org.uk/~rmk/linux-arm
[deliverable/linux.git] / drivers / clocksource / exynos_mct.c
1 /* linux/arch/arm/mach-exynos4/mct.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * EXYNOS4 MCT(Multi-Core Timer) support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/sched.h>
14 #include <linux/interrupt.h>
15 #include <linux/irq.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/clockchips.h>
19 #include <linux/cpu.h>
20 #include <linux/platform_device.h>
21 #include <linux/delay.h>
22 #include <linux/percpu.h>
23 #include <linux/of.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_address.h>
26 #include <linux/clocksource.h>
27 #include <linux/sched_clock.h>
28
29 #define EXYNOS4_MCTREG(x) (x)
30 #define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
31 #define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
32 #define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
33 #define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
34 #define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
35 #define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
36 #define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
37 #define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
38 #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
39 #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
40 #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
41 #define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
42 #define EXYNOS4_MCT_L_MASK (0xffffff00)
43
44 #define MCT_L_TCNTB_OFFSET (0x00)
45 #define MCT_L_ICNTB_OFFSET (0x08)
46 #define MCT_L_TCON_OFFSET (0x20)
47 #define MCT_L_INT_CSTAT_OFFSET (0x30)
48 #define MCT_L_INT_ENB_OFFSET (0x34)
49 #define MCT_L_WSTAT_OFFSET (0x40)
50 #define MCT_G_TCON_START (1 << 8)
51 #define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
52 #define MCT_G_TCON_COMP0_ENABLE (1 << 0)
53 #define MCT_L_TCON_INTERVAL_MODE (1 << 2)
54 #define MCT_L_TCON_INT_START (1 << 1)
55 #define MCT_L_TCON_TIMER_START (1 << 0)
56
57 #define TICK_BASE_CNT 1
58
59 enum {
60 MCT_INT_SPI,
61 MCT_INT_PPI
62 };
63
64 enum {
65 MCT_G0_IRQ,
66 MCT_G1_IRQ,
67 MCT_G2_IRQ,
68 MCT_G3_IRQ,
69 MCT_L0_IRQ,
70 MCT_L1_IRQ,
71 MCT_L2_IRQ,
72 MCT_L3_IRQ,
73 MCT_L4_IRQ,
74 MCT_L5_IRQ,
75 MCT_L6_IRQ,
76 MCT_L7_IRQ,
77 MCT_NR_IRQS,
78 };
79
80 static void __iomem *reg_base;
81 static unsigned long clk_rate;
82 static unsigned int mct_int_type;
83 static int mct_irqs[MCT_NR_IRQS];
84
85 struct mct_clock_event_device {
86 struct clock_event_device evt;
87 unsigned long base;
88 char name[10];
89 };
90
91 static void exynos4_mct_write(unsigned int value, unsigned long offset)
92 {
93 unsigned long stat_addr;
94 u32 mask;
95 u32 i;
96
97 __raw_writel(value, reg_base + offset);
98
99 if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
100 stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
101 switch (offset & EXYNOS4_MCT_L_MASK) {
102 case MCT_L_TCON_OFFSET:
103 mask = 1 << 3; /* L_TCON write status */
104 break;
105 case MCT_L_ICNTB_OFFSET:
106 mask = 1 << 1; /* L_ICNTB write status */
107 break;
108 case MCT_L_TCNTB_OFFSET:
109 mask = 1 << 0; /* L_TCNTB write status */
110 break;
111 default:
112 return;
113 }
114 } else {
115 switch (offset) {
116 case EXYNOS4_MCT_G_TCON:
117 stat_addr = EXYNOS4_MCT_G_WSTAT;
118 mask = 1 << 16; /* G_TCON write status */
119 break;
120 case EXYNOS4_MCT_G_COMP0_L:
121 stat_addr = EXYNOS4_MCT_G_WSTAT;
122 mask = 1 << 0; /* G_COMP0_L write status */
123 break;
124 case EXYNOS4_MCT_G_COMP0_U:
125 stat_addr = EXYNOS4_MCT_G_WSTAT;
126 mask = 1 << 1; /* G_COMP0_U write status */
127 break;
128 case EXYNOS4_MCT_G_COMP0_ADD_INCR:
129 stat_addr = EXYNOS4_MCT_G_WSTAT;
130 mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
131 break;
132 case EXYNOS4_MCT_G_CNT_L:
133 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
134 mask = 1 << 0; /* G_CNT_L write status */
135 break;
136 case EXYNOS4_MCT_G_CNT_U:
137 stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
138 mask = 1 << 1; /* G_CNT_U write status */
139 break;
140 default:
141 return;
142 }
143 }
144
145 /* Wait maximum 1 ms until written values are applied */
146 for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
147 if (__raw_readl(reg_base + stat_addr) & mask) {
148 __raw_writel(mask, reg_base + stat_addr);
149 return;
150 }
151
152 panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
153 }
154
155 /* Clocksource handling */
156 static void exynos4_mct_frc_start(void)
157 {
158 u32 reg;
159
160 reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
161 reg |= MCT_G_TCON_START;
162 exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
163 }
164
165 static cycle_t exynos4_frc_read(struct clocksource *cs)
166 {
167 unsigned int lo, hi;
168 u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
169
170 do {
171 hi = hi2;
172 lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
173 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
174 } while (hi != hi2);
175
176 return ((cycle_t)hi << 32) | lo;
177 }
178
179 static void exynos4_frc_resume(struct clocksource *cs)
180 {
181 exynos4_mct_frc_start();
182 }
183
184 struct clocksource mct_frc = {
185 .name = "mct-frc",
186 .rating = 400,
187 .read = exynos4_frc_read,
188 .mask = CLOCKSOURCE_MASK(64),
189 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
190 .resume = exynos4_frc_resume,
191 };
192
193 static u64 notrace exynos4_read_sched_clock(void)
194 {
195 return exynos4_frc_read(&mct_frc);
196 }
197
198 static void __init exynos4_clocksource_init(void)
199 {
200 exynos4_mct_frc_start();
201
202 if (clocksource_register_hz(&mct_frc, clk_rate))
203 panic("%s: can't register clocksource\n", mct_frc.name);
204
205 sched_clock_register(exynos4_read_sched_clock, 64, clk_rate);
206 }
207
208 static void exynos4_mct_comp0_stop(void)
209 {
210 unsigned int tcon;
211
212 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
213 tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
214
215 exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
216 exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
217 }
218
219 static void exynos4_mct_comp0_start(enum clock_event_mode mode,
220 unsigned long cycles)
221 {
222 unsigned int tcon;
223 cycle_t comp_cycle;
224
225 tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
226
227 if (mode == CLOCK_EVT_MODE_PERIODIC) {
228 tcon |= MCT_G_TCON_COMP0_AUTO_INC;
229 exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
230 }
231
232 comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
233 exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
234 exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
235
236 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
237
238 tcon |= MCT_G_TCON_COMP0_ENABLE;
239 exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
240 }
241
242 static int exynos4_comp_set_next_event(unsigned long cycles,
243 struct clock_event_device *evt)
244 {
245 exynos4_mct_comp0_start(evt->mode, cycles);
246
247 return 0;
248 }
249
250 static void exynos4_comp_set_mode(enum clock_event_mode mode,
251 struct clock_event_device *evt)
252 {
253 unsigned long cycles_per_jiffy;
254 exynos4_mct_comp0_stop();
255
256 switch (mode) {
257 case CLOCK_EVT_MODE_PERIODIC:
258 cycles_per_jiffy =
259 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
260 exynos4_mct_comp0_start(mode, cycles_per_jiffy);
261 break;
262
263 case CLOCK_EVT_MODE_ONESHOT:
264 case CLOCK_EVT_MODE_UNUSED:
265 case CLOCK_EVT_MODE_SHUTDOWN:
266 case CLOCK_EVT_MODE_RESUME:
267 break;
268 }
269 }
270
271 static struct clock_event_device mct_comp_device = {
272 .name = "mct-comp",
273 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
274 .rating = 250,
275 .set_next_event = exynos4_comp_set_next_event,
276 .set_mode = exynos4_comp_set_mode,
277 };
278
279 static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
280 {
281 struct clock_event_device *evt = dev_id;
282
283 exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
284
285 evt->event_handler(evt);
286
287 return IRQ_HANDLED;
288 }
289
290 static struct irqaction mct_comp_event_irq = {
291 .name = "mct_comp_irq",
292 .flags = IRQF_TIMER | IRQF_IRQPOLL,
293 .handler = exynos4_mct_comp_isr,
294 .dev_id = &mct_comp_device,
295 };
296
297 static void exynos4_clockevent_init(void)
298 {
299 mct_comp_device.cpumask = cpumask_of(0);
300 clockevents_config_and_register(&mct_comp_device, clk_rate,
301 0xf, 0xffffffff);
302 setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
303 }
304
305 static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick);
306
307 /* Clock event handling */
308 static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
309 {
310 unsigned long tmp;
311 unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
312 unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
313
314 tmp = __raw_readl(reg_base + offset);
315 if (tmp & mask) {
316 tmp &= ~mask;
317 exynos4_mct_write(tmp, offset);
318 }
319 }
320
321 static void exynos4_mct_tick_start(unsigned long cycles,
322 struct mct_clock_event_device *mevt)
323 {
324 unsigned long tmp;
325
326 exynos4_mct_tick_stop(mevt);
327
328 tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */
329
330 /* update interrupt count buffer */
331 exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
332
333 /* enable MCT tick interrupt */
334 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
335
336 tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
337 tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
338 MCT_L_TCON_INTERVAL_MODE;
339 exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
340 }
341
342 static int exynos4_tick_set_next_event(unsigned long cycles,
343 struct clock_event_device *evt)
344 {
345 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
346
347 exynos4_mct_tick_start(cycles, mevt);
348
349 return 0;
350 }
351
352 static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
353 struct clock_event_device *evt)
354 {
355 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
356 unsigned long cycles_per_jiffy;
357
358 exynos4_mct_tick_stop(mevt);
359
360 switch (mode) {
361 case CLOCK_EVT_MODE_PERIODIC:
362 cycles_per_jiffy =
363 (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift);
364 exynos4_mct_tick_start(cycles_per_jiffy, mevt);
365 break;
366
367 case CLOCK_EVT_MODE_ONESHOT:
368 case CLOCK_EVT_MODE_UNUSED:
369 case CLOCK_EVT_MODE_SHUTDOWN:
370 case CLOCK_EVT_MODE_RESUME:
371 break;
372 }
373 }
374
375 static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
376 {
377 struct clock_event_device *evt = &mevt->evt;
378
379 /*
380 * This is for supporting oneshot mode.
381 * Mct would generate interrupt periodically
382 * without explicit stopping.
383 */
384 if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
385 exynos4_mct_tick_stop(mevt);
386
387 /* Clear the MCT tick interrupt */
388 if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
389 exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
390 return 1;
391 } else {
392 return 0;
393 }
394 }
395
396 static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
397 {
398 struct mct_clock_event_device *mevt = dev_id;
399 struct clock_event_device *evt = &mevt->evt;
400
401 exynos4_mct_tick_clear(mevt);
402
403 evt->event_handler(evt);
404
405 return IRQ_HANDLED;
406 }
407
408 static int exynos4_local_timer_setup(struct clock_event_device *evt)
409 {
410 struct mct_clock_event_device *mevt;
411 unsigned int cpu = smp_processor_id();
412
413 mevt = container_of(evt, struct mct_clock_event_device, evt);
414
415 mevt->base = EXYNOS4_MCT_L_BASE(cpu);
416 snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);
417
418 evt->name = mevt->name;
419 evt->cpumask = cpumask_of(cpu);
420 evt->set_next_event = exynos4_tick_set_next_event;
421 evt->set_mode = exynos4_tick_set_mode;
422 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
423 evt->rating = 450;
424
425 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
426
427 if (mct_int_type == MCT_INT_SPI) {
428 evt->irq = mct_irqs[MCT_L0_IRQ + cpu];
429 if (request_irq(evt->irq, exynos4_mct_tick_isr,
430 IRQF_TIMER | IRQF_NOBALANCING,
431 evt->name, mevt)) {
432 pr_err("exynos-mct: cannot register IRQ %d\n",
433 evt->irq);
434 return -EIO;
435 }
436 irq_force_affinity(mct_irqs[MCT_L0_IRQ + cpu], cpumask_of(cpu));
437 } else {
438 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
439 }
440 clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
441 0xf, 0x7fffffff);
442
443 return 0;
444 }
445
446 static void exynos4_local_timer_stop(struct clock_event_device *evt)
447 {
448 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
449 if (mct_int_type == MCT_INT_SPI)
450 free_irq(evt->irq, this_cpu_ptr(&percpu_mct_tick));
451 else
452 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
453 }
454
455 static int exynos4_mct_cpu_notify(struct notifier_block *self,
456 unsigned long action, void *hcpu)
457 {
458 struct mct_clock_event_device *mevt;
459
460 /*
461 * Grab cpu pointer in each case to avoid spurious
462 * preemptible warnings
463 */
464 switch (action & ~CPU_TASKS_FROZEN) {
465 case CPU_STARTING:
466 mevt = this_cpu_ptr(&percpu_mct_tick);
467 exynos4_local_timer_setup(&mevt->evt);
468 break;
469 case CPU_DYING:
470 mevt = this_cpu_ptr(&percpu_mct_tick);
471 exynos4_local_timer_stop(&mevt->evt);
472 break;
473 }
474
475 return NOTIFY_OK;
476 }
477
478 static struct notifier_block exynos4_mct_cpu_nb = {
479 .notifier_call = exynos4_mct_cpu_notify,
480 };
481
482 static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
483 {
484 int err;
485 struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick);
486 struct clk *mct_clk, *tick_clk;
487
488 tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
489 clk_get(NULL, "fin_pll");
490 if (IS_ERR(tick_clk))
491 panic("%s: unable to determine tick clock rate\n", __func__);
492 clk_rate = clk_get_rate(tick_clk);
493
494 mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
495 if (IS_ERR(mct_clk))
496 panic("%s: unable to retrieve mct clock instance\n", __func__);
497 clk_prepare_enable(mct_clk);
498
499 reg_base = base;
500 if (!reg_base)
501 panic("%s: unable to ioremap mct address space\n", __func__);
502
503 if (mct_int_type == MCT_INT_PPI) {
504
505 err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
506 exynos4_mct_tick_isr, "MCT",
507 &percpu_mct_tick);
508 WARN(err, "MCT: can't request IRQ %d (%d)\n",
509 mct_irqs[MCT_L0_IRQ], err);
510 } else {
511 irq_set_affinity(mct_irqs[MCT_L0_IRQ], cpumask_of(0));
512 }
513
514 err = register_cpu_notifier(&exynos4_mct_cpu_nb);
515 if (err)
516 goto out_irq;
517
518 /* Immediately configure the timer on the boot CPU */
519 exynos4_local_timer_setup(&mevt->evt);
520 return;
521
522 out_irq:
523 free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick);
524 }
525
526 void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1)
527 {
528 mct_irqs[MCT_G0_IRQ] = irq_g0;
529 mct_irqs[MCT_L0_IRQ] = irq_l0;
530 mct_irqs[MCT_L1_IRQ] = irq_l1;
531 mct_int_type = MCT_INT_SPI;
532
533 exynos4_timer_resources(NULL, base);
534 exynos4_clocksource_init();
535 exynos4_clockevent_init();
536 }
537
538 static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
539 {
540 u32 nr_irqs, i;
541
542 mct_int_type = int_type;
543
544 /* This driver uses only one global timer interrupt */
545 mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
546
547 /*
548 * Find out the number of local irqs specified. The local
549 * timer irqs are specified after the four global timer
550 * irqs are specified.
551 */
552 #ifdef CONFIG_OF
553 nr_irqs = of_irq_count(np);
554 #else
555 nr_irqs = 0;
556 #endif
557 for (i = MCT_L0_IRQ; i < nr_irqs; i++)
558 mct_irqs[i] = irq_of_parse_and_map(np, i);
559
560 exynos4_timer_resources(np, of_iomap(np, 0));
561 exynos4_clocksource_init();
562 exynos4_clockevent_init();
563 }
564
565
566 static void __init mct_init_spi(struct device_node *np)
567 {
568 return mct_init_dt(np, MCT_INT_SPI);
569 }
570
571 static void __init mct_init_ppi(struct device_node *np)
572 {
573 return mct_init_dt(np, MCT_INT_PPI);
574 }
575 CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
576 CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);
Linux kernel - Deliverables
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