drivers/clocksource/mips-gic-timer.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2012 MIPS Technologies, Inc.  All rights reserved.
   7  */
   8 #include <linux/clockchips.h>
   9 #include <linux/cpu.h>
  10 #include <linux/init.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/irqchip/mips-gic.h>
  13 #include <linux/notifier.h>
  14 #include <linux/of_irq.h>
  15 #include <linux/percpu.h>
  16 #include <linux/smp.h>
  17 #include <linux/time.h>
  18
  19 static DEFINE_PER_CPU(struct clock_event_device, gic_clockevent_device);
  20 static int gic_timer_irq;
  21 static unsigned int gic_frequency;
  22
  23 static int gic_next_event(unsigned long delta, struct clock_event_device *evt)
  24 {
  25         u64 cnt;
  26         int res;
  27
  28         cnt = gic_read_count();
  29         cnt += (u64)delta;
  30         gic_write_cpu_compare(cnt, cpumask_first(evt->cpumask));
  31         res = ((int)(gic_read_count() - cnt) >= 0) ? -ETIME : 0;
  32         return res;
  33 }
  34
  35 static void gic_set_clock_mode(enum clock_event_mode mode,
  36                                 struct clock_event_device *evt)
  37 {
  38         /* Nothing to do ...  */
  39 }
  40
  41 static irqreturn_t gic_compare_interrupt(int irq, void *dev_id)
  42 {
  43         struct clock_event_device *cd = dev_id;
  44
  45         gic_write_compare(gic_read_compare());
  46         cd->event_handler(cd);
  47         return IRQ_HANDLED;
  48 }
  49
  50 struct irqaction gic_compare_irqaction = {
  51         .handler = gic_compare_interrupt,
  52         .percpu_dev_id = &gic_clockevent_device,
  53         .flags = IRQF_PERCPU | IRQF_TIMER,
  54         .name = "timer",
  55 };
  56
  57 static void gic_clockevent_cpu_init(struct clock_event_device *cd)
  58 {
  59         unsigned int cpu = smp_processor_id();
  60
  61         cd->name                = "MIPS GIC";
  62         cd->features            = CLOCK_EVT_FEAT_ONESHOT |
  63                                   CLOCK_EVT_FEAT_C3STOP;
  64
  65         cd->rating              = 350;
  66         cd->irq                 = gic_timer_irq;
  67         cd->cpumask             = cpumask_of(cpu);
  68         cd->set_next_event      = gic_next_event;
  69         cd->set_mode            = gic_set_clock_mode;
  70
  71         clockevents_config_and_register(cd, gic_frequency, 0x300, 0x7fffffff);
  72
  73         enable_percpu_irq(gic_timer_irq, IRQ_TYPE_NONE);
  74 }
  75
  76 static void gic_clockevent_cpu_exit(struct clock_event_device *cd)
  77 {
  78         disable_percpu_irq(gic_timer_irq);
  79 }
  80
  81 static int gic_cpu_notifier(struct notifier_block *nb, unsigned long action,
  82                                 void *data)
  83 {
  84         switch (action & ~CPU_TASKS_FROZEN) {
  85         case CPU_STARTING:
  86                 gic_clockevent_cpu_init(this_cpu_ptr(&gic_clockevent_device));
  87                 break;
  88         case CPU_DYING:
  89                 gic_clockevent_cpu_exit(this_cpu_ptr(&gic_clockevent_device));
  90                 break;
  91         }
  92
  93         return NOTIFY_OK;
  94 }
  95
  96 static struct notifier_block gic_cpu_nb = {
  97         .notifier_call = gic_cpu_notifier,
  98 };
  99
 100 static int gic_clockevent_init(void)
 101 {
 102         if (!cpu_has_counter || !gic_frequency)
 103                 return -ENXIO;
 104
 105         setup_percpu_irq(gic_timer_irq, &gic_compare_irqaction);
 106
 107         register_cpu_notifier(&gic_cpu_nb);
 108
 109         gic_clockevent_cpu_init(this_cpu_ptr(&gic_clockevent_device));
 110
 111         return 0;
 112 }
 113
 114 static cycle_t gic_hpt_read(struct clocksource *cs)
 115 {
 116         return gic_read_count();
 117 }
 118
 119 static struct clocksource gic_clocksource = {
 120         .name   = "GIC",
 121         .read   = gic_hpt_read,
 122         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 123 };
 124
 125 static void __init __gic_clocksource_init(void)
 126 {
 127         /* Set clocksource mask. */
 128         gic_clocksource.mask = CLOCKSOURCE_MASK(gic_get_count_width());
 129
 130         /* Calculate a somewhat reasonable rating value. */
 131         gic_clocksource.rating = 200 + gic_frequency / 10000000;
 132
 133         clocksource_register_hz(&gic_clocksource, gic_frequency);
 134
 135         gic_clockevent_init();
 136 }
 137
 138 void __init gic_clocksource_init(unsigned int frequency)
 139 {
 140         gic_frequency = frequency;
 141         gic_timer_irq = MIPS_GIC_IRQ_BASE +
 142                 GIC_LOCAL_TO_HWIRQ(GIC_LOCAL_INT_COMPARE);
 143
 144         __gic_clocksource_init();
 145 }
 146
 147 static void __init gic_clocksource_of_init(struct device_node *node)
 148 {
 149         if (WARN_ON(!gic_present || !node->parent ||
 150                     !of_device_is_compatible(node->parent, "mti,gic")))
 151                 return;
 152
 153         if (of_property_read_u32(node, "clock-frequency", &gic_frequency)) {
 154                 pr_err("GIC frequency not specified.\n");
 155                 return;
 156         }
 157         gic_timer_irq = irq_of_parse_and_map(node, 0);
 158         if (!gic_timer_irq) {
 159                 pr_err("GIC timer IRQ not specified.\n");
 160                 return;
 161         }
 162
 163         __gic_clocksource_init();
 164 }
 165 CLOCKSOURCE_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
 166                        gic_clocksource_of_init);