2 * SuperH Timer Support - CMT
4 * Copyright (C) 2008 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
26 #include <linux/clk.h>
27 #include <linux/irq.h>
28 #include <linux/err.h>
29 #include <linux/delay.h>
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/sh_timer.h>
33 #include <linux/slab.h>
34 #include <linux/module.h>
35 #include <linux/pm_domain.h>
36 #include <linux/pm_runtime.h>
39 void __iomem
*mapbase
;
41 unsigned long width
; /* 16 or 32 bit version of hardware block */
42 unsigned long overflow_bit
;
43 unsigned long clear_bits
;
44 struct irqaction irqaction
;
45 struct platform_device
*pdev
;
48 unsigned long match_value
;
49 unsigned long next_match_value
;
50 unsigned long max_match_value
;
53 struct clock_event_device ced
;
54 struct clocksource cs
;
55 unsigned long total_cycles
;
59 static DEFINE_RAW_SPINLOCK(sh_cmt_lock
);
61 #define CMSTR -1 /* shared register */
62 #define CMCSR 0 /* channel register */
63 #define CMCNT 1 /* channel register */
64 #define CMCOR 2 /* channel register */
66 static inline unsigned long sh_cmt_read(struct sh_cmt_priv
*p
, int reg_nr
)
68 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
69 void __iomem
*base
= p
->mapbase
;
72 if (reg_nr
== CMSTR
) {
74 base
-= cfg
->channel_offset
;
82 if ((reg_nr
== CMCNT
) || (reg_nr
== CMCOR
))
83 return ioread32(base
+ offs
);
86 return ioread16(base
+ offs
);
89 static inline unsigned long sh_cmt_read_cmstr(struct sh_cmt_priv
*p
)
91 return sh_cmt_read(p
, CMSTR
);
94 static inline unsigned long sh_cmt_read_cmcsr(struct sh_cmt_priv
*p
)
96 return sh_cmt_read(p
, CMCSR
);
99 static inline unsigned long sh_cmt_read_cmcnt(struct sh_cmt_priv
*p
)
101 return sh_cmt_read(p
, CMCNT
);
104 static inline void sh_cmt_write(struct sh_cmt_priv
*p
, int reg_nr
,
107 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
108 void __iomem
*base
= p
->mapbase
;
111 if (reg_nr
== CMSTR
) {
113 base
-= cfg
->channel_offset
;
121 if ((reg_nr
== CMCNT
) || (reg_nr
== CMCOR
)) {
122 iowrite32(value
, base
+ offs
);
127 iowrite16(value
, base
+ offs
);
130 static inline void sh_cmt_write_cmstr(struct sh_cmt_priv
*p
,
133 sh_cmt_write(p
, CMSTR
, value
);
136 static inline void sh_cmt_write_cmcsr(struct sh_cmt_priv
*p
,
139 sh_cmt_write(p
, CMCSR
, value
);
142 static inline void sh_cmt_write_cmcnt(struct sh_cmt_priv
*p
,
145 sh_cmt_write(p
, CMCNT
, value
);
148 static inline void sh_cmt_write_cmcor(struct sh_cmt_priv
*p
,
151 sh_cmt_write(p
, CMCOR
, value
);
154 static unsigned long sh_cmt_get_counter(struct sh_cmt_priv
*p
,
157 unsigned long v1
, v2
, v3
;
160 o1
= sh_cmt_read_cmcsr(p
) & p
->overflow_bit
;
162 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
165 v1
= sh_cmt_read_cmcnt(p
);
166 v2
= sh_cmt_read_cmcnt(p
);
167 v3
= sh_cmt_read_cmcnt(p
);
168 o1
= sh_cmt_read_cmcsr(p
) & p
->overflow_bit
;
169 } while (unlikely((o1
!= o2
) || (v1
> v2
&& v1
< v3
)
170 || (v2
> v3
&& v2
< v1
) || (v3
> v1
&& v3
< v2
)));
177 static void sh_cmt_start_stop_ch(struct sh_cmt_priv
*p
, int start
)
179 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
180 unsigned long flags
, value
;
182 /* start stop register shared by multiple timer channels */
183 raw_spin_lock_irqsave(&sh_cmt_lock
, flags
);
184 value
= sh_cmt_read_cmstr(p
);
187 value
|= 1 << cfg
->timer_bit
;
189 value
&= ~(1 << cfg
->timer_bit
);
191 sh_cmt_write_cmstr(p
, value
);
192 raw_spin_unlock_irqrestore(&sh_cmt_lock
, flags
);
195 static int sh_cmt_enable(struct sh_cmt_priv
*p
, unsigned long *rate
)
199 pm_runtime_get_sync(&p
->pdev
->dev
);
200 dev_pm_syscore_device(&p
->pdev
->dev
, true);
203 ret
= clk_enable(p
->clk
);
205 dev_err(&p
->pdev
->dev
, "cannot enable clock\n");
209 /* make sure channel is disabled */
210 sh_cmt_start_stop_ch(p
, 0);
212 /* configure channel, periodic mode and maximum timeout */
213 if (p
->width
== 16) {
214 *rate
= clk_get_rate(p
->clk
) / 512;
215 sh_cmt_write_cmcsr(p
, 0x43);
217 *rate
= clk_get_rate(p
->clk
) / 8;
218 sh_cmt_write_cmcsr(p
, 0x01a4);
221 sh_cmt_write_cmcor(p
, 0xffffffff);
222 sh_cmt_write_cmcnt(p
, 0);
225 * According to the sh73a0 user's manual, as CMCNT can be operated
226 * only by the RCLK (Pseudo 32 KHz), there's one restriction on
227 * modifying CMCNT register; two RCLK cycles are necessary before
228 * this register is either read or any modification of the value
229 * it holds is reflected in the LSI's actual operation.
231 * While at it, we're supposed to clear out the CMCNT as of this
232 * moment, so make sure it's processed properly here. This will
233 * take RCLKx2 at maximum.
235 for (k
= 0; k
< 100; k
++) {
236 if (!sh_cmt_read_cmcnt(p
))
241 if (sh_cmt_read_cmcnt(p
)) {
242 dev_err(&p
->pdev
->dev
, "cannot clear CMCNT\n");
248 sh_cmt_start_stop_ch(p
, 1);
258 static void sh_cmt_disable(struct sh_cmt_priv
*p
)
260 /* disable channel */
261 sh_cmt_start_stop_ch(p
, 0);
263 /* disable interrupts in CMT block */
264 sh_cmt_write_cmcsr(p
, 0);
269 dev_pm_syscore_device(&p
->pdev
->dev
, false);
270 pm_runtime_put(&p
->pdev
->dev
);
274 #define FLAG_CLOCKEVENT (1 << 0)
275 #define FLAG_CLOCKSOURCE (1 << 1)
276 #define FLAG_REPROGRAM (1 << 2)
277 #define FLAG_SKIPEVENT (1 << 3)
278 #define FLAG_IRQCONTEXT (1 << 4)
280 static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv
*p
,
283 unsigned long new_match
;
284 unsigned long value
= p
->next_match_value
;
285 unsigned long delay
= 0;
286 unsigned long now
= 0;
289 now
= sh_cmt_get_counter(p
, &has_wrapped
);
290 p
->flags
|= FLAG_REPROGRAM
; /* force reprogram */
293 /* we're competing with the interrupt handler.
294 * -> let the interrupt handler reprogram the timer.
295 * -> interrupt number two handles the event.
297 p
->flags
|= FLAG_SKIPEVENT
;
305 /* reprogram the timer hardware,
306 * but don't save the new match value yet.
308 new_match
= now
+ value
+ delay
;
309 if (new_match
> p
->max_match_value
)
310 new_match
= p
->max_match_value
;
312 sh_cmt_write_cmcor(p
, new_match
);
314 now
= sh_cmt_get_counter(p
, &has_wrapped
);
315 if (has_wrapped
&& (new_match
> p
->match_value
)) {
316 /* we are changing to a greater match value,
317 * so this wrap must be caused by the counter
318 * matching the old value.
319 * -> first interrupt reprograms the timer.
320 * -> interrupt number two handles the event.
322 p
->flags
|= FLAG_SKIPEVENT
;
327 /* we are changing to a smaller match value,
328 * so the wrap must be caused by the counter
329 * matching the new value.
330 * -> save programmed match value.
331 * -> let isr handle the event.
333 p
->match_value
= new_match
;
337 /* be safe: verify hardware settings */
338 if (now
< new_match
) {
339 /* timer value is below match value, all good.
340 * this makes sure we won't miss any match events.
341 * -> save programmed match value.
342 * -> let isr handle the event.
344 p
->match_value
= new_match
;
348 /* the counter has reached a value greater
349 * than our new match value. and since the
350 * has_wrapped flag isn't set we must have
351 * programmed a too close event.
352 * -> increase delay and retry.
360 dev_warn(&p
->pdev
->dev
, "too long delay\n");
365 static void __sh_cmt_set_next(struct sh_cmt_priv
*p
, unsigned long delta
)
367 if (delta
> p
->max_match_value
)
368 dev_warn(&p
->pdev
->dev
, "delta out of range\n");
370 p
->next_match_value
= delta
;
371 sh_cmt_clock_event_program_verify(p
, 0);
374 static void sh_cmt_set_next(struct sh_cmt_priv
*p
, unsigned long delta
)
378 raw_spin_lock_irqsave(&p
->lock
, flags
);
379 __sh_cmt_set_next(p
, delta
);
380 raw_spin_unlock_irqrestore(&p
->lock
, flags
);
383 static irqreturn_t
sh_cmt_interrupt(int irq
, void *dev_id
)
385 struct sh_cmt_priv
*p
= dev_id
;
388 sh_cmt_write_cmcsr(p
, sh_cmt_read_cmcsr(p
) & p
->clear_bits
);
390 /* update clock source counter to begin with if enabled
391 * the wrap flag should be cleared by the timer specific
392 * isr before we end up here.
394 if (p
->flags
& FLAG_CLOCKSOURCE
)
395 p
->total_cycles
+= p
->match_value
+ 1;
397 if (!(p
->flags
& FLAG_REPROGRAM
))
398 p
->next_match_value
= p
->max_match_value
;
400 p
->flags
|= FLAG_IRQCONTEXT
;
402 if (p
->flags
& FLAG_CLOCKEVENT
) {
403 if (!(p
->flags
& FLAG_SKIPEVENT
)) {
404 if (p
->ced
.mode
== CLOCK_EVT_MODE_ONESHOT
) {
405 p
->next_match_value
= p
->max_match_value
;
406 p
->flags
|= FLAG_REPROGRAM
;
409 p
->ced
.event_handler(&p
->ced
);
413 p
->flags
&= ~FLAG_SKIPEVENT
;
415 if (p
->flags
& FLAG_REPROGRAM
) {
416 p
->flags
&= ~FLAG_REPROGRAM
;
417 sh_cmt_clock_event_program_verify(p
, 1);
419 if (p
->flags
& FLAG_CLOCKEVENT
)
420 if ((p
->ced
.mode
== CLOCK_EVT_MODE_SHUTDOWN
)
421 || (p
->match_value
== p
->next_match_value
))
422 p
->flags
&= ~FLAG_REPROGRAM
;
425 p
->flags
&= ~FLAG_IRQCONTEXT
;
430 static int sh_cmt_start(struct sh_cmt_priv
*p
, unsigned long flag
)
435 raw_spin_lock_irqsave(&p
->lock
, flags
);
437 if (!(p
->flags
& (FLAG_CLOCKEVENT
| FLAG_CLOCKSOURCE
)))
438 ret
= sh_cmt_enable(p
, &p
->rate
);
444 /* setup timeout if no clockevent */
445 if ((flag
== FLAG_CLOCKSOURCE
) && (!(p
->flags
& FLAG_CLOCKEVENT
)))
446 __sh_cmt_set_next(p
, p
->max_match_value
);
448 raw_spin_unlock_irqrestore(&p
->lock
, flags
);
453 static void sh_cmt_stop(struct sh_cmt_priv
*p
, unsigned long flag
)
458 raw_spin_lock_irqsave(&p
->lock
, flags
);
460 f
= p
->flags
& (FLAG_CLOCKEVENT
| FLAG_CLOCKSOURCE
);
463 if (f
&& !(p
->flags
& (FLAG_CLOCKEVENT
| FLAG_CLOCKSOURCE
)))
466 /* adjust the timeout to maximum if only clocksource left */
467 if ((flag
== FLAG_CLOCKEVENT
) && (p
->flags
& FLAG_CLOCKSOURCE
))
468 __sh_cmt_set_next(p
, p
->max_match_value
);
470 raw_spin_unlock_irqrestore(&p
->lock
, flags
);
473 static struct sh_cmt_priv
*cs_to_sh_cmt(struct clocksource
*cs
)
475 return container_of(cs
, struct sh_cmt_priv
, cs
);
478 static cycle_t
sh_cmt_clocksource_read(struct clocksource
*cs
)
480 struct sh_cmt_priv
*p
= cs_to_sh_cmt(cs
);
481 unsigned long flags
, raw
;
485 raw_spin_lock_irqsave(&p
->lock
, flags
);
486 value
= p
->total_cycles
;
487 raw
= sh_cmt_get_counter(p
, &has_wrapped
);
489 if (unlikely(has_wrapped
))
490 raw
+= p
->match_value
+ 1;
491 raw_spin_unlock_irqrestore(&p
->lock
, flags
);
496 static int sh_cmt_clocksource_enable(struct clocksource
*cs
)
499 struct sh_cmt_priv
*p
= cs_to_sh_cmt(cs
);
501 WARN_ON(p
->cs_enabled
);
505 ret
= sh_cmt_start(p
, FLAG_CLOCKSOURCE
);
507 __clocksource_updatefreq_hz(cs
, p
->rate
);
508 p
->cs_enabled
= true;
513 static void sh_cmt_clocksource_disable(struct clocksource
*cs
)
515 struct sh_cmt_priv
*p
= cs_to_sh_cmt(cs
);
517 WARN_ON(!p
->cs_enabled
);
519 sh_cmt_stop(p
, FLAG_CLOCKSOURCE
);
520 p
->cs_enabled
= false;
523 static void sh_cmt_clocksource_suspend(struct clocksource
*cs
)
525 struct sh_cmt_priv
*p
= cs_to_sh_cmt(cs
);
527 sh_cmt_stop(p
, FLAG_CLOCKSOURCE
);
528 pm_genpd_syscore_poweroff(&p
->pdev
->dev
);
531 static void sh_cmt_clocksource_resume(struct clocksource
*cs
)
533 struct sh_cmt_priv
*p
= cs_to_sh_cmt(cs
);
535 pm_genpd_syscore_poweron(&p
->pdev
->dev
);
536 sh_cmt_start(p
, FLAG_CLOCKSOURCE
);
539 static int sh_cmt_register_clocksource(struct sh_cmt_priv
*p
,
540 char *name
, unsigned long rating
)
542 struct clocksource
*cs
= &p
->cs
;
546 cs
->read
= sh_cmt_clocksource_read
;
547 cs
->enable
= sh_cmt_clocksource_enable
;
548 cs
->disable
= sh_cmt_clocksource_disable
;
549 cs
->suspend
= sh_cmt_clocksource_suspend
;
550 cs
->resume
= sh_cmt_clocksource_resume
;
551 cs
->mask
= CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
552 cs
->flags
= CLOCK_SOURCE_IS_CONTINUOUS
;
554 dev_info(&p
->pdev
->dev
, "used as clock source\n");
556 /* Register with dummy 1 Hz value, gets updated in ->enable() */
557 clocksource_register_hz(cs
, 1);
561 static struct sh_cmt_priv
*ced_to_sh_cmt(struct clock_event_device
*ced
)
563 return container_of(ced
, struct sh_cmt_priv
, ced
);
566 static void sh_cmt_clock_event_start(struct sh_cmt_priv
*p
, int periodic
)
568 struct clock_event_device
*ced
= &p
->ced
;
570 sh_cmt_start(p
, FLAG_CLOCKEVENT
);
572 /* TODO: calculate good shift from rate and counter bit width */
575 ced
->mult
= div_sc(p
->rate
, NSEC_PER_SEC
, ced
->shift
);
576 ced
->max_delta_ns
= clockevent_delta2ns(p
->max_match_value
, ced
);
577 ced
->min_delta_ns
= clockevent_delta2ns(0x1f, ced
);
580 sh_cmt_set_next(p
, ((p
->rate
+ HZ
/2) / HZ
) - 1);
582 sh_cmt_set_next(p
, p
->max_match_value
);
585 static void sh_cmt_clock_event_mode(enum clock_event_mode mode
,
586 struct clock_event_device
*ced
)
588 struct sh_cmt_priv
*p
= ced_to_sh_cmt(ced
);
590 /* deal with old setting first */
592 case CLOCK_EVT_MODE_PERIODIC
:
593 case CLOCK_EVT_MODE_ONESHOT
:
594 sh_cmt_stop(p
, FLAG_CLOCKEVENT
);
601 case CLOCK_EVT_MODE_PERIODIC
:
602 dev_info(&p
->pdev
->dev
, "used for periodic clock events\n");
603 sh_cmt_clock_event_start(p
, 1);
605 case CLOCK_EVT_MODE_ONESHOT
:
606 dev_info(&p
->pdev
->dev
, "used for oneshot clock events\n");
607 sh_cmt_clock_event_start(p
, 0);
609 case CLOCK_EVT_MODE_SHUTDOWN
:
610 case CLOCK_EVT_MODE_UNUSED
:
611 sh_cmt_stop(p
, FLAG_CLOCKEVENT
);
618 static int sh_cmt_clock_event_next(unsigned long delta
,
619 struct clock_event_device
*ced
)
621 struct sh_cmt_priv
*p
= ced_to_sh_cmt(ced
);
623 BUG_ON(ced
->mode
!= CLOCK_EVT_MODE_ONESHOT
);
624 if (likely(p
->flags
& FLAG_IRQCONTEXT
))
625 p
->next_match_value
= delta
- 1;
627 sh_cmt_set_next(p
, delta
- 1);
632 static void sh_cmt_clock_event_suspend(struct clock_event_device
*ced
)
634 pm_genpd_syscore_poweroff(&ced_to_sh_cmt(ced
)->pdev
->dev
);
637 static void sh_cmt_clock_event_resume(struct clock_event_device
*ced
)
639 pm_genpd_syscore_poweron(&ced_to_sh_cmt(ced
)->pdev
->dev
);
642 static void sh_cmt_register_clockevent(struct sh_cmt_priv
*p
,
643 char *name
, unsigned long rating
)
645 struct clock_event_device
*ced
= &p
->ced
;
647 memset(ced
, 0, sizeof(*ced
));
650 ced
->features
= CLOCK_EVT_FEAT_PERIODIC
;
651 ced
->features
|= CLOCK_EVT_FEAT_ONESHOT
;
652 ced
->rating
= rating
;
653 ced
->cpumask
= cpumask_of(0);
654 ced
->set_next_event
= sh_cmt_clock_event_next
;
655 ced
->set_mode
= sh_cmt_clock_event_mode
;
656 ced
->suspend
= sh_cmt_clock_event_suspend
;
657 ced
->resume
= sh_cmt_clock_event_resume
;
659 dev_info(&p
->pdev
->dev
, "used for clock events\n");
660 clockevents_register_device(ced
);
663 static int sh_cmt_register(struct sh_cmt_priv
*p
, char *name
,
664 unsigned long clockevent_rating
,
665 unsigned long clocksource_rating
)
667 if (clockevent_rating
)
668 sh_cmt_register_clockevent(p
, name
, clockevent_rating
);
670 if (clocksource_rating
)
671 sh_cmt_register_clocksource(p
, name
, clocksource_rating
);
676 static int sh_cmt_setup(struct sh_cmt_priv
*p
, struct platform_device
*pdev
)
678 struct sh_timer_config
*cfg
= pdev
->dev
.platform_data
;
679 struct resource
*res
;
683 memset(p
, 0, sizeof(*p
));
687 dev_err(&p
->pdev
->dev
, "missing platform data\n");
691 platform_set_drvdata(pdev
, p
);
693 res
= platform_get_resource(p
->pdev
, IORESOURCE_MEM
, 0);
695 dev_err(&p
->pdev
->dev
, "failed to get I/O memory\n");
699 irq
= platform_get_irq(p
->pdev
, 0);
701 dev_err(&p
->pdev
->dev
, "failed to get irq\n");
705 /* map memory, let mapbase point to our channel */
706 p
->mapbase
= ioremap_nocache(res
->start
, resource_size(res
));
707 if (p
->mapbase
== NULL
) {
708 dev_err(&p
->pdev
->dev
, "failed to remap I/O memory\n");
712 /* request irq using setup_irq() (too early for request_irq()) */
713 p
->irqaction
.name
= dev_name(&p
->pdev
->dev
);
714 p
->irqaction
.handler
= sh_cmt_interrupt
;
715 p
->irqaction
.dev_id
= p
;
716 p
->irqaction
.flags
= IRQF_DISABLED
| IRQF_TIMER
| \
717 IRQF_IRQPOLL
| IRQF_NOBALANCING
;
719 /* get hold of clock */
720 p
->clk
= clk_get(&p
->pdev
->dev
, "cmt_fck");
721 if (IS_ERR(p
->clk
)) {
722 dev_err(&p
->pdev
->dev
, "cannot get clock\n");
723 ret
= PTR_ERR(p
->clk
);
727 if (resource_size(res
) == 6) {
729 p
->overflow_bit
= 0x80;
730 p
->clear_bits
= ~0x80;
733 p
->overflow_bit
= 0x8000;
734 p
->clear_bits
= ~0xc000;
737 if (p
->width
== (sizeof(p
->max_match_value
) * 8))
738 p
->max_match_value
= ~0;
740 p
->max_match_value
= (1 << p
->width
) - 1;
742 p
->match_value
= p
->max_match_value
;
743 raw_spin_lock_init(&p
->lock
);
745 ret
= sh_cmt_register(p
, (char *)dev_name(&p
->pdev
->dev
),
746 cfg
->clockevent_rating
,
747 cfg
->clocksource_rating
);
749 dev_err(&p
->pdev
->dev
, "registration failed\n");
752 p
->cs_enabled
= false;
754 ret
= setup_irq(irq
, &p
->irqaction
);
756 dev_err(&p
->pdev
->dev
, "failed to request irq %d\n", irq
);
770 static int sh_cmt_probe(struct platform_device
*pdev
)
772 struct sh_cmt_priv
*p
= platform_get_drvdata(pdev
);
773 struct sh_timer_config
*cfg
= pdev
->dev
.platform_data
;
776 if (!is_early_platform_device(pdev
)) {
777 pm_runtime_set_active(&pdev
->dev
);
778 pm_runtime_enable(&pdev
->dev
);
782 dev_info(&pdev
->dev
, "kept as earlytimer\n");
786 p
= kmalloc(sizeof(*p
), GFP_KERNEL
);
788 dev_err(&pdev
->dev
, "failed to allocate driver data\n");
792 ret
= sh_cmt_setup(p
, pdev
);
795 platform_set_drvdata(pdev
, NULL
);
796 pm_runtime_idle(&pdev
->dev
);
799 if (is_early_platform_device(pdev
))
803 if (cfg
->clockevent_rating
|| cfg
->clocksource_rating
)
804 pm_runtime_irq_safe(&pdev
->dev
);
806 pm_runtime_idle(&pdev
->dev
);
811 static int sh_cmt_remove(struct platform_device
*pdev
)
813 return -EBUSY
; /* cannot unregister clockevent and clocksource */
816 static struct platform_driver sh_cmt_device_driver
= {
817 .probe
= sh_cmt_probe
,
818 .remove
= sh_cmt_remove
,
824 static int __init
sh_cmt_init(void)
826 return platform_driver_register(&sh_cmt_device_driver
);
829 static void __exit
sh_cmt_exit(void)
831 platform_driver_unregister(&sh_cmt_device_driver
);
834 early_platform_init("earlytimer", &sh_cmt_device_driver
);
835 module_init(sh_cmt_init
);
836 module_exit(sh_cmt_exit
);
838 MODULE_AUTHOR("Magnus Damm");
839 MODULE_DESCRIPTION("SuperH CMT Timer Driver");
840 MODULE_LICENSE("GPL v2");