2 * SuperH Timer Support - CMT
4 * Copyright (C) 2008 Magnus Damm
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
26 #include <linux/clk.h>
27 #include <linux/irq.h>
28 #include <linux/err.h>
29 #include <linux/clocksource.h>
30 #include <linux/clockchips.h>
31 #include <linux/sh_timer.h>
34 void __iomem
*mapbase
;
36 unsigned long width
; /* 16 or 32 bit version of hardware block */
37 unsigned long overflow_bit
;
38 unsigned long clear_bits
;
39 struct irqaction irqaction
;
40 struct platform_device
*pdev
;
43 unsigned long match_value
;
44 unsigned long next_match_value
;
45 unsigned long max_match_value
;
48 struct clock_event_device ced
;
49 struct clocksource cs
;
50 unsigned long total_cycles
;
53 static DEFINE_SPINLOCK(sh_cmt_lock
);
55 #define CMSTR -1 /* shared register */
56 #define CMCSR 0 /* channel register */
57 #define CMCNT 1 /* channel register */
58 #define CMCOR 2 /* channel register */
60 static inline unsigned long sh_cmt_read(struct sh_cmt_priv
*p
, int reg_nr
)
62 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
63 void __iomem
*base
= p
->mapbase
;
66 if (reg_nr
== CMSTR
) {
68 base
-= cfg
->channel_offset
;
76 if ((reg_nr
== CMCNT
) || (reg_nr
== CMCOR
))
77 return ioread32(base
+ offs
);
80 return ioread16(base
+ offs
);
83 static inline void sh_cmt_write(struct sh_cmt_priv
*p
, int reg_nr
,
86 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
87 void __iomem
*base
= p
->mapbase
;
90 if (reg_nr
== CMSTR
) {
92 base
-= cfg
->channel_offset
;
100 if ((reg_nr
== CMCNT
) || (reg_nr
== CMCOR
)) {
101 iowrite32(value
, base
+ offs
);
106 iowrite16(value
, base
+ offs
);
109 static unsigned long sh_cmt_get_counter(struct sh_cmt_priv
*p
,
112 unsigned long v1
, v2
, v3
;
115 o1
= sh_cmt_read(p
, CMCSR
) & p
->overflow_bit
;
117 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
120 v1
= sh_cmt_read(p
, CMCNT
);
121 v2
= sh_cmt_read(p
, CMCNT
);
122 v3
= sh_cmt_read(p
, CMCNT
);
123 o1
= sh_cmt_read(p
, CMCSR
) & p
->overflow_bit
;
124 } while (unlikely((o1
!= o2
) || (v1
> v2
&& v1
< v3
)
125 || (v2
> v3
&& v2
< v1
) || (v3
> v1
&& v3
< v2
)));
132 static void sh_cmt_start_stop_ch(struct sh_cmt_priv
*p
, int start
)
134 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
135 unsigned long flags
, value
;
137 /* start stop register shared by multiple timer channels */
138 spin_lock_irqsave(&sh_cmt_lock
, flags
);
139 value
= sh_cmt_read(p
, CMSTR
);
142 value
|= 1 << cfg
->timer_bit
;
144 value
&= ~(1 << cfg
->timer_bit
);
146 sh_cmt_write(p
, CMSTR
, value
);
147 spin_unlock_irqrestore(&sh_cmt_lock
, flags
);
150 static int sh_cmt_enable(struct sh_cmt_priv
*p
, unsigned long *rate
)
152 struct sh_timer_config
*cfg
= p
->pdev
->dev
.platform_data
;
156 ret
= clk_enable(p
->clk
);
158 pr_err("sh_cmt: cannot enable clock \"%s\"\n", cfg
->clk
);
162 /* make sure channel is disabled */
163 sh_cmt_start_stop_ch(p
, 0);
165 /* configure channel, periodic mode and maximum timeout */
166 if (p
->width
== 16) {
167 *rate
= clk_get_rate(p
->clk
) / 512;
168 sh_cmt_write(p
, CMCSR
, 0x43);
170 *rate
= clk_get_rate(p
->clk
) / 8;
171 sh_cmt_write(p
, CMCSR
, 0x01a4);
174 sh_cmt_write(p
, CMCOR
, 0xffffffff);
175 sh_cmt_write(p
, CMCNT
, 0);
178 sh_cmt_start_stop_ch(p
, 1);
182 static void sh_cmt_disable(struct sh_cmt_priv
*p
)
184 /* disable channel */
185 sh_cmt_start_stop_ch(p
, 0);
192 #define FLAG_CLOCKEVENT (1 << 0)
193 #define FLAG_CLOCKSOURCE (1 << 1)
194 #define FLAG_REPROGRAM (1 << 2)
195 #define FLAG_SKIPEVENT (1 << 3)
196 #define FLAG_IRQCONTEXT (1 << 4)
198 static void sh_cmt_clock_event_program_verify(struct sh_cmt_priv
*p
,
201 unsigned long new_match
;
202 unsigned long value
= p
->next_match_value
;
203 unsigned long delay
= 0;
204 unsigned long now
= 0;
207 now
= sh_cmt_get_counter(p
, &has_wrapped
);
208 p
->flags
|= FLAG_REPROGRAM
; /* force reprogram */
211 /* we're competing with the interrupt handler.
212 * -> let the interrupt handler reprogram the timer.
213 * -> interrupt number two handles the event.
215 p
->flags
|= FLAG_SKIPEVENT
;
223 /* reprogram the timer hardware,
224 * but don't save the new match value yet.
226 new_match
= now
+ value
+ delay
;
227 if (new_match
> p
->max_match_value
)
228 new_match
= p
->max_match_value
;
230 sh_cmt_write(p
, CMCOR
, new_match
);
232 now
= sh_cmt_get_counter(p
, &has_wrapped
);
233 if (has_wrapped
&& (new_match
> p
->match_value
)) {
234 /* we are changing to a greater match value,
235 * so this wrap must be caused by the counter
236 * matching the old value.
237 * -> first interrupt reprograms the timer.
238 * -> interrupt number two handles the event.
240 p
->flags
|= FLAG_SKIPEVENT
;
245 /* we are changing to a smaller match value,
246 * so the wrap must be caused by the counter
247 * matching the new value.
248 * -> save programmed match value.
249 * -> let isr handle the event.
251 p
->match_value
= new_match
;
255 /* be safe: verify hardware settings */
256 if (now
< new_match
) {
257 /* timer value is below match value, all good.
258 * this makes sure we won't miss any match events.
259 * -> save programmed match value.
260 * -> let isr handle the event.
262 p
->match_value
= new_match
;
266 /* the counter has reached a value greater
267 * than our new match value. and since the
268 * has_wrapped flag isn't set we must have
269 * programmed a too close event.
270 * -> increase delay and retry.
278 pr_warning("sh_cmt: too long delay\n");
283 static void sh_cmt_set_next(struct sh_cmt_priv
*p
, unsigned long delta
)
287 if (delta
> p
->max_match_value
)
288 pr_warning("sh_cmt: delta out of range\n");
290 spin_lock_irqsave(&p
->lock
, flags
);
291 p
->next_match_value
= delta
;
292 sh_cmt_clock_event_program_verify(p
, 0);
293 spin_unlock_irqrestore(&p
->lock
, flags
);
296 static irqreturn_t
sh_cmt_interrupt(int irq
, void *dev_id
)
298 struct sh_cmt_priv
*p
= dev_id
;
301 sh_cmt_write(p
, CMCSR
, sh_cmt_read(p
, CMCSR
) & p
->clear_bits
);
303 /* update clock source counter to begin with if enabled
304 * the wrap flag should be cleared by the timer specific
305 * isr before we end up here.
307 if (p
->flags
& FLAG_CLOCKSOURCE
)
308 p
->total_cycles
+= p
->match_value
;
310 if (!(p
->flags
& FLAG_REPROGRAM
))
311 p
->next_match_value
= p
->max_match_value
;
313 p
->flags
|= FLAG_IRQCONTEXT
;
315 if (p
->flags
& FLAG_CLOCKEVENT
) {
316 if (!(p
->flags
& FLAG_SKIPEVENT
)) {
317 if (p
->ced
.mode
== CLOCK_EVT_MODE_ONESHOT
) {
318 p
->next_match_value
= p
->max_match_value
;
319 p
->flags
|= FLAG_REPROGRAM
;
322 p
->ced
.event_handler(&p
->ced
);
326 p
->flags
&= ~FLAG_SKIPEVENT
;
328 if (p
->flags
& FLAG_REPROGRAM
) {
329 p
->flags
&= ~FLAG_REPROGRAM
;
330 sh_cmt_clock_event_program_verify(p
, 1);
332 if (p
->flags
& FLAG_CLOCKEVENT
)
333 if ((p
->ced
.mode
== CLOCK_EVT_MODE_SHUTDOWN
)
334 || (p
->match_value
== p
->next_match_value
))
335 p
->flags
&= ~FLAG_REPROGRAM
;
338 p
->flags
&= ~FLAG_IRQCONTEXT
;
343 static int sh_cmt_start(struct sh_cmt_priv
*p
, unsigned long flag
)
348 spin_lock_irqsave(&p
->lock
, flags
);
350 if (!(p
->flags
& (FLAG_CLOCKEVENT
| FLAG_CLOCKSOURCE
)))
351 ret
= sh_cmt_enable(p
, &p
->rate
);
357 /* setup timeout if no clockevent */
358 if ((flag
== FLAG_CLOCKSOURCE
) && (!(p
->flags
& FLAG_CLOCKEVENT
)))
359 sh_cmt_set_next(p
, p
->max_match_value
);
361 spin_unlock_irqrestore(&p
->lock
, flags
);
366 static void sh_cmt_stop(struct sh_cmt_priv
*p
, unsigned long flag
)
371 spin_lock_irqsave(&p
->lock
, flags
);
373 f
= p
->flags
& (FLAG_CLOCKEVENT
| FLAG_CLOCKSOURCE
);
376 if (f
&& !(p
->flags
& (FLAG_CLOCKEVENT
| FLAG_CLOCKSOURCE
)))
379 /* adjust the timeout to maximum if only clocksource left */
380 if ((flag
== FLAG_CLOCKEVENT
) && (p
->flags
& FLAG_CLOCKSOURCE
))
381 sh_cmt_set_next(p
, p
->max_match_value
);
383 spin_unlock_irqrestore(&p
->lock
, flags
);
386 static struct sh_cmt_priv
*cs_to_sh_cmt(struct clocksource
*cs
)
388 return container_of(cs
, struct sh_cmt_priv
, cs
);
391 static cycle_t
sh_cmt_clocksource_read(struct clocksource
*cs
)
393 struct sh_cmt_priv
*p
= cs_to_sh_cmt(cs
);
394 unsigned long flags
, raw
;
398 spin_lock_irqsave(&p
->lock
, flags
);
399 value
= p
->total_cycles
;
400 raw
= sh_cmt_get_counter(p
, &has_wrapped
);
402 if (unlikely(has_wrapped
))
403 raw
+= p
->match_value
;
404 spin_unlock_irqrestore(&p
->lock
, flags
);
409 static int sh_cmt_clocksource_enable(struct clocksource
*cs
)
411 struct sh_cmt_priv
*p
= cs_to_sh_cmt(cs
);
416 ret
= sh_cmt_start(p
, FLAG_CLOCKSOURCE
);
420 /* TODO: calculate good shift from rate and counter bit width */
422 cs
->mult
= clocksource_hz2mult(p
->rate
, cs
->shift
);
426 static void sh_cmt_clocksource_disable(struct clocksource
*cs
)
428 sh_cmt_stop(cs_to_sh_cmt(cs
), FLAG_CLOCKSOURCE
);
431 static int sh_cmt_register_clocksource(struct sh_cmt_priv
*p
,
432 char *name
, unsigned long rating
)
434 struct clocksource
*cs
= &p
->cs
;
438 cs
->read
= sh_cmt_clocksource_read
;
439 cs
->enable
= sh_cmt_clocksource_enable
;
440 cs
->disable
= sh_cmt_clocksource_disable
;
441 cs
->mask
= CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
442 cs
->flags
= CLOCK_SOURCE_IS_CONTINUOUS
;
443 pr_info("sh_cmt: %s used as clock source\n", cs
->name
);
444 clocksource_register(cs
);
448 static struct sh_cmt_priv
*ced_to_sh_cmt(struct clock_event_device
*ced
)
450 return container_of(ced
, struct sh_cmt_priv
, ced
);
453 static void sh_cmt_clock_event_start(struct sh_cmt_priv
*p
, int periodic
)
455 struct clock_event_device
*ced
= &p
->ced
;
457 sh_cmt_start(p
, FLAG_CLOCKEVENT
);
459 /* TODO: calculate good shift from rate and counter bit width */
462 ced
->mult
= div_sc(p
->rate
, NSEC_PER_SEC
, ced
->shift
);
463 ced
->max_delta_ns
= clockevent_delta2ns(p
->max_match_value
, ced
);
464 ced
->min_delta_ns
= clockevent_delta2ns(0x1f, ced
);
467 sh_cmt_set_next(p
, (p
->rate
+ HZ
/2) / HZ
);
469 sh_cmt_set_next(p
, p
->max_match_value
);
472 static void sh_cmt_clock_event_mode(enum clock_event_mode mode
,
473 struct clock_event_device
*ced
)
475 struct sh_cmt_priv
*p
= ced_to_sh_cmt(ced
);
477 /* deal with old setting first */
479 case CLOCK_EVT_MODE_PERIODIC
:
480 case CLOCK_EVT_MODE_ONESHOT
:
481 sh_cmt_stop(p
, FLAG_CLOCKEVENT
);
488 case CLOCK_EVT_MODE_PERIODIC
:
489 pr_info("sh_cmt: %s used for periodic clock events\n",
491 sh_cmt_clock_event_start(p
, 1);
493 case CLOCK_EVT_MODE_ONESHOT
:
494 pr_info("sh_cmt: %s used for oneshot clock events\n",
496 sh_cmt_clock_event_start(p
, 0);
498 case CLOCK_EVT_MODE_SHUTDOWN
:
499 case CLOCK_EVT_MODE_UNUSED
:
500 sh_cmt_stop(p
, FLAG_CLOCKEVENT
);
507 static int sh_cmt_clock_event_next(unsigned long delta
,
508 struct clock_event_device
*ced
)
510 struct sh_cmt_priv
*p
= ced_to_sh_cmt(ced
);
512 BUG_ON(ced
->mode
!= CLOCK_EVT_MODE_ONESHOT
);
513 if (likely(p
->flags
& FLAG_IRQCONTEXT
))
514 p
->next_match_value
= delta
;
516 sh_cmt_set_next(p
, delta
);
521 static void sh_cmt_register_clockevent(struct sh_cmt_priv
*p
,
522 char *name
, unsigned long rating
)
524 struct clock_event_device
*ced
= &p
->ced
;
526 memset(ced
, 0, sizeof(*ced
));
529 ced
->features
= CLOCK_EVT_FEAT_PERIODIC
;
530 ced
->features
|= CLOCK_EVT_FEAT_ONESHOT
;
531 ced
->rating
= rating
;
532 ced
->cpumask
= cpumask_of(0);
533 ced
->set_next_event
= sh_cmt_clock_event_next
;
534 ced
->set_mode
= sh_cmt_clock_event_mode
;
536 pr_info("sh_cmt: %s used for clock events\n", ced
->name
);
537 clockevents_register_device(ced
);
540 static int sh_cmt_register(struct sh_cmt_priv
*p
, char *name
,
541 unsigned long clockevent_rating
,
542 unsigned long clocksource_rating
)
544 if (p
->width
== (sizeof(p
->max_match_value
) * 8))
545 p
->max_match_value
= ~0;
547 p
->max_match_value
= (1 << p
->width
) - 1;
549 p
->match_value
= p
->max_match_value
;
550 spin_lock_init(&p
->lock
);
552 if (clockevent_rating
)
553 sh_cmt_register_clockevent(p
, name
, clockevent_rating
);
555 if (clocksource_rating
)
556 sh_cmt_register_clocksource(p
, name
, clocksource_rating
);
561 static int sh_cmt_setup(struct sh_cmt_priv
*p
, struct platform_device
*pdev
)
563 struct sh_timer_config
*cfg
= pdev
->dev
.platform_data
;
564 struct resource
*res
;
568 memset(p
, 0, sizeof(*p
));
572 dev_err(&p
->pdev
->dev
, "missing platform data\n");
576 platform_set_drvdata(pdev
, p
);
578 res
= platform_get_resource(p
->pdev
, IORESOURCE_MEM
, 0);
580 dev_err(&p
->pdev
->dev
, "failed to get I/O memory\n");
584 irq
= platform_get_irq(p
->pdev
, 0);
586 dev_err(&p
->pdev
->dev
, "failed to get irq\n");
590 /* map memory, let mapbase point to our channel */
591 p
->mapbase
= ioremap_nocache(res
->start
, resource_size(res
));
592 if (p
->mapbase
== NULL
) {
593 pr_err("sh_cmt: failed to remap I/O memory\n");
597 /* request irq using setup_irq() (too early for request_irq()) */
598 p
->irqaction
.name
= cfg
->name
;
599 p
->irqaction
.handler
= sh_cmt_interrupt
;
600 p
->irqaction
.dev_id
= p
;
601 p
->irqaction
.flags
= IRQF_DISABLED
| IRQF_TIMER
| IRQF_IRQPOLL
;
602 p
->irqaction
.mask
= CPU_MASK_NONE
;
603 ret
= setup_irq(irq
, &p
->irqaction
);
605 pr_err("sh_cmt: failed to request irq %d\n", irq
);
609 /* get hold of clock */
610 p
->clk
= clk_get(&p
->pdev
->dev
, cfg
->clk
);
611 if (IS_ERR(p
->clk
)) {
612 pr_err("sh_cmt: cannot get clock \"%s\"\n", cfg
->clk
);
613 ret
= PTR_ERR(p
->clk
);
617 if (resource_size(res
) == 6) {
619 p
->overflow_bit
= 0x80;
620 p
->clear_bits
= ~0x80;
623 p
->overflow_bit
= 0x8000;
624 p
->clear_bits
= ~0xc000;
627 return sh_cmt_register(p
, cfg
->name
,
628 cfg
->clockevent_rating
,
629 cfg
->clocksource_rating
);
631 remove_irq(irq
, &p
->irqaction
);
638 static int __devinit
sh_cmt_probe(struct platform_device
*pdev
)
640 struct sh_cmt_priv
*p
= platform_get_drvdata(pdev
);
641 struct sh_timer_config
*cfg
= pdev
->dev
.platform_data
;
645 pr_info("sh_cmt: %s kept as earlytimer\n", cfg
->name
);
649 p
= kmalloc(sizeof(*p
), GFP_KERNEL
);
651 dev_err(&pdev
->dev
, "failed to allocate driver data\n");
655 ret
= sh_cmt_setup(p
, pdev
);
658 platform_set_drvdata(pdev
, NULL
);
663 static int __devexit
sh_cmt_remove(struct platform_device
*pdev
)
665 return -EBUSY
; /* cannot unregister clockevent and clocksource */
668 static struct platform_driver sh_cmt_device_driver
= {
669 .probe
= sh_cmt_probe
,
670 .remove
= __devexit_p(sh_cmt_remove
),
676 static int __init
sh_cmt_init(void)
678 return platform_driver_register(&sh_cmt_device_driver
);
681 static void __exit
sh_cmt_exit(void)
683 platform_driver_unregister(&sh_cmt_device_driver
);
686 early_platform_init("earlytimer", &sh_cmt_device_driver
);
687 module_init(sh_cmt_init
);
688 module_exit(sh_cmt_exit
);
690 MODULE_AUTHOR("Magnus Damm");
691 MODULE_DESCRIPTION("SuperH CMT Timer Driver");
692 MODULE_LICENSE("GPL v2");