drivers/clocksource/sh_mtu2.c

   1 /*
   2  * SuperH Timer Support - MTU2
   3  *
   4  *  Copyright (C) 2009 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/ioport.h>
  25 #include <linux/delay.h>
  26 #include <linux/io.h>
  27 #include <linux/clk.h>
  28 #include <linux/irq.h>
  29 #include <linux/err.h>
  30 #include <linux/clockchips.h>
  31 #include <linux/sh_timer.h>
  32 #include <linux/slab.h>
  33 #include <linux/module.h>
  34 #include <linux/pm_domain.h>
  35
  36 struct sh_mtu2_priv {
  37         void __iomem *mapbase;
  38         struct clk *clk;
  39         struct irqaction irqaction;
  40         struct platform_device *pdev;
  41         unsigned long rate;
  42         unsigned long periodic;
  43         struct clock_event_device ced;
  44 };
  45
  46 static DEFINE_RAW_SPINLOCK(sh_mtu2_lock);
  47
  48 #define TSTR -1 /* shared register */
  49 #define TCR  0 /* channel register */
  50 #define TMDR 1 /* channel register */
  51 #define TIOR 2 /* channel register */
  52 #define TIER 3 /* channel register */
  53 #define TSR  4 /* channel register */
  54 #define TCNT 5 /* channel register */
  55 #define TGR  6 /* channel register */
  56
  57 static unsigned long mtu2_reg_offs[] = {
  58         [TCR] = 0,
  59         [TMDR] = 1,
  60         [TIOR] = 2,
  61         [TIER] = 4,
  62         [TSR] = 5,
  63         [TCNT] = 6,
  64         [TGR] = 8,
  65 };
  66
  67 static inline unsigned long sh_mtu2_read(struct sh_mtu2_priv *p, int reg_nr)
  68 {
  69         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
  70         void __iomem *base = p->mapbase;
  71         unsigned long offs;
  72
  73         if (reg_nr == TSTR)
  74                 return ioread8(base + cfg->channel_offset);
  75
  76         offs = mtu2_reg_offs[reg_nr];
  77
  78         if ((reg_nr == TCNT) || (reg_nr == TGR))
  79                 return ioread16(base + offs);
  80         else
  81                 return ioread8(base + offs);
  82 }
  83
  84 static inline void sh_mtu2_write(struct sh_mtu2_priv *p, int reg_nr,
  85                                 unsigned long value)
  86 {
  87         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
  88         void __iomem *base = p->mapbase;
  89         unsigned long offs;
  90
  91         if (reg_nr == TSTR) {
  92                 iowrite8(value, base + cfg->channel_offset);
  93                 return;
  94         }
  95
  96         offs = mtu2_reg_offs[reg_nr];
  97
  98         if ((reg_nr == TCNT) || (reg_nr == TGR))
  99                 iowrite16(value, base + offs);
 100         else
 101                 iowrite8(value, base + offs);
 102 }
 103
 104 static void sh_mtu2_start_stop_ch(struct sh_mtu2_priv *p, int start)
 105 {
 106         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
 107         unsigned long flags, value;
 108
 109         /* start stop register shared by multiple timer channels */
 110         raw_spin_lock_irqsave(&sh_mtu2_lock, flags);
 111         value = sh_mtu2_read(p, TSTR);
 112
 113         if (start)
 114                 value |= 1 << cfg->timer_bit;
 115         else
 116                 value &= ~(1 << cfg->timer_bit);
 117
 118         sh_mtu2_write(p, TSTR, value);
 119         raw_spin_unlock_irqrestore(&sh_mtu2_lock, flags);
 120 }
 121
 122 static int sh_mtu2_enable(struct sh_mtu2_priv *p)
 123 {
 124         int ret;
 125
 126         /* enable clock */
 127         ret = clk_enable(p->clk);
 128         if (ret) {
 129                 dev_err(&p->pdev->dev, "cannot enable clock\n");
 130                 return ret;
 131         }
 132
 133         /* make sure channel is disabled */
 134         sh_mtu2_start_stop_ch(p, 0);
 135
 136         p->rate = clk_get_rate(p->clk) / 64;
 137         p->periodic = (p->rate + HZ/2) / HZ;
 138
 139         /* "Periodic Counter Operation" */
 140         sh_mtu2_write(p, TCR, 0x23); /* TGRA clear, divide clock by 64 */
 141         sh_mtu2_write(p, TIOR, 0);
 142         sh_mtu2_write(p, TGR, p->periodic);
 143         sh_mtu2_write(p, TCNT, 0);
 144         sh_mtu2_write(p, TMDR, 0);
 145         sh_mtu2_write(p, TIER, 0x01);
 146
 147         /* enable channel */
 148         sh_mtu2_start_stop_ch(p, 1);
 149
 150         return 0;
 151 }
 152
 153 static void sh_mtu2_disable(struct sh_mtu2_priv *p)
 154 {
 155         /* disable channel */
 156         sh_mtu2_start_stop_ch(p, 0);
 157
 158         /* stop clock */
 159         clk_disable(p->clk);
 160 }
 161
 162 static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
 163 {
 164         struct sh_mtu2_priv *p = dev_id;
 165
 166         /* acknowledge interrupt */
 167         sh_mtu2_read(p, TSR);
 168         sh_mtu2_write(p, TSR, 0xfe);
 169
 170         /* notify clockevent layer */
 171         p->ced.event_handler(&p->ced);
 172         return IRQ_HANDLED;
 173 }
 174
 175 static struct sh_mtu2_priv *ced_to_sh_mtu2(struct clock_event_device *ced)
 176 {
 177         return container_of(ced, struct sh_mtu2_priv, ced);
 178 }
 179
 180 static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
 181                                     struct clock_event_device *ced)
 182 {
 183         struct sh_mtu2_priv *p = ced_to_sh_mtu2(ced);
 184         int disabled = 0;
 185
 186         /* deal with old setting first */
 187         switch (ced->mode) {
 188         case CLOCK_EVT_MODE_PERIODIC:
 189                 sh_mtu2_disable(p);
 190                 disabled = 1;
 191                 break;
 192         default:
 193                 break;
 194         }
 195
 196         switch (mode) {
 197         case CLOCK_EVT_MODE_PERIODIC:
 198                 dev_info(&p->pdev->dev, "used for periodic clock events\n");
 199                 sh_mtu2_enable(p);
 200                 break;
 201         case CLOCK_EVT_MODE_UNUSED:
 202                 if (!disabled)
 203                         sh_mtu2_disable(p);
 204                 break;
 205         case CLOCK_EVT_MODE_SHUTDOWN:
 206         default:
 207                 break;
 208         }
 209 }
 210
 211 static void sh_mtu2_register_clockevent(struct sh_mtu2_priv *p,
 212                                        char *name, unsigned long rating)
 213 {
 214         struct clock_event_device *ced = &p->ced;
 215         int ret;
 216
 217         memset(ced, 0, sizeof(*ced));
 218
 219         ced->name = name;
 220         ced->features = CLOCK_EVT_FEAT_PERIODIC;
 221         ced->rating = rating;
 222         ced->cpumask = cpumask_of(0);
 223         ced->set_mode = sh_mtu2_clock_event_mode;
 224
 225         dev_info(&p->pdev->dev, "used for clock events\n");
 226         clockevents_register_device(ced);
 227
 228         ret = setup_irq(p->irqaction.irq, &p->irqaction);
 229         if (ret) {
 230                 dev_err(&p->pdev->dev, "failed to request irq %d\n",
 231                         p->irqaction.irq);
 232                 return;
 233         }
 234 }
 235
 236 static int sh_mtu2_register(struct sh_mtu2_priv *p, char *name,
 237                             unsigned long clockevent_rating)
 238 {
 239         if (clockevent_rating)
 240                 sh_mtu2_register_clockevent(p, name, clockevent_rating);
 241
 242         return 0;
 243 }
 244
 245 static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
 246 {
 247         struct sh_timer_config *cfg = pdev->dev.platform_data;
 248         struct resource *res;
 249         int irq, ret;
 250         ret = -ENXIO;
 251
 252         memset(p, 0, sizeof(*p));
 253         p->pdev = pdev;
 254
 255         if (!cfg) {
 256                 dev_err(&p->pdev->dev, "missing platform data\n");
 257                 goto err0;
 258         }
 259
 260         platform_set_drvdata(pdev, p);
 261
 262         res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
 263         if (!res) {
 264                 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
 265                 goto err0;
 266         }
 267
 268         irq = platform_get_irq(p->pdev, 0);
 269         if (irq < 0) {
 270                 dev_err(&p->pdev->dev, "failed to get irq\n");
 271                 goto err0;
 272         }
 273
 274         /* map memory, let mapbase point to our channel */
 275         p->mapbase = ioremap_nocache(res->start, resource_size(res));
 276         if (p->mapbase == NULL) {
 277                 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
 278                 goto err0;
 279         }
 280
 281         /* setup data for setup_irq() (too early for request_irq()) */
 282         p->irqaction.name = dev_name(&p->pdev->dev);
 283         p->irqaction.handler = sh_mtu2_interrupt;
 284         p->irqaction.dev_id = p;
 285         p->irqaction.irq = irq;
 286         p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
 287                              IRQF_IRQPOLL  | IRQF_NOBALANCING;
 288
 289         /* get hold of clock */
 290         p->clk = clk_get(&p->pdev->dev, "mtu2_fck");
 291         if (IS_ERR(p->clk)) {
 292                 dev_err(&p->pdev->dev, "cannot get clock\n");
 293                 ret = PTR_ERR(p->clk);
 294                 goto err1;
 295         }
 296
 297         return sh_mtu2_register(p, (char *)dev_name(&p->pdev->dev),
 298                                 cfg->clockevent_rating);
 299  err1:
 300         iounmap(p->mapbase);
 301  err0:
 302         return ret;
 303 }
 304
 305 static int __devinit sh_mtu2_probe(struct platform_device *pdev)
 306 {
 307         struct sh_mtu2_priv *p = platform_get_drvdata(pdev);
 308         int ret;
 309
 310         if (!is_early_platform_device(pdev))
 311                 pm_genpd_dev_always_on(&pdev->dev, true);
 312
 313         if (p) {
 314                 dev_info(&pdev->dev, "kept as earlytimer\n");
 315                 return 0;
 316         }
 317
 318         p = kmalloc(sizeof(*p), GFP_KERNEL);
 319         if (p == NULL) {
 320                 dev_err(&pdev->dev, "failed to allocate driver data\n");
 321                 return -ENOMEM;
 322         }
 323
 324         ret = sh_mtu2_setup(p, pdev);
 325         if (ret) {
 326                 kfree(p);
 327                 platform_set_drvdata(pdev, NULL);
 328         }
 329         return ret;
 330 }
 331
 332 static int __devexit sh_mtu2_remove(struct platform_device *pdev)
 333 {
 334         return -EBUSY; /* cannot unregister clockevent */
 335 }
 336
 337 static struct platform_driver sh_mtu2_device_driver = {
 338         .probe          = sh_mtu2_probe,
 339         .remove         = __devexit_p(sh_mtu2_remove),
 340         .driver         = {
 341                 .name   = "sh_mtu2",
 342         }
 343 };
 344
 345 static int __init sh_mtu2_init(void)
 346 {
 347         return platform_driver_register(&sh_mtu2_device_driver);
 348 }
 349
 350 static void __exit sh_mtu2_exit(void)
 351 {
 352         platform_driver_unregister(&sh_mtu2_device_driver);
 353 }
 354
 355 early_platform_init("earlytimer", &sh_mtu2_device_driver);
 356 module_init(sh_mtu2_init);
 357 module_exit(sh_mtu2_exit);
 358
 359 MODULE_AUTHOR("Magnus Damm");
 360 MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
 361 MODULE_LICENSE("GPL v2");