drivers/clocksource/time-pistachio.c

   1 /*
   2  * Pistachio clocksource based on general-purpose timers
   3  *
   4  * Copyright (C) 2015 Imagination Technologies
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License. See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #define pr_fmt(fmt) "%s: " fmt, __func__
  12
  13 #include <linux/clk.h>
  14 #include <linux/clocksource.h>
  15 #include <linux/clockchips.h>
  16 #include <linux/delay.h>
  17 #include <linux/err.h>
  18 #include <linux/init.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/mfd/syscon.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/regmap.h>
  25 #include <linux/sched_clock.h>
  26 #include <linux/time.h>
  27
  28 /* Top level reg */
  29 #define CR_TIMER_CTRL_CFG               0x00
  30 #define TIMER_ME_GLOBAL                 BIT(0)
  31 #define CR_TIMER_REV                    0x10
  32
  33 /* Timer specific registers */
  34 #define TIMER_CFG                       0x20
  35 #define TIMER_ME_LOCAL                  BIT(0)
  36 #define TIMER_RELOAD_VALUE              0x24
  37 #define TIMER_CURRENT_VALUE             0x28
  38 #define TIMER_CURRENT_OVERFLOW_VALUE    0x2C
  39 #define TIMER_IRQ_STATUS                0x30
  40 #define TIMER_IRQ_CLEAR                 0x34
  41 #define TIMER_IRQ_MASK                  0x38
  42
  43 #define PERIP_TIMER_CONTROL             0x90
  44
  45 /* Timer specific configuration Values */
  46 #define RELOAD_VALUE                    0xffffffff
  47
  48 struct pistachio_clocksource {
  49         void __iomem *base;
  50         raw_spinlock_t lock;
  51         struct clocksource cs;
  52 };
  53
  54 static struct pistachio_clocksource pcs_gpt;
  55
  56 #define to_pistachio_clocksource(cs)    \
  57         container_of(cs, struct pistachio_clocksource, cs)
  58
  59 static inline u32 gpt_readl(void __iomem *base, u32 offset, u32 gpt_id)
  60 {
  61         return readl(base + 0x20 * gpt_id + offset);
  62 }
  63
  64 static inline void gpt_writel(void __iomem *base, u32 value, u32 offset,
  65                 u32 gpt_id)
  66 {
  67         writel(value, base + 0x20 * gpt_id + offset);
  68 }
  69
  70 static cycle_t pistachio_clocksource_read_cycles(struct clocksource *cs)
  71 {
  72         struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);
  73         u32 counter, overflw;
  74         unsigned long flags;
  75
  76         /*
  77          * The counter value is only refreshed after the overflow value is read.
  78          * And they must be read in strict order, hence raw spin lock added.
  79          */
  80
  81         raw_spin_lock_irqsave(&pcs->lock, flags);
  82         overflw = gpt_readl(pcs->base, TIMER_CURRENT_OVERFLOW_VALUE, 0);
  83         counter = gpt_readl(pcs->base, TIMER_CURRENT_VALUE, 0);
  84         raw_spin_unlock_irqrestore(&pcs->lock, flags);
  85
  86         return ~(cycle_t)counter;
  87 }
  88
  89 static u64 notrace pistachio_read_sched_clock(void)
  90 {
  91         return pistachio_clocksource_read_cycles(&pcs_gpt.cs);
  92 }
  93
  94 static void pistachio_clksrc_set_mode(struct clocksource *cs, int timeridx,
  95                         int enable)
  96 {
  97         struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);
  98         u32 val;
  99
 100         val = gpt_readl(pcs->base, TIMER_CFG, timeridx);
 101         if (enable)
 102                 val |= TIMER_ME_LOCAL;
 103         else
 104                 val &= ~TIMER_ME_LOCAL;
 105
 106         gpt_writel(pcs->base, val, TIMER_CFG, timeridx);
 107 }
 108
 109 static void pistachio_clksrc_enable(struct clocksource *cs, int timeridx)
 110 {
 111         struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);
 112
 113         /* Disable GPT local before loading reload value */
 114         pistachio_clksrc_set_mode(cs, timeridx, false);
 115         gpt_writel(pcs->base, RELOAD_VALUE, TIMER_RELOAD_VALUE, timeridx);
 116         pistachio_clksrc_set_mode(cs, timeridx, true);
 117 }
 118
 119 static void pistachio_clksrc_disable(struct clocksource *cs, int timeridx)
 120 {
 121         /* Disable GPT local */
 122         pistachio_clksrc_set_mode(cs, timeridx, false);
 123 }
 124
 125 static int pistachio_clocksource_enable(struct clocksource *cs)
 126 {
 127         pistachio_clksrc_enable(cs, 0);
 128         return 0;
 129 }
 130
 131 static void pistachio_clocksource_disable(struct clocksource *cs)
 132 {
 133         pistachio_clksrc_disable(cs, 0);
 134 }
 135
 136 /* Desirable clock source for pistachio platform */
 137 static struct pistachio_clocksource pcs_gpt = {
 138         .cs =   {
 139                 .name           = "gptimer",
 140                 .rating         = 300,
 141                 .enable         = pistachio_clocksource_enable,
 142                 .disable        = pistachio_clocksource_disable,
 143                 .read           = pistachio_clocksource_read_cycles,
 144                 .mask           = CLOCKSOURCE_MASK(32),
 145                 .flags          = CLOCK_SOURCE_IS_CONTINUOUS |
 146                                   CLOCK_SOURCE_SUSPEND_NONSTOP,
 147                 },
 148 };
 149
 150 static void __init pistachio_clksrc_of_init(struct device_node *node)
 151 {
 152         struct clk *sys_clk, *fast_clk;
 153         struct regmap *periph_regs;
 154         unsigned long rate;
 155         int ret;
 156
 157         pcs_gpt.base = of_iomap(node, 0);
 158         if (!pcs_gpt.base) {
 159                 pr_err("cannot iomap\n");
 160                 return;
 161         }
 162
 163         periph_regs = syscon_regmap_lookup_by_phandle(node, "img,cr-periph");
 164         if (IS_ERR(periph_regs)) {
 165                 pr_err("cannot get peripheral regmap (%lu)\n",
 166                        PTR_ERR(periph_regs));
 167                 return;
 168         }
 169
 170         /* Switch to using the fast counter clock */
 171         ret = regmap_update_bits(periph_regs, PERIP_TIMER_CONTROL,
 172                                  0xf, 0x0);
 173         if (ret)
 174                 return;
 175
 176         sys_clk = of_clk_get_by_name(node, "sys");
 177         if (IS_ERR(sys_clk)) {
 178                 pr_err("clock get failed (%lu)\n", PTR_ERR(sys_clk));
 179                 return;
 180         }
 181
 182         fast_clk = of_clk_get_by_name(node, "fast");
 183         if (IS_ERR(fast_clk)) {
 184                 pr_err("clock get failed (%lu)\n", PTR_ERR(fast_clk));
 185                 return;
 186         }
 187
 188         ret = clk_prepare_enable(sys_clk);
 189         if (ret < 0) {
 190                 pr_err("failed to enable clock (%d)\n", ret);
 191                 return;
 192         }
 193
 194         ret = clk_prepare_enable(fast_clk);
 195         if (ret < 0) {
 196                 pr_err("failed to enable clock (%d)\n", ret);
 197                 clk_disable_unprepare(sys_clk);
 198                 return;
 199         }
 200
 201         rate = clk_get_rate(fast_clk);
 202
 203         /* Disable irq's for clocksource usage */
 204         gpt_writel(&pcs_gpt.base, 0, TIMER_IRQ_MASK, 0);
 205         gpt_writel(&pcs_gpt.base, 0, TIMER_IRQ_MASK, 1);
 206         gpt_writel(&pcs_gpt.base, 0, TIMER_IRQ_MASK, 2);
 207         gpt_writel(&pcs_gpt.base, 0, TIMER_IRQ_MASK, 3);
 208
 209         /* Enable timer block */
 210         writel(TIMER_ME_GLOBAL, pcs_gpt.base);
 211
 212         raw_spin_lock_init(&pcs_gpt.lock);
 213         sched_clock_register(pistachio_read_sched_clock, 32, rate);
 214         clocksource_register_hz(&pcs_gpt.cs, rate);
 215 }
 216 CLOCKSOURCE_OF_DECLARE(pistachio_gptimer, "img,pistachio-gptimer",
 217                        pistachio_clksrc_of_init);