drivers/cpufreq/exynos-cpufreq.h

   1 /*
   2  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS - CPUFreq support
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 enum cpufreq_level_index {
  13         L0, L1, L2, L3, L4,
  14         L5, L6, L7, L8, L9,
  15         L10, L11, L12, L13, L14,
  16         L15, L16, L17, L18, L19,
  17         L20,
  18 };
  19
  20 enum exynos_soc_type {
  21         EXYNOS_SOC_4210,
  22         EXYNOS_SOC_4212,
  23         EXYNOS_SOC_4412,
  24         EXYNOS_SOC_5250,
  25 };
  26
  27 #define APLL_FREQ(f, a0, a1, a2, a3, a4, a5, a6, a7, b0, b1, b2, m, p, s) \
  28         { \
  29                 .freq = (f) * 1000, \
  30                 .clk_div_cpu0 = ((a0) | (a1) << 4 | (a2) << 8 | (a3) << 12 | \
  31                         (a4) << 16 | (a5) << 20 | (a6) << 24 | (a7) << 28), \
  32                 .clk_div_cpu1 = (b0 << 0 | b1 << 4 | b2 << 8), \
  33                 .mps = ((m) << 16 | (p) << 8 | (s)), \
  34         }
  35
  36 struct apll_freq {
  37         unsigned int freq;
  38         u32 clk_div_cpu0;
  39         u32 clk_div_cpu1;
  40         u32 mps;
  41 };
  42
  43 struct exynos_dvfs_info {
  44         enum exynos_soc_type type;
  45         struct device   *dev;
  46         unsigned long   mpll_freq_khz;
  47         unsigned int    pll_safe_idx;
  48         struct clk      *cpu_clk;
  49         unsigned int    *volt_table;
  50         struct cpufreq_frequency_table  *freq_table;
  51         void (*set_freq)(unsigned int, unsigned int);
  52         bool (*need_apll_change)(unsigned int, unsigned int);
  53         void __iomem    *cmu_regs;
  54 };
  55
  56 #ifdef CONFIG_ARM_EXYNOS4210_CPUFREQ
  57 extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *);
  58 #else
  59 static inline int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
  60 {
  61         return -EOPNOTSUPP;
  62 }
  63 #endif
  64 #ifdef CONFIG_ARM_EXYNOS4X12_CPUFREQ
  65 extern int exynos4x12_cpufreq_init(struct exynos_dvfs_info *);
  66 #else
  67 static inline int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
  68 {
  69         return -EOPNOTSUPP;
  70 }
  71 #endif
  72 #ifdef CONFIG_ARM_EXYNOS5250_CPUFREQ
  73 extern int exynos5250_cpufreq_init(struct exynos_dvfs_info *);
  74 #else
  75 static inline int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
  76 {
  77         return -EOPNOTSUPP;
  78 }
  79 #endif
  80
  81 #define EXYNOS4_CLKSRC_CPU                      0x14200
  82 #define EXYNOS4_CLKMUX_STATCPU                  0x14400
  83
  84 #define EXYNOS4_CLKDIV_CPU                      0x14500
  85 #define EXYNOS4_CLKDIV_CPU1                     0x14504
  86 #define EXYNOS4_CLKDIV_STATCPU                  0x14600
  87 #define EXYNOS4_CLKDIV_STATCPU1                 0x14604
  88
  89 #define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT        (16)
  90 #define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK     (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT)
  91
  92 #define EXYNOS5_APLL_LOCK                       0x00000
  93 #define EXYNOS5_APLL_CON0                       0x00100
  94 #define EXYNOS5_CLKMUX_STATCPU                  0x00400
  95 #define EXYNOS5_CLKDIV_CPU0                     0x00500
  96 #define EXYNOS5_CLKDIV_CPU1                     0x00504
  97 #define EXYNOS5_CLKDIV_STATCPU0                 0x00600
  98 #define EXYNOS5_CLKDIV_STATCPU1                 0x00604