drivers/cpufreq/exynos4210-cpufreq.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS4210 - CPU frequency scaling support
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/err.h>
  15 #include <linux/clk.h>
  16 #include <linux/io.h>
  17 #include <linux/slab.h>
  18 #include <linux/cpufreq.h>
  19 #include <linux/of.h>
  20 #include <linux/of_address.h>
  21
  22 #include "exynos-cpufreq.h"
  23
  24 static struct clk *cpu_clk;
  25 static struct clk *moutcore;
  26 static struct clk *mout_mpll;
  27 static struct clk *mout_apll;
  28 static struct exynos_dvfs_info *cpufreq;
  29
  30 static unsigned int exynos4210_volt_table[] = {
  31         1250000, 1150000, 1050000, 975000, 950000,
  32 };
  33
  34 static struct cpufreq_frequency_table exynos4210_freq_table[] = {
  35         {0, L0, 1200 * 1000},
  36         {0, L1, 1000 * 1000},
  37         {0, L2,  800 * 1000},
  38         {0, L3,  500 * 1000},
  39         {0, L4,  200 * 1000},
  40         {0, 0, CPUFREQ_TABLE_END},
  41 };
  42
  43 static struct apll_freq apll_freq_4210[] = {
  44         /*
  45          * values:
  46          * freq
  47          * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, RESERVED
  48          * clock divider for COPY, HPM, RESERVED
  49          * PLL M, P, S
  50          */
  51         APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1),
  52         APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1),
  53         APLL_FREQ(800,  0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1),
  54         APLL_FREQ(500,  0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2),
  55         APLL_FREQ(200,  0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3),
  56 };
  57
  58 static void exynos4210_set_clkdiv(unsigned int div_index)
  59 {
  60         unsigned int tmp;
  61
  62         /* Change Divider - CPU0 */
  63
  64         tmp = apll_freq_4210[div_index].clk_div_cpu0;
  65
  66         __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU);
  67
  68         do {
  69                 tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU);
  70         } while (tmp & 0x1111111);
  71
  72         /* Change Divider - CPU1 */
  73
  74         tmp = apll_freq_4210[div_index].clk_div_cpu1;
  75
  76         __raw_writel(tmp, cpufreq->cmu_regs + EXYNOS4_CLKDIV_CPU1);
  77
  78         do {
  79                 tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKDIV_STATCPU1);
  80         } while (tmp & 0x11);
  81 }
  82
  83 static void exynos4210_set_apll(unsigned int index)
  84 {
  85         unsigned int tmp, freq = apll_freq_4210[index].freq;
  86
  87         /* MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
  88         clk_set_parent(moutcore, mout_mpll);
  89
  90         do {
  91                 tmp = (__raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU)
  92                         >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
  93                 tmp &= 0x7;
  94         } while (tmp != 0x2);
  95
  96         clk_set_rate(mout_apll, freq * 1000);
  97
  98         /* MUX_CORE_SEL = APLL */
  99         clk_set_parent(moutcore, mout_apll);
 100
 101         do {
 102                 tmp = __raw_readl(cpufreq->cmu_regs + EXYNOS4_CLKMUX_STATCPU);
 103                 tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
 104         } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
 105 }
 106
 107 static void exynos4210_set_frequency(unsigned int old_index,
 108                                      unsigned int new_index)
 109 {
 110         if (old_index > new_index) {
 111                 exynos4210_set_clkdiv(new_index);
 112                 exynos4210_set_apll(new_index);
 113         } else if (old_index < new_index) {
 114                 exynos4210_set_apll(new_index);
 115                 exynos4210_set_clkdiv(new_index);
 116         }
 117 }
 118
 119 int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
 120 {
 121         struct device_node *np;
 122         unsigned long rate;
 123
 124         /*
 125          * HACK: This is a temporary workaround to get access to clock
 126          * controller registers directly and remove static mappings and
 127          * dependencies on platform headers. It is necessary to enable
 128          * Exynos multi-platform support and will be removed together with
 129          * this whole driver as soon as Exynos gets migrated to use
 130          * cpufreq-dt driver.
 131          */
 132         np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-clock");
 133         if (!np) {
 134                 pr_err("%s: failed to find clock controller DT node\n",
 135                         __func__);
 136                 return -ENODEV;
 137         }
 138
 139         info->cmu_regs = of_iomap(np, 0);
 140         if (!info->cmu_regs) {
 141                 pr_err("%s: failed to map CMU registers\n", __func__);
 142                 return -EFAULT;
 143         }
 144
 145         cpu_clk = clk_get(NULL, "armclk");
 146         if (IS_ERR(cpu_clk))
 147                 return PTR_ERR(cpu_clk);
 148
 149         moutcore = clk_get(NULL, "moutcore");
 150         if (IS_ERR(moutcore))
 151                 goto err_moutcore;
 152
 153         mout_mpll = clk_get(NULL, "mout_mpll");
 154         if (IS_ERR(mout_mpll))
 155                 goto err_mout_mpll;
 156
 157         rate = clk_get_rate(mout_mpll) / 1000;
 158
 159         mout_apll = clk_get(NULL, "mout_apll");
 160         if (IS_ERR(mout_apll))
 161                 goto err_mout_apll;
 162
 163         info->mpll_freq_khz = rate;
 164         /* 800Mhz */
 165         info->pll_safe_idx = L2;
 166         info->cpu_clk = cpu_clk;
 167         info->volt_table = exynos4210_volt_table;
 168         info->freq_table = exynos4210_freq_table;
 169         info->set_freq = exynos4210_set_frequency;
 170
 171         cpufreq = info;
 172
 173         return 0;
 174
 175 err_mout_apll:
 176         clk_put(mout_mpll);
 177 err_mout_mpll:
 178         clk_put(moutcore);
 179 err_moutcore:
 180         clk_put(cpu_clk);
 181
 182         pr_debug("%s: failed initialization\n", __func__);
 183         return -EINVAL;
 184 }