drivers/cpufreq/exynos4210-cpufreq.c

   1 /*
   2  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * EXYNOS4210 - CPU frequency scaling support
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/err.h>
  15 #include <linux/clk.h>
  16 #include <linux/io.h>
  17 #include <linux/slab.h>
  18 #include <linux/cpufreq.h>
  19
  20 #include <mach/regs-clock.h>
  21
  22 #include "exynos-cpufreq.h"
  23
  24 #define CPUFREQ_LEVEL_END       L5
  25
  26 static int max_support_idx = L0;
  27 static int min_support_idx = (CPUFREQ_LEVEL_END - 1);
  28
  29 static struct clk *cpu_clk;
  30 static struct clk *moutcore;
  31 static struct clk *mout_mpll;
  32 static struct clk *mout_apll;
  33
  34 struct cpufreq_clkdiv {
  35         unsigned int index;
  36         unsigned int clkdiv;
  37 };
  38
  39 static unsigned int exynos4210_volt_table[CPUFREQ_LEVEL_END] = {
  40         1250000, 1150000, 1050000, 975000, 950000,
  41 };
  42
  43
  44 static struct cpufreq_clkdiv exynos4210_clkdiv_table[CPUFREQ_LEVEL_END];
  45
  46 static struct cpufreq_frequency_table exynos4210_freq_table[] = {
  47         {L0, 1200*1000},
  48         {L1, 1000*1000},
  49         {L2, 800*1000},
  50         {L3, 500*1000},
  51         {L4, 200*1000},
  52         {0, CPUFREQ_TABLE_END},
  53 };
  54
  55 static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
  56         /*
  57          * Clock divider value for following
  58          * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
  59          *              DIVATB, DIVPCLK_DBG, DIVAPLL }
  60          */
  61
  62         /* ARM L0: 1200MHz */
  63         { 0, 3, 7, 3, 4, 1, 7 },
  64
  65         /* ARM L1: 1000MHz */
  66         { 0, 3, 7, 3, 4, 1, 7 },
  67
  68         /* ARM L2: 800MHz */
  69         { 0, 3, 7, 3, 3, 1, 7 },
  70
  71         /* ARM L3: 500MHz */
  72         { 0, 3, 7, 3, 3, 1, 7 },
  73
  74         /* ARM L4: 200MHz */
  75         { 0, 1, 3, 1, 3, 1, 0 },
  76 };
  77
  78 static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
  79         /*
  80          * Clock divider value for following
  81          * { DIVCOPY, DIVHPM }
  82          */
  83
  84         /* ARM L0: 1200MHz */
  85         { 5, 0 },
  86
  87         /* ARM L1: 1000MHz */
  88         { 4, 0 },
  89
  90         /* ARM L2: 800MHz */
  91         { 3, 0 },
  92
  93         /* ARM L3: 500MHz */
  94         { 3, 0 },
  95
  96         /* ARM L4: 200MHz */
  97         { 3, 0 },
  98 };
  99
 100 static unsigned int exynos4210_apll_pms_table[CPUFREQ_LEVEL_END] = {
 101         /* APLL FOUT L0: 1200MHz */
 102         ((150 << 16) | (3 << 8) | 1),
 103
 104         /* APLL FOUT L1: 1000MHz */
 105         ((250 << 16) | (6 << 8) | 1),
 106
 107         /* APLL FOUT L2: 800MHz */
 108         ((200 << 16) | (6 << 8) | 1),
 109
 110         /* APLL FOUT L3: 500MHz */
 111         ((250 << 16) | (6 << 8) | 2),
 112
 113         /* APLL FOUT L4: 200MHz */
 114         ((200 << 16) | (6 << 8) | 3),
 115 };
 116
 117 static void exynos4210_set_clkdiv(unsigned int div_index)
 118 {
 119         unsigned int tmp;
 120
 121         /* Change Divider - CPU0 */
 122
 123         tmp = exynos4210_clkdiv_table[div_index].clkdiv;
 124
 125         __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
 126
 127         do {
 128                 tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU);
 129         } while (tmp & 0x1111111);
 130
 131         /* Change Divider - CPU1 */
 132
 133         tmp = __raw_readl(EXYNOS4_CLKDIV_CPU1);
 134
 135         tmp &= ~((0x7 << 4) | 0x7);
 136
 137         tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
 138                 (clkdiv_cpu1[div_index][1] << 0));
 139
 140         __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
 141
 142         do {
 143                 tmp = __raw_readl(EXYNOS4_CLKDIV_STATCPU1);
 144         } while (tmp & 0x11);
 145 }
 146
 147 static void exynos4210_set_apll(unsigned int index)
 148 {
 149         unsigned int tmp;
 150
 151         /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
 152         clk_set_parent(moutcore, mout_mpll);
 153
 154         do {
 155                 tmp = (__raw_readl(EXYNOS4_CLKMUX_STATCPU)
 156                         >> EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT);
 157                 tmp &= 0x7;
 158         } while (tmp != 0x2);
 159
 160         /* 2. Set APLL Lock time */
 161         __raw_writel(EXYNOS4_APLL_LOCKTIME, EXYNOS4_APLL_LOCK);
 162
 163         /* 3. Change PLL PMS values */
 164         tmp = __raw_readl(EXYNOS4_APLL_CON0);
 165         tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
 166         tmp |= exynos4210_apll_pms_table[index];
 167         __raw_writel(tmp, EXYNOS4_APLL_CON0);
 168
 169         /* 4. wait_lock_time */
 170         do {
 171                 tmp = __raw_readl(EXYNOS4_APLL_CON0);
 172         } while (!(tmp & (0x1 << EXYNOS4_APLLCON0_LOCKED_SHIFT)));
 173
 174         /* 5. MUX_CORE_SEL = APLL */
 175         clk_set_parent(moutcore, mout_apll);
 176
 177         do {
 178                 tmp = __raw_readl(EXYNOS4_CLKMUX_STATCPU);
 179                 tmp &= EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK;
 180         } while (tmp != (0x1 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT));
 181 }
 182
 183 bool exynos4210_pms_change(unsigned int old_index, unsigned int new_index)
 184 {
 185         unsigned int old_pm = (exynos4210_apll_pms_table[old_index] >> 8);
 186         unsigned int new_pm = (exynos4210_apll_pms_table[new_index] >> 8);
 187
 188         return (old_pm == new_pm) ? 0 : 1;
 189 }
 190
 191 static void exynos4210_set_frequency(unsigned int old_index,
 192                                      unsigned int new_index)
 193 {
 194         unsigned int tmp;
 195
 196         if (old_index > new_index) {
 197                 if (!exynos4210_pms_change(old_index, new_index)) {
 198                         /* 1. Change the system clock divider values */
 199                         exynos4210_set_clkdiv(new_index);
 200
 201                         /* 2. Change just s value in apll m,p,s value */
 202                         tmp = __raw_readl(EXYNOS4_APLL_CON0);
 203                         tmp &= ~(0x7 << 0);
 204                         tmp |= (exynos4210_apll_pms_table[new_index] & 0x7);
 205                         __raw_writel(tmp, EXYNOS4_APLL_CON0);
 206                 } else {
 207                         /* Clock Configuration Procedure */
 208                         /* 1. Change the system clock divider values */
 209                         exynos4210_set_clkdiv(new_index);
 210                         /* 2. Change the apll m,p,s value */
 211                         exynos4210_set_apll(new_index);
 212                 }
 213         } else if (old_index < new_index) {
 214                 if (!exynos4210_pms_change(old_index, new_index)) {
 215                         /* 1. Change just s value in apll m,p,s value */
 216                         tmp = __raw_readl(EXYNOS4_APLL_CON0);
 217                         tmp &= ~(0x7 << 0);
 218                         tmp |= (exynos4210_apll_pms_table[new_index] & 0x7);
 219                         __raw_writel(tmp, EXYNOS4_APLL_CON0);
 220
 221                         /* 2. Change the system clock divider values */
 222                         exynos4210_set_clkdiv(new_index);
 223                 } else {
 224                         /* Clock Configuration Procedure */
 225                         /* 1. Change the apll m,p,s value */
 226                         exynos4210_set_apll(new_index);
 227                         /* 2. Change the system clock divider values */
 228                         exynos4210_set_clkdiv(new_index);
 229                 }
 230         }
 231 }
 232
 233 int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
 234 {
 235         int i;
 236         unsigned int tmp;
 237         unsigned long rate;
 238
 239         cpu_clk = clk_get(NULL, "armclk");
 240         if (IS_ERR(cpu_clk))
 241                 return PTR_ERR(cpu_clk);
 242
 243         moutcore = clk_get(NULL, "moutcore");
 244         if (IS_ERR(moutcore))
 245                 goto err_moutcore;
 246
 247         mout_mpll = clk_get(NULL, "mout_mpll");
 248         if (IS_ERR(mout_mpll))
 249                 goto err_mout_mpll;
 250
 251         rate = clk_get_rate(mout_mpll) / 1000;
 252
 253         mout_apll = clk_get(NULL, "mout_apll");
 254         if (IS_ERR(mout_apll))
 255                 goto err_mout_apll;
 256
 257         tmp = __raw_readl(EXYNOS4_CLKDIV_CPU);
 258
 259         for (i = L0; i <  CPUFREQ_LEVEL_END; i++) {
 260                 tmp &= ~(EXYNOS4_CLKDIV_CPU0_CORE_MASK |
 261                         EXYNOS4_CLKDIV_CPU0_COREM0_MASK |
 262                         EXYNOS4_CLKDIV_CPU0_COREM1_MASK |
 263                         EXYNOS4_CLKDIV_CPU0_PERIPH_MASK |
 264                         EXYNOS4_CLKDIV_CPU0_ATB_MASK |
 265                         EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK |
 266                         EXYNOS4_CLKDIV_CPU0_APLL_MASK);
 267
 268                 tmp |= ((clkdiv_cpu0[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
 269                         (clkdiv_cpu0[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
 270                         (clkdiv_cpu0[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
 271                         (clkdiv_cpu0[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
 272                         (clkdiv_cpu0[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
 273                         (clkdiv_cpu0[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
 274                         (clkdiv_cpu0[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT));
 275
 276                 exynos4210_clkdiv_table[i].clkdiv = tmp;
 277         }
 278
 279         info->mpll_freq_khz = rate;
 280         info->pm_lock_idx = L2;
 281         info->pll_safe_idx = L2;
 282         info->max_support_idx = max_support_idx;
 283         info->min_support_idx = min_support_idx;
 284         info->cpu_clk = cpu_clk;
 285         info->volt_table = exynos4210_volt_table;
 286         info->freq_table = exynos4210_freq_table;
 287         info->set_freq = exynos4210_set_frequency;
 288         info->need_apll_change = exynos4210_pms_change;
 289
 290         return 0;
 291
 292 err_mout_apll:
 293         if (!IS_ERR(mout_mpll))
 294                 clk_put(mout_mpll);
 295 err_mout_mpll:
 296         if (!IS_ERR(moutcore))
 297                 clk_put(moutcore);
 298 err_moutcore:
 299         if (!IS_ERR(cpu_clk))
 300                 clk_put(cpu_clk);
 301
 302         pr_debug("%s: failed initialization\n", __func__);
 303         return -EINVAL;
 304 }
 305 EXPORT_SYMBOL(exynos4210_cpufreq_init);