2 * intel_pstate.c: Native P state management for Intel processors
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #include <linux/kernel.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/module.h>
16 #include <linux/ktime.h>
17 #include <linux/hrtimer.h>
18 #include <linux/tick.h>
19 #include <linux/slab.h>
20 #include <linux/sched.h>
21 #include <linux/list.h>
22 #include <linux/cpu.h>
23 #include <linux/cpufreq.h>
24 #include <linux/sysfs.h>
25 #include <linux/types.h>
27 #include <linux/debugfs.h>
28 #include <linux/acpi.h>
29 #include <trace/events/power.h>
31 #include <asm/div64.h>
33 #include <asm/cpu_device_id.h>
35 #define BYT_RATIOS 0x66a
36 #define BYT_VIDS 0x66b
37 #define BYT_TURBO_RATIOS 0x66c
38 #define BYT_TURBO_VIDS 0x66d
41 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
42 #define fp_toint(X) ((X) >> FRAC_BITS)
45 static inline int32_t mul_fp(int32_t x
, int32_t y
)
47 return ((int64_t)x
* (int64_t)y
) >> FRAC_BITS
;
50 static inline int32_t div_fp(int32_t x
, int32_t y
)
52 return div_s64((int64_t)x
<< FRAC_BITS
, y
);
55 static inline int ceiling_fp(int32_t x
)
60 mask
= (1 << FRAC_BITS
) - 1;
67 int32_t core_pct_busy
;
102 struct timer_list timer
;
104 struct pstate_data pstate
;
108 ktime_t last_sample_time
;
111 struct sample sample
;
114 static struct cpudata
**all_cpu_data
;
115 struct pstate_adjust_policy
{
124 struct pstate_funcs
{
125 int (*get_max
)(void);
126 int (*get_min
)(void);
127 int (*get_turbo
)(void);
128 int (*get_scaling
)(void);
129 void (*set
)(struct cpudata
*, int pstate
);
130 void (*get_vid
)(struct cpudata
*);
133 struct cpu_defaults
{
134 struct pstate_adjust_policy pid_policy
;
135 struct pstate_funcs funcs
;
138 static struct pstate_adjust_policy pid_params
;
139 static struct pstate_funcs pstate_funcs
;
140 static int hwp_active
;
153 static struct perf_limits limits
= {
157 .max_perf
= int_tofp(1),
160 .max_policy_pct
= 100,
161 .max_sysfs_pct
= 100,
164 static inline void pid_reset(struct _pid
*pid
, int setpoint
, int busy
,
165 int deadband
, int integral
) {
166 pid
->setpoint
= setpoint
;
167 pid
->deadband
= deadband
;
168 pid
->integral
= int_tofp(integral
);
169 pid
->last_err
= int_tofp(setpoint
) - int_tofp(busy
);
172 static inline void pid_p_gain_set(struct _pid
*pid
, int percent
)
174 pid
->p_gain
= div_fp(int_tofp(percent
), int_tofp(100));
177 static inline void pid_i_gain_set(struct _pid
*pid
, int percent
)
179 pid
->i_gain
= div_fp(int_tofp(percent
), int_tofp(100));
182 static inline void pid_d_gain_set(struct _pid
*pid
, int percent
)
184 pid
->d_gain
= div_fp(int_tofp(percent
), int_tofp(100));
187 static signed int pid_calc(struct _pid
*pid
, int32_t busy
)
190 int32_t pterm
, dterm
, fp_error
;
191 int32_t integral_limit
;
193 fp_error
= int_tofp(pid
->setpoint
) - busy
;
195 if (abs(fp_error
) <= int_tofp(pid
->deadband
))
198 pterm
= mul_fp(pid
->p_gain
, fp_error
);
200 pid
->integral
+= fp_error
;
203 * We limit the integral here so that it will never
204 * get higher than 30. This prevents it from becoming
205 * too large an input over long periods of time and allows
206 * it to get factored out sooner.
208 * The value of 30 was chosen through experimentation.
210 integral_limit
= int_tofp(30);
211 if (pid
->integral
> integral_limit
)
212 pid
->integral
= integral_limit
;
213 if (pid
->integral
< -integral_limit
)
214 pid
->integral
= -integral_limit
;
216 dterm
= mul_fp(pid
->d_gain
, fp_error
- pid
->last_err
);
217 pid
->last_err
= fp_error
;
219 result
= pterm
+ mul_fp(pid
->integral
, pid
->i_gain
) + dterm
;
220 result
= result
+ (1 << (FRAC_BITS
-1));
221 return (signed int)fp_toint(result
);
224 static inline void intel_pstate_busy_pid_reset(struct cpudata
*cpu
)
226 pid_p_gain_set(&cpu
->pid
, pid_params
.p_gain_pct
);
227 pid_d_gain_set(&cpu
->pid
, pid_params
.d_gain_pct
);
228 pid_i_gain_set(&cpu
->pid
, pid_params
.i_gain_pct
);
230 pid_reset(&cpu
->pid
, pid_params
.setpoint
, 100, pid_params
.deadband
, 0);
233 static inline void intel_pstate_reset_all_pid(void)
237 for_each_online_cpu(cpu
) {
238 if (all_cpu_data
[cpu
])
239 intel_pstate_busy_pid_reset(all_cpu_data
[cpu
]);
243 static inline void update_turbo_state(void)
248 cpu
= all_cpu_data
[0];
249 rdmsrl(MSR_IA32_MISC_ENABLE
, misc_en
);
250 limits
.turbo_disabled
=
251 (misc_en
& MSR_IA32_MISC_ENABLE_TURBO_DISABLE
||
252 cpu
->pstate
.max_pstate
== cpu
->pstate
.turbo_pstate
);
255 #define PCT_TO_HWP(x) (x * 255 / 100)
256 static void intel_pstate_hwp_set(void)
263 for_each_online_cpu(cpu
) {
264 rdmsrl_on_cpu(cpu
, MSR_HWP_REQUEST
, &value
);
265 min
= PCT_TO_HWP(limits
.min_perf_pct
);
266 value
&= ~HWP_MIN_PERF(~0L);
267 value
|= HWP_MIN_PERF(min
);
269 max
= PCT_TO_HWP(limits
.max_perf_pct
);
270 if (limits
.no_turbo
) {
271 rdmsrl( MSR_HWP_CAPABILITIES
, freq
);
272 max
= HWP_GUARANTEED_PERF(freq
);
275 value
&= ~HWP_MAX_PERF(~0L);
276 value
|= HWP_MAX_PERF(max
);
277 wrmsrl_on_cpu(cpu
, MSR_HWP_REQUEST
, value
);
283 /************************** debugfs begin ************************/
284 static int pid_param_set(void *data
, u64 val
)
287 intel_pstate_reset_all_pid();
291 static int pid_param_get(void *data
, u64
*val
)
296 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param
, pid_param_get
, pid_param_set
, "%llu\n");
303 static struct pid_param pid_files
[] = {
304 {"sample_rate_ms", &pid_params
.sample_rate_ms
},
305 {"d_gain_pct", &pid_params
.d_gain_pct
},
306 {"i_gain_pct", &pid_params
.i_gain_pct
},
307 {"deadband", &pid_params
.deadband
},
308 {"setpoint", &pid_params
.setpoint
},
309 {"p_gain_pct", &pid_params
.p_gain_pct
},
313 static void __init
intel_pstate_debug_expose_params(void)
315 struct dentry
*debugfs_parent
;
320 debugfs_parent
= debugfs_create_dir("pstate_snb", NULL
);
321 if (IS_ERR_OR_NULL(debugfs_parent
))
323 while (pid_files
[i
].name
) {
324 debugfs_create_file(pid_files
[i
].name
, 0660,
325 debugfs_parent
, pid_files
[i
].value
,
331 /************************** debugfs end ************************/
333 /************************** sysfs begin ************************/
334 #define show_one(file_name, object) \
335 static ssize_t show_##file_name \
336 (struct kobject *kobj, struct attribute *attr, char *buf) \
338 return sprintf(buf, "%u\n", limits.object); \
341 static ssize_t
show_no_turbo(struct kobject
*kobj
,
342 struct attribute
*attr
, char *buf
)
346 update_turbo_state();
347 if (limits
.turbo_disabled
)
348 ret
= sprintf(buf
, "%u\n", limits
.turbo_disabled
);
350 ret
= sprintf(buf
, "%u\n", limits
.no_turbo
);
355 static ssize_t
store_no_turbo(struct kobject
*a
, struct attribute
*b
,
356 const char *buf
, size_t count
)
361 ret
= sscanf(buf
, "%u", &input
);
365 update_turbo_state();
366 if (limits
.turbo_disabled
) {
367 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
371 limits
.no_turbo
= clamp_t(int, input
, 0, 1);
374 intel_pstate_hwp_set();
379 static ssize_t
store_max_perf_pct(struct kobject
*a
, struct attribute
*b
,
380 const char *buf
, size_t count
)
385 ret
= sscanf(buf
, "%u", &input
);
389 limits
.max_sysfs_pct
= clamp_t(int, input
, 0 , 100);
390 limits
.max_perf_pct
= min(limits
.max_policy_pct
, limits
.max_sysfs_pct
);
391 limits
.max_perf
= div_fp(int_tofp(limits
.max_perf_pct
), int_tofp(100));
394 intel_pstate_hwp_set();
398 static ssize_t
store_min_perf_pct(struct kobject
*a
, struct attribute
*b
,
399 const char *buf
, size_t count
)
404 ret
= sscanf(buf
, "%u", &input
);
407 limits
.min_perf_pct
= clamp_t(int, input
, 0 , 100);
408 limits
.min_perf
= div_fp(int_tofp(limits
.min_perf_pct
), int_tofp(100));
411 intel_pstate_hwp_set();
415 show_one(max_perf_pct
, max_perf_pct
);
416 show_one(min_perf_pct
, min_perf_pct
);
418 define_one_global_rw(no_turbo
);
419 define_one_global_rw(max_perf_pct
);
420 define_one_global_rw(min_perf_pct
);
422 static struct attribute
*intel_pstate_attributes
[] = {
429 static struct attribute_group intel_pstate_attr_group
= {
430 .attrs
= intel_pstate_attributes
,
433 static void __init
intel_pstate_sysfs_expose_params(void)
435 struct kobject
*intel_pstate_kobject
;
438 intel_pstate_kobject
= kobject_create_and_add("intel_pstate",
439 &cpu_subsys
.dev_root
->kobj
);
440 BUG_ON(!intel_pstate_kobject
);
441 rc
= sysfs_create_group(intel_pstate_kobject
, &intel_pstate_attr_group
);
444 /************************** sysfs end ************************/
446 static void intel_pstate_hwp_enable(void)
449 pr_info("intel_pstate HWP enabled\n");
451 wrmsrl( MSR_PM_ENABLE
, 0x1);
454 static int byt_get_min_pstate(void)
458 rdmsrl(BYT_RATIOS
, value
);
459 return (value
>> 8) & 0x7F;
462 static int byt_get_max_pstate(void)
466 rdmsrl(BYT_RATIOS
, value
);
467 return (value
>> 16) & 0x7F;
470 static int byt_get_turbo_pstate(void)
474 rdmsrl(BYT_TURBO_RATIOS
, value
);
478 static void byt_set_pstate(struct cpudata
*cpudata
, int pstate
)
485 if (limits
.no_turbo
&& !limits
.turbo_disabled
)
488 vid_fp
= cpudata
->vid
.min
+ mul_fp(
489 int_tofp(pstate
- cpudata
->pstate
.min_pstate
),
492 vid_fp
= clamp_t(int32_t, vid_fp
, cpudata
->vid
.min
, cpudata
->vid
.max
);
493 vid
= ceiling_fp(vid_fp
);
495 if (pstate
> cpudata
->pstate
.max_pstate
)
496 vid
= cpudata
->vid
.turbo
;
500 wrmsrl(MSR_IA32_PERF_CTL
, val
);
503 #define BYT_BCLK_FREQS 5
504 static int byt_freq_table
[BYT_BCLK_FREQS
] = { 833, 1000, 1333, 1167, 800};
506 static int byt_get_scaling(void)
511 rdmsrl(MSR_FSB_FREQ
, value
);
514 BUG_ON(i
> BYT_BCLK_FREQS
);
516 return byt_freq_table
[i
] * 100;
519 static void byt_get_vid(struct cpudata
*cpudata
)
523 rdmsrl(BYT_VIDS
, value
);
524 cpudata
->vid
.min
= int_tofp((value
>> 8) & 0x7f);
525 cpudata
->vid
.max
= int_tofp((value
>> 16) & 0x7f);
526 cpudata
->vid
.ratio
= div_fp(
527 cpudata
->vid
.max
- cpudata
->vid
.min
,
528 int_tofp(cpudata
->pstate
.max_pstate
-
529 cpudata
->pstate
.min_pstate
));
531 rdmsrl(BYT_TURBO_VIDS
, value
);
532 cpudata
->vid
.turbo
= value
& 0x7f;
535 static int core_get_min_pstate(void)
539 rdmsrl(MSR_PLATFORM_INFO
, value
);
540 return (value
>> 40) & 0xFF;
543 static int core_get_max_pstate(void)
547 rdmsrl(MSR_PLATFORM_INFO
, value
);
548 return (value
>> 8) & 0xFF;
551 static int core_get_turbo_pstate(void)
556 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT
, value
);
557 nont
= core_get_max_pstate();
564 static inline int core_get_scaling(void)
569 static void core_set_pstate(struct cpudata
*cpudata
, int pstate
)
574 if (limits
.no_turbo
&& !limits
.turbo_disabled
)
577 wrmsrl_on_cpu(cpudata
->cpu
, MSR_IA32_PERF_CTL
, val
);
580 static struct cpu_defaults core_params
= {
582 .sample_rate_ms
= 10,
590 .get_max
= core_get_max_pstate
,
591 .get_min
= core_get_min_pstate
,
592 .get_turbo
= core_get_turbo_pstate
,
593 .get_scaling
= core_get_scaling
,
594 .set
= core_set_pstate
,
598 static struct cpu_defaults byt_params
= {
600 .sample_rate_ms
= 10,
608 .get_max
= byt_get_max_pstate
,
609 .get_min
= byt_get_min_pstate
,
610 .get_turbo
= byt_get_turbo_pstate
,
611 .set
= byt_set_pstate
,
612 .get_scaling
= byt_get_scaling
,
613 .get_vid
= byt_get_vid
,
617 static void intel_pstate_get_min_max(struct cpudata
*cpu
, int *min
, int *max
)
619 int max_perf
= cpu
->pstate
.turbo_pstate
;
623 if (limits
.no_turbo
|| limits
.turbo_disabled
)
624 max_perf
= cpu
->pstate
.max_pstate
;
627 * performance can be limited by user through sysfs, by cpufreq
628 * policy, or by cpu specific default values determined through
631 max_perf_adj
= fp_toint(mul_fp(int_tofp(max_perf
), limits
.max_perf
));
632 *max
= clamp_t(int, max_perf_adj
,
633 cpu
->pstate
.min_pstate
, cpu
->pstate
.turbo_pstate
);
635 min_perf
= fp_toint(mul_fp(int_tofp(max_perf
), limits
.min_perf
));
636 *min
= clamp_t(int, min_perf
, cpu
->pstate
.min_pstate
, max_perf
);
639 static void intel_pstate_set_pstate(struct cpudata
*cpu
, int pstate
)
641 int max_perf
, min_perf
;
643 update_turbo_state();
645 intel_pstate_get_min_max(cpu
, &min_perf
, &max_perf
);
647 pstate
= clamp_t(int, pstate
, min_perf
, max_perf
);
649 if (pstate
== cpu
->pstate
.current_pstate
)
652 trace_cpu_frequency(pstate
* cpu
->pstate
.scaling
, cpu
->cpu
);
654 cpu
->pstate
.current_pstate
= pstate
;
656 pstate_funcs
.set(cpu
, pstate
);
659 static void intel_pstate_get_cpu_pstates(struct cpudata
*cpu
)
661 cpu
->pstate
.min_pstate
= pstate_funcs
.get_min();
662 cpu
->pstate
.max_pstate
= pstate_funcs
.get_max();
663 cpu
->pstate
.turbo_pstate
= pstate_funcs
.get_turbo();
664 cpu
->pstate
.scaling
= pstate_funcs
.get_scaling();
666 if (pstate_funcs
.get_vid
)
667 pstate_funcs
.get_vid(cpu
);
668 intel_pstate_set_pstate(cpu
, cpu
->pstate
.min_pstate
);
671 static inline void intel_pstate_calc_busy(struct cpudata
*cpu
)
673 struct sample
*sample
= &cpu
->sample
;
676 core_pct
= int_tofp(sample
->aperf
) * int_tofp(100);
677 core_pct
= div64_u64(core_pct
, int_tofp(sample
->mperf
));
679 sample
->freq
= fp_toint(
681 cpu
->pstate
.max_pstate
* cpu
->pstate
.scaling
/ 100),
684 sample
->core_pct_busy
= (int32_t)core_pct
;
687 static inline void intel_pstate_sample(struct cpudata
*cpu
)
692 local_irq_save(flags
);
693 rdmsrl(MSR_IA32_APERF
, aperf
);
694 rdmsrl(MSR_IA32_MPERF
, mperf
);
695 local_irq_restore(flags
);
697 cpu
->last_sample_time
= cpu
->sample
.time
;
698 cpu
->sample
.time
= ktime_get();
699 cpu
->sample
.aperf
= aperf
;
700 cpu
->sample
.mperf
= mperf
;
701 cpu
->sample
.aperf
-= cpu
->prev_aperf
;
702 cpu
->sample
.mperf
-= cpu
->prev_mperf
;
704 intel_pstate_calc_busy(cpu
);
706 cpu
->prev_aperf
= aperf
;
707 cpu
->prev_mperf
= mperf
;
710 static inline void intel_hwp_set_sample_time(struct cpudata
*cpu
)
714 delay
= msecs_to_jiffies(50);
715 mod_timer_pinned(&cpu
->timer
, jiffies
+ delay
);
718 static inline void intel_pstate_set_sample_time(struct cpudata
*cpu
)
722 delay
= msecs_to_jiffies(pid_params
.sample_rate_ms
);
723 mod_timer_pinned(&cpu
->timer
, jiffies
+ delay
);
726 static inline int32_t intel_pstate_get_scaled_busy(struct cpudata
*cpu
)
728 int32_t core_busy
, max_pstate
, current_pstate
, sample_ratio
;
733 * core_busy is the ratio of actual performance to max
734 * max_pstate is the max non turbo pstate available
735 * current_pstate was the pstate that was requested during
736 * the last sample period.
738 * We normalize core_busy, which was our actual percent
739 * performance to what we requested during the last sample
740 * period. The result will be a percentage of busy at a
743 core_busy
= cpu
->sample
.core_pct_busy
;
744 max_pstate
= int_tofp(cpu
->pstate
.max_pstate
);
745 current_pstate
= int_tofp(cpu
->pstate
.current_pstate
);
746 core_busy
= mul_fp(core_busy
, div_fp(max_pstate
, current_pstate
));
749 * Since we have a deferred timer, it will not fire unless
750 * we are in C0. So, determine if the actual elapsed time
751 * is significantly greater (3x) than our sample interval. If it
752 * is, then we were idle for a long enough period of time
753 * to adjust our busyness.
755 sample_time
= pid_params
.sample_rate_ms
* USEC_PER_MSEC
;
756 duration_us
= (u32
) ktime_us_delta(cpu
->sample
.time
,
757 cpu
->last_sample_time
);
758 if (duration_us
> sample_time
* 3) {
759 sample_ratio
= div_fp(int_tofp(sample_time
),
760 int_tofp(duration_us
));
761 core_busy
= mul_fp(core_busy
, sample_ratio
);
767 static inline void intel_pstate_adjust_busy_pstate(struct cpudata
*cpu
)
774 busy_scaled
= intel_pstate_get_scaled_busy(cpu
);
776 ctl
= pid_calc(pid
, busy_scaled
);
778 /* Negative values of ctl increase the pstate and vice versa */
779 intel_pstate_set_pstate(cpu
, cpu
->pstate
.current_pstate
- ctl
);
782 static void intel_hwp_timer_func(unsigned long __data
)
784 struct cpudata
*cpu
= (struct cpudata
*) __data
;
786 intel_pstate_sample(cpu
);
787 intel_hwp_set_sample_time(cpu
);
790 static void intel_pstate_timer_func(unsigned long __data
)
792 struct cpudata
*cpu
= (struct cpudata
*) __data
;
793 struct sample
*sample
;
795 intel_pstate_sample(cpu
);
797 sample
= &cpu
->sample
;
799 intel_pstate_adjust_busy_pstate(cpu
);
801 trace_pstate_sample(fp_toint(sample
->core_pct_busy
),
802 fp_toint(intel_pstate_get_scaled_busy(cpu
)),
803 cpu
->pstate
.current_pstate
,
808 intel_pstate_set_sample_time(cpu
);
811 #define ICPU(model, policy) \
812 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
813 (unsigned long)&policy }
815 static const struct x86_cpu_id intel_pstate_cpu_ids
[] = {
816 ICPU(0x2a, core_params
),
817 ICPU(0x2d, core_params
),
818 ICPU(0x37, byt_params
),
819 ICPU(0x3a, core_params
),
820 ICPU(0x3c, core_params
),
821 ICPU(0x3d, core_params
),
822 ICPU(0x3e, core_params
),
823 ICPU(0x3f, core_params
),
824 ICPU(0x45, core_params
),
825 ICPU(0x46, core_params
),
826 ICPU(0x47, core_params
),
827 ICPU(0x4c, byt_params
),
828 ICPU(0x4f, core_params
),
829 ICPU(0x56, core_params
),
832 MODULE_DEVICE_TABLE(x86cpu
, intel_pstate_cpu_ids
);
834 static const struct x86_cpu_id intel_pstate_cpu_oob_ids
[] = {
835 ICPU(0x56, core_params
),
839 static int intel_pstate_init_cpu(unsigned int cpunum
)
843 if (!all_cpu_data
[cpunum
])
844 all_cpu_data
[cpunum
] = kzalloc(sizeof(struct cpudata
),
846 if (!all_cpu_data
[cpunum
])
849 cpu
= all_cpu_data
[cpunum
];
852 intel_pstate_get_cpu_pstates(cpu
);
854 init_timer_deferrable(&cpu
->timer
);
855 cpu
->timer
.data
= (unsigned long)cpu
;
856 cpu
->timer
.expires
= jiffies
+ HZ
/100;
859 cpu
->timer
.function
= intel_pstate_timer_func
;
861 cpu
->timer
.function
= intel_hwp_timer_func
;
863 intel_pstate_busy_pid_reset(cpu
);
864 intel_pstate_sample(cpu
);
866 add_timer_on(&cpu
->timer
, cpunum
);
868 pr_debug("Intel pstate controlling: cpu %d\n", cpunum
);
873 static unsigned int intel_pstate_get(unsigned int cpu_num
)
875 struct sample
*sample
;
878 cpu
= all_cpu_data
[cpu_num
];
881 sample
= &cpu
->sample
;
885 static int intel_pstate_set_policy(struct cpufreq_policy
*policy
)
887 if (!policy
->cpuinfo
.max_freq
)
890 if (policy
->policy
== CPUFREQ_POLICY_PERFORMANCE
) {
891 limits
.min_perf_pct
= 100;
892 limits
.min_perf
= int_tofp(1);
893 limits
.max_policy_pct
= 100;
894 limits
.max_perf_pct
= 100;
895 limits
.max_perf
= int_tofp(1);
900 limits
.min_perf_pct
= (policy
->min
* 100) / policy
->cpuinfo
.max_freq
;
901 limits
.min_perf_pct
= clamp_t(int, limits
.min_perf_pct
, 0 , 100);
902 limits
.min_perf
= div_fp(int_tofp(limits
.min_perf_pct
), int_tofp(100));
904 limits
.max_policy_pct
= (policy
->max
* 100) / policy
->cpuinfo
.max_freq
;
905 limits
.max_policy_pct
= clamp_t(int, limits
.max_policy_pct
, 0 , 100);
906 limits
.max_perf_pct
= min(limits
.max_policy_pct
, limits
.max_sysfs_pct
);
907 limits
.max_perf
= div_fp(int_tofp(limits
.max_perf_pct
), int_tofp(100));
910 intel_pstate_hwp_set();
915 static int intel_pstate_verify_policy(struct cpufreq_policy
*policy
)
917 cpufreq_verify_within_cpu_limits(policy
);
919 if (policy
->policy
!= CPUFREQ_POLICY_POWERSAVE
&&
920 policy
->policy
!= CPUFREQ_POLICY_PERFORMANCE
)
926 static void intel_pstate_stop_cpu(struct cpufreq_policy
*policy
)
928 int cpu_num
= policy
->cpu
;
929 struct cpudata
*cpu
= all_cpu_data
[cpu_num
];
931 pr_info("intel_pstate CPU %d exiting\n", cpu_num
);
933 del_timer_sync(&all_cpu_data
[cpu_num
]->timer
);
937 intel_pstate_set_pstate(cpu
, cpu
->pstate
.min_pstate
);
940 static int intel_pstate_cpu_init(struct cpufreq_policy
*policy
)
945 rc
= intel_pstate_init_cpu(policy
->cpu
);
949 cpu
= all_cpu_data
[policy
->cpu
];
951 if (limits
.min_perf_pct
== 100 && limits
.max_perf_pct
== 100)
952 policy
->policy
= CPUFREQ_POLICY_PERFORMANCE
;
954 policy
->policy
= CPUFREQ_POLICY_POWERSAVE
;
956 policy
->min
= cpu
->pstate
.min_pstate
* cpu
->pstate
.scaling
;
957 policy
->max
= cpu
->pstate
.turbo_pstate
* cpu
->pstate
.scaling
;
959 /* cpuinfo and default policy values */
960 policy
->cpuinfo
.min_freq
= cpu
->pstate
.min_pstate
* cpu
->pstate
.scaling
;
961 policy
->cpuinfo
.max_freq
=
962 cpu
->pstate
.turbo_pstate
* cpu
->pstate
.scaling
;
963 policy
->cpuinfo
.transition_latency
= CPUFREQ_ETERNAL
;
964 cpumask_set_cpu(policy
->cpu
, policy
->cpus
);
969 static struct cpufreq_driver intel_pstate_driver
= {
970 .flags
= CPUFREQ_CONST_LOOPS
,
971 .verify
= intel_pstate_verify_policy
,
972 .setpolicy
= intel_pstate_set_policy
,
973 .get
= intel_pstate_get
,
974 .init
= intel_pstate_cpu_init
,
975 .stop_cpu
= intel_pstate_stop_cpu
,
976 .name
= "intel_pstate",
979 static int __initdata no_load
;
980 static int __initdata no_hwp
;
981 static unsigned int force_load
;
983 static int intel_pstate_msrs_not_valid(void)
985 /* Check that all the msr's we are using are valid. */
986 u64 aperf
, mperf
, tmp
;
988 rdmsrl(MSR_IA32_APERF
, aperf
);
989 rdmsrl(MSR_IA32_MPERF
, mperf
);
991 if (!pstate_funcs
.get_max() ||
992 !pstate_funcs
.get_min() ||
993 !pstate_funcs
.get_turbo())
996 rdmsrl(MSR_IA32_APERF
, tmp
);
1000 rdmsrl(MSR_IA32_MPERF
, tmp
);
1007 static void copy_pid_params(struct pstate_adjust_policy
*policy
)
1009 pid_params
.sample_rate_ms
= policy
->sample_rate_ms
;
1010 pid_params
.p_gain_pct
= policy
->p_gain_pct
;
1011 pid_params
.i_gain_pct
= policy
->i_gain_pct
;
1012 pid_params
.d_gain_pct
= policy
->d_gain_pct
;
1013 pid_params
.deadband
= policy
->deadband
;
1014 pid_params
.setpoint
= policy
->setpoint
;
1017 static void copy_cpu_funcs(struct pstate_funcs
*funcs
)
1019 pstate_funcs
.get_max
= funcs
->get_max
;
1020 pstate_funcs
.get_min
= funcs
->get_min
;
1021 pstate_funcs
.get_turbo
= funcs
->get_turbo
;
1022 pstate_funcs
.get_scaling
= funcs
->get_scaling
;
1023 pstate_funcs
.set
= funcs
->set
;
1024 pstate_funcs
.get_vid
= funcs
->get_vid
;
1027 #if IS_ENABLED(CONFIG_ACPI)
1028 #include <acpi/processor.h>
1030 static bool intel_pstate_no_acpi_pss(void)
1034 for_each_possible_cpu(i
) {
1036 union acpi_object
*pss
;
1037 struct acpi_buffer buffer
= { ACPI_ALLOCATE_BUFFER
, NULL
};
1038 struct acpi_processor
*pr
= per_cpu(processors
, i
);
1043 status
= acpi_evaluate_object(pr
->handle
, "_PSS", NULL
, &buffer
);
1044 if (ACPI_FAILURE(status
))
1047 pss
= buffer
.pointer
;
1048 if (pss
&& pss
->type
== ACPI_TYPE_PACKAGE
) {
1059 static bool intel_pstate_has_acpi_ppc(void)
1063 for_each_possible_cpu(i
) {
1064 struct acpi_processor
*pr
= per_cpu(processors
, i
);
1068 if (acpi_has_method(pr
->handle
, "_PPC"))
1079 struct hw_vendor_info
{
1081 char oem_id
[ACPI_OEM_ID_SIZE
];
1082 char oem_table_id
[ACPI_OEM_TABLE_ID_SIZE
];
1086 /* Hardware vendor-specific info that has its own power management modes */
1087 static struct hw_vendor_info vendor_info
[] = {
1088 {1, "HP ", "ProLiant", PSS
},
1089 {1, "ORACLE", "X4-2 ", PPC
},
1090 {1, "ORACLE", "X4-2L ", PPC
},
1091 {1, "ORACLE", "X4-2B ", PPC
},
1092 {1, "ORACLE", "X3-2 ", PPC
},
1093 {1, "ORACLE", "X3-2L ", PPC
},
1094 {1, "ORACLE", "X3-2B ", PPC
},
1095 {1, "ORACLE", "X4470M2 ", PPC
},
1096 {1, "ORACLE", "X4270M3 ", PPC
},
1097 {1, "ORACLE", "X4270M2 ", PPC
},
1098 {1, "ORACLE", "X4170M2 ", PPC
},
1102 static bool intel_pstate_platform_pwr_mgmt_exists(void)
1104 struct acpi_table_header hdr
;
1105 struct hw_vendor_info
*v_info
;
1106 const struct x86_cpu_id
*id
;
1109 id
= x86_match_cpu(intel_pstate_cpu_oob_ids
);
1111 rdmsrl(MSR_MISC_PWR_MGMT
, misc_pwr
);
1112 if ( misc_pwr
& (1 << 8))
1116 if (acpi_disabled
||
1117 ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT
, 0, &hdr
)))
1120 for (v_info
= vendor_info
; v_info
->valid
; v_info
++) {
1121 if (!strncmp(hdr
.oem_id
, v_info
->oem_id
, ACPI_OEM_ID_SIZE
) &&
1122 !strncmp(hdr
.oem_table_id
, v_info
->oem_table_id
,
1123 ACPI_OEM_TABLE_ID_SIZE
))
1124 switch (v_info
->oem_pwr_table
) {
1126 return intel_pstate_no_acpi_pss();
1128 return intel_pstate_has_acpi_ppc() &&
1135 #else /* CONFIG_ACPI not enabled */
1136 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
1137 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
1138 #endif /* CONFIG_ACPI */
1140 static int __init
intel_pstate_init(void)
1143 const struct x86_cpu_id
*id
;
1144 struct cpu_defaults
*cpu_info
;
1145 struct cpuinfo_x86
*c
= &boot_cpu_data
;
1150 id
= x86_match_cpu(intel_pstate_cpu_ids
);
1155 * The Intel pstate driver will be ignored if the platform
1156 * firmware has its own power management modes.
1158 if (intel_pstate_platform_pwr_mgmt_exists())
1161 cpu_info
= (struct cpu_defaults
*)id
->driver_data
;
1163 copy_pid_params(&cpu_info
->pid_policy
);
1164 copy_cpu_funcs(&cpu_info
->funcs
);
1166 if (intel_pstate_msrs_not_valid())
1169 pr_info("Intel P-state driver initializing.\n");
1171 all_cpu_data
= vzalloc(sizeof(void *) * num_possible_cpus());
1175 if (cpu_has(c
,X86_FEATURE_HWP
) && !no_hwp
)
1176 intel_pstate_hwp_enable();
1178 rc
= cpufreq_register_driver(&intel_pstate_driver
);
1182 intel_pstate_debug_expose_params();
1183 intel_pstate_sysfs_expose_params();
1188 for_each_online_cpu(cpu
) {
1189 if (all_cpu_data
[cpu
]) {
1190 del_timer_sync(&all_cpu_data
[cpu
]->timer
);
1191 kfree(all_cpu_data
[cpu
]);
1196 vfree(all_cpu_data
);
1199 device_initcall(intel_pstate_init
);
1201 static int __init
intel_pstate_setup(char *str
)
1206 if (!strcmp(str
, "disable"))
1208 if (!strcmp(str
, "no_hwp"))
1210 if (!strcmp(str
, "force"))
1214 early_param("intel_pstate", intel_pstate_setup
);
1216 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
1217 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
1218 MODULE_LICENSE("GPL");