3 bool "Hardware crypto devices"
6 Say Y here to get to see options for hardware crypto devices and
7 processors. This option alone does not add any kernel code.
9 If you say N, all options in this submenu will be skipped and disabled.
13 config CRYPTO_DEV_PADLOCK
14 tristate "Support for VIA PadLock ACE"
15 depends on X86 && !UML
17 Some VIA processors come with an integrated crypto engine
18 (so called VIA PadLock ACE, Advanced Cryptography Engine)
19 that provides instructions for very fast cryptographic
20 operations with supported algorithms.
22 The instructions are used only when the CPU supports them.
23 Otherwise software encryption is used.
25 config CRYPTO_DEV_PADLOCK_AES
26 tristate "PadLock driver for AES algorithm"
27 depends on CRYPTO_DEV_PADLOCK
28 select CRYPTO_BLKCIPHER
31 Use VIA PadLock for AES algorithm.
33 Available in VIA C3 and newer CPUs.
35 If unsure say M. The compiled module will be
38 config CRYPTO_DEV_PADLOCK_SHA
39 tristate "PadLock driver for SHA1 and SHA256 algorithms"
40 depends on CRYPTO_DEV_PADLOCK
45 Use VIA PadLock for SHA1/SHA256 algorithms.
47 Available in VIA C7 and newer processors.
49 If unsure say M. The compiled module will be
52 config CRYPTO_DEV_GEODE
53 tristate "Support for the Geode LX AES engine"
54 depends on X86_32 && PCI
56 select CRYPTO_BLKCIPHER
58 Say 'Y' here to use the AMD Geode LX processor on-board AES
59 engine for the CryptoAPI AES algorithm.
61 To compile this driver as a module, choose M here: the module
62 will be called geode-aes.
65 tristate "Support for PCI-attached cryptographic adapters"
67 select ZCRYPT_MONOLITHIC if ZCRYPT="y"
70 Select this option if you want to use a PCI-attached cryptographic
72 + PCI Cryptographic Accelerator (PCICA)
73 + PCI Cryptographic Coprocessor (PCICC)
74 + PCI-X Cryptographic Coprocessor (PCIXCC)
75 + Crypto Express2 Coprocessor (CEX2C)
76 + Crypto Express2 Accelerator (CEX2A)
78 config ZCRYPT_MONOLITHIC
79 bool "Monolithic zcrypt module"
82 Select this option if you want to have a single module z90crypt,
83 that contains all parts of the crypto device driver (ap bus,
84 request router and all the card drivers).
86 config CRYPTO_SHA1_S390
87 tristate "SHA1 digest algorithm"
91 This is the s390 hardware accelerated implementation of the
92 SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2).
94 It is available as of z990.
96 config CRYPTO_SHA256_S390
97 tristate "SHA256 digest algorithm"
101 This is the s390 hardware accelerated implementation of the
102 SHA256 secure hash standard (DFIPS 180-2).
104 It is available as of z9.
106 config CRYPTO_SHA512_S390
107 tristate "SHA384 and SHA512 digest algorithm"
111 This is the s390 hardware accelerated implementation of the
112 SHA512 secure hash standard.
114 It is available as of z10.
116 config CRYPTO_DES_S390
117 tristate "DES and Triple DES cipher algorithms"
120 select CRYPTO_BLKCIPHER
122 This is the s390 hardware accelerated implementation of the
123 DES cipher algorithm (FIPS 46-2), and Triple DES EDE (FIPS 46-3).
125 As of z990 the ECB and CBC mode are hardware accelerated.
126 As of z196 the CTR mode is hardware accelerated.
128 config CRYPTO_AES_S390
129 tristate "AES cipher algorithms"
132 select CRYPTO_BLKCIPHER
134 This is the s390 hardware accelerated implementation of the
135 AES cipher algorithms (FIPS-197).
137 As of z9 the ECB and CBC modes are hardware accelerated
139 As of z10 the ECB and CBC modes are hardware accelerated
140 for all AES key sizes.
141 As of z196 the CTR mode is hardware accelerated for all AES
142 key sizes and XTS mode is hardware accelerated for 256 and
146 tristate "Pseudo random number generator device driver"
150 Select this option if you want to use the s390 pseudo random number
151 generator. The PRNG is part of the cryptographic processor functions
152 and uses triple-DES to generate secure random numbers like the
153 ANSI X9.17 standard. User-space programs access the
154 pseudo-random-number device through the char device /dev/prandom.
156 It is available as of z9.
158 config CRYPTO_GHASH_S390
159 tristate "GHASH digest algorithm"
163 This is the s390 hardware accelerated implementation of the
164 GHASH message digest algorithm for GCM (Galois/Counter Mode).
166 It is available as of z196.
168 config CRYPTO_DEV_MV_CESA
169 tristate "Marvell's Cryptographic Engine"
170 depends on PLAT_ORION
173 select CRYPTO_BLKCIPHER2
175 This driver allows you to utilize the Cryptographic Engines and
176 Security Accelerator (CESA) which can be found on the Marvell Orion
177 and Kirkwood SoCs, such as QNAP's TS-209.
179 Currently the driver supports AES in ECB and CBC mode without DMA.
181 config CRYPTO_DEV_NIAGARA2
182 tristate "Niagara2 Stream Processing Unit driver"
187 Each core of a Niagara2 processor contains a Stream
188 Processing Unit, which itself contains several cryptographic
189 sub-units. One set provides the Modular Arithmetic Unit,
190 used for SSL offload. The other set provides the Cipher
191 Group, which can perform encryption, decryption, hashing,
192 checksumming, and raw copies.
194 config CRYPTO_DEV_HIFN_795X
195 tristate "Driver HIFN 795x crypto accelerator chips"
198 select CRYPTO_BLKCIPHER
199 select HW_RANDOM if CRYPTO_DEV_HIFN_795X_RNG
202 This option allows you to have support for HIFN 795x crypto adapters.
204 config CRYPTO_DEV_HIFN_795X_RNG
205 bool "HIFN 795x random number generator"
206 depends on CRYPTO_DEV_HIFN_795X
208 Select this option if you want to enable the random number generator
209 on the HIFN 795x crypto adapters.
211 source drivers/crypto/caam/Kconfig
213 config CRYPTO_DEV_TALITOS
214 tristate "Talitos Freescale Security Engine (SEC)"
216 select CRYPTO_AUTHENC
220 Say 'Y' here to use the Freescale Security Engine (SEC)
221 to offload cryptographic algorithm computation.
223 The Freescale SEC is present on PowerQUICC 'E' processors, such
224 as the MPC8349E and MPC8548E.
226 To compile this driver as a module, choose M here: the module
227 will be called talitos.
229 config CRYPTO_DEV_IXP4XX
230 tristate "Driver for IXP4xx crypto hardware acceleration"
231 depends on ARCH_IXP4XX
234 select CRYPTO_AUTHENC
235 select CRYPTO_BLKCIPHER
237 Driver for the IXP4xx NPE crypto engine.
239 config CRYPTO_DEV_PPC4XX
240 tristate "Driver AMCC PPC4xx crypto accelerator"
241 depends on PPC && 4xx
244 select CRYPTO_BLKCIPHER
246 This option allows you to have support for AMCC crypto acceleration.
248 config CRYPTO_DEV_OMAP_SHAM
249 tristate "Support for OMAP SHA1/MD5 hw accelerator"
250 depends on ARCH_OMAP2 || ARCH_OMAP3
254 OMAP processors have SHA1/MD5 hw accelerator. Select this if you
255 want to use the OMAP module for SHA1/MD5 algorithms.
257 config CRYPTO_DEV_OMAP_AES
258 tristate "Support for OMAP AES hw engine"
259 depends on ARCH_OMAP2 || ARCH_OMAP3
262 OMAP processors have AES module accelerator. Select this if you
263 want to use the OMAP module for AES algorithms.
265 config CRYPTO_DEV_PICOXCELL
266 tristate "Support for picoXcell IPSEC and Layer2 crypto engines"
267 depends on ARCH_PICOXCELL
269 select CRYPTO_AUTHENC
276 This option enables support for the hardware offload engines in the
277 Picochip picoXcell SoC devices. Select this for IPSEC ESP offload
278 and for 3gpp Layer 2 ciphering support.
280 Saying m here will build a module named pipcoxcell_crypto.
282 config CRYPTO_DEV_S5P
283 tristate "Support for Samsung S5PV210 crypto accelerator"
284 depends on ARCH_S5PV210
287 select CRYPTO_BLKCIPHER
289 This option allows you to have support for S5P crypto acceleration.
290 Select this to offload Samsung S5PV210 or S5PC110 from AES
291 algorithms execution.