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crypto: atmel-aes - improve performances of data transfer
[deliverable/linux.git] / drivers / crypto / atmel-aes.c
1 /*
2 * Cryptographic API.
3 *
4 * Support for ATMEL AES HW acceleration.
5 *
6 * Copyright (c) 2012 Eukréa Electromatique - ATMEL
7 * Author: Nicolas Royer <nicolas@eukrea.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 *
13 * Some ideas are from omap-aes.c driver.
14 */
15
16
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/err.h>
21 #include <linux/clk.h>
22 #include <linux/io.h>
23 #include <linux/hw_random.h>
24 #include <linux/platform_device.h>
25
26 #include <linux/device.h>
27 #include <linux/init.h>
28 #include <linux/errno.h>
29 #include <linux/interrupt.h>
30 #include <linux/irq.h>
31 #include <linux/scatterlist.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/of_device.h>
34 #include <linux/delay.h>
35 #include <linux/crypto.h>
36 #include <crypto/scatterwalk.h>
37 #include <crypto/algapi.h>
38 #include <crypto/aes.h>
39 #include <linux/platform_data/crypto-atmel.h>
40 #include <dt-bindings/dma/at91.h>
41 #include "atmel-aes-regs.h"
42
43 #define ATMEL_AES_PRIORITY 300
44
45 #define ATMEL_AES_BUFFER_ORDER 2
46 #define ATMEL_AES_BUFFER_SIZE (PAGE_SIZE << ATMEL_AES_BUFFER_ORDER)
47
48 #define CFB8_BLOCK_SIZE 1
49 #define CFB16_BLOCK_SIZE 2
50 #define CFB32_BLOCK_SIZE 4
51 #define CFB64_BLOCK_SIZE 8
52
53 #define SIZE_IN_WORDS(x) ((x) >> 2)
54
55 /* AES flags */
56 /* Reserve bits [18:16] [14:12] [0] for mode (same as for AES_MR) */
57 #define AES_FLAGS_ENCRYPT AES_MR_CYPHER_ENC
58 #define AES_FLAGS_OPMODE_MASK (AES_MR_OPMOD_MASK | AES_MR_CFBS_MASK)
59 #define AES_FLAGS_ECB AES_MR_OPMOD_ECB
60 #define AES_FLAGS_CBC AES_MR_OPMOD_CBC
61 #define AES_FLAGS_OFB AES_MR_OPMOD_OFB
62 #define AES_FLAGS_CFB128 (AES_MR_OPMOD_CFB | AES_MR_CFBS_128b)
63 #define AES_FLAGS_CFB64 (AES_MR_OPMOD_CFB | AES_MR_CFBS_64b)
64 #define AES_FLAGS_CFB32 (AES_MR_OPMOD_CFB | AES_MR_CFBS_32b)
65 #define AES_FLAGS_CFB16 (AES_MR_OPMOD_CFB | AES_MR_CFBS_16b)
66 #define AES_FLAGS_CFB8 (AES_MR_OPMOD_CFB | AES_MR_CFBS_8b)
67 #define AES_FLAGS_CTR AES_MR_OPMOD_CTR
68
69 #define AES_FLAGS_MODE_MASK (AES_FLAGS_OPMODE_MASK | \
70 AES_FLAGS_ENCRYPT)
71
72 #define AES_FLAGS_INIT BIT(2)
73 #define AES_FLAGS_BUSY BIT(3)
74
75 #define AES_FLAGS_PERSISTENT (AES_FLAGS_INIT | AES_FLAGS_BUSY)
76
77 #define ATMEL_AES_QUEUE_LENGTH 50
78
79 #define ATMEL_AES_DMA_THRESHOLD 16
80
81
82 struct atmel_aes_caps {
83 bool has_dualbuff;
84 bool has_cfb64;
85 u32 max_burst_size;
86 };
87
88 struct atmel_aes_dev;
89
90
91 typedef int (*atmel_aes_fn_t)(struct atmel_aes_dev *);
92
93
94 struct atmel_aes_base_ctx {
95 struct atmel_aes_dev *dd;
96 atmel_aes_fn_t start;
97
98 int keylen;
99 u32 key[AES_KEYSIZE_256 / sizeof(u32)];
100
101 u16 block_size;
102 };
103
104 struct atmel_aes_ctx {
105 struct atmel_aes_base_ctx base;
106 };
107
108 struct atmel_aes_reqctx {
109 unsigned long mode;
110 };
111
112 struct atmel_aes_dma {
113 struct dma_chan *chan;
114 struct scatterlist *sg;
115 int nents;
116 unsigned int remainder;
117 unsigned int sg_len;
118 };
119
120 struct atmel_aes_dev {
121 struct list_head list;
122 unsigned long phys_base;
123 void __iomem *io_base;
124
125 struct crypto_async_request *areq;
126 struct atmel_aes_base_ctx *ctx;
127
128 bool is_async;
129 atmel_aes_fn_t resume;
130 atmel_aes_fn_t cpu_transfer_complete;
131
132 struct device *dev;
133 struct clk *iclk;
134 int irq;
135
136 unsigned long flags;
137
138 spinlock_t lock;
139 struct crypto_queue queue;
140
141 struct tasklet_struct done_task;
142 struct tasklet_struct queue_task;
143
144 size_t total;
145 size_t datalen;
146 u32 *data;
147
148 struct atmel_aes_dma src;
149 struct atmel_aes_dma dst;
150
151 size_t buflen;
152 void *buf;
153 struct scatterlist aligned_sg;
154 struct scatterlist *real_dst;
155
156 struct atmel_aes_caps caps;
157
158 u32 hw_version;
159 };
160
161 struct atmel_aes_drv {
162 struct list_head dev_list;
163 spinlock_t lock;
164 };
165
166 static struct atmel_aes_drv atmel_aes = {
167 .dev_list = LIST_HEAD_INIT(atmel_aes.dev_list),
168 .lock = __SPIN_LOCK_UNLOCKED(atmel_aes.lock),
169 };
170
171
172 static inline u32 atmel_aes_read(struct atmel_aes_dev *dd, u32 offset)
173 {
174 return readl_relaxed(dd->io_base + offset);
175 }
176
177 static inline void atmel_aes_write(struct atmel_aes_dev *dd,
178 u32 offset, u32 value)
179 {
180 writel_relaxed(value, dd->io_base + offset);
181 }
182
183 static void atmel_aes_read_n(struct atmel_aes_dev *dd, u32 offset,
184 u32 *value, int count)
185 {
186 for (; count--; value++, offset += 4)
187 *value = atmel_aes_read(dd, offset);
188 }
189
190 static void atmel_aes_write_n(struct atmel_aes_dev *dd, u32 offset,
191 const u32 *value, int count)
192 {
193 for (; count--; value++, offset += 4)
194 atmel_aes_write(dd, offset, *value);
195 }
196
197 static inline void atmel_aes_read_block(struct atmel_aes_dev *dd, u32 offset,
198 u32 *value)
199 {
200 atmel_aes_read_n(dd, offset, value, SIZE_IN_WORDS(AES_BLOCK_SIZE));
201 }
202
203 static inline void atmel_aes_write_block(struct atmel_aes_dev *dd, u32 offset,
204 const u32 *value)
205 {
206 atmel_aes_write_n(dd, offset, value, SIZE_IN_WORDS(AES_BLOCK_SIZE));
207 }
208
209 static inline int atmel_aes_wait_for_data_ready(struct atmel_aes_dev *dd,
210 atmel_aes_fn_t resume)
211 {
212 u32 isr = atmel_aes_read(dd, AES_ISR);
213
214 if (unlikely(isr & AES_INT_DATARDY))
215 return resume(dd);
216
217 dd->resume = resume;
218 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
219 return -EINPROGRESS;
220 }
221
222 static inline size_t atmel_aes_padlen(size_t len, size_t block_size)
223 {
224 len &= block_size - 1;
225 return len ? block_size - len : 0;
226 }
227
228 static struct atmel_aes_dev *atmel_aes_find_dev(struct atmel_aes_base_ctx *ctx)
229 {
230 struct atmel_aes_dev *aes_dd = NULL;
231 struct atmel_aes_dev *tmp;
232
233 spin_lock_bh(&atmel_aes.lock);
234 if (!ctx->dd) {
235 list_for_each_entry(tmp, &atmel_aes.dev_list, list) {
236 aes_dd = tmp;
237 break;
238 }
239 ctx->dd = aes_dd;
240 } else {
241 aes_dd = ctx->dd;
242 }
243
244 spin_unlock_bh(&atmel_aes.lock);
245
246 return aes_dd;
247 }
248
249 static int atmel_aes_hw_init(struct atmel_aes_dev *dd)
250 {
251 int err;
252
253 err = clk_prepare_enable(dd->iclk);
254 if (err)
255 return err;
256
257 if (!(dd->flags & AES_FLAGS_INIT)) {
258 atmel_aes_write(dd, AES_CR, AES_CR_SWRST);
259 atmel_aes_write(dd, AES_MR, 0xE << AES_MR_CKEY_OFFSET);
260 dd->flags |= AES_FLAGS_INIT;
261 }
262
263 return 0;
264 }
265
266 static inline unsigned int atmel_aes_get_version(struct atmel_aes_dev *dd)
267 {
268 return atmel_aes_read(dd, AES_HW_VERSION) & 0x00000fff;
269 }
270
271 static int atmel_aes_hw_version_init(struct atmel_aes_dev *dd)
272 {
273 int err;
274
275 err = atmel_aes_hw_init(dd);
276 if (err)
277 return err;
278
279 dd->hw_version = atmel_aes_get_version(dd);
280
281 dev_info(dd->dev, "version: 0x%x\n", dd->hw_version);
282
283 clk_disable_unprepare(dd->iclk);
284 return 0;
285 }
286
287 static inline void atmel_aes_set_mode(struct atmel_aes_dev *dd,
288 const struct atmel_aes_reqctx *rctx)
289 {
290 /* Clear all but persistent flags and set request flags. */
291 dd->flags = (dd->flags & AES_FLAGS_PERSISTENT) | rctx->mode;
292 }
293
294 static inline int atmel_aes_complete(struct atmel_aes_dev *dd, int err)
295 {
296 clk_disable_unprepare(dd->iclk);
297 dd->flags &= ~AES_FLAGS_BUSY;
298
299 if (dd->is_async)
300 dd->areq->complete(dd->areq, err);
301
302 tasklet_schedule(&dd->queue_task);
303
304 return err;
305 }
306
307
308 /* CPU transfer */
309
310 static int atmel_aes_cpu_transfer(struct atmel_aes_dev *dd)
311 {
312 int err = 0;
313 u32 isr;
314
315 for (;;) {
316 atmel_aes_read_block(dd, AES_ODATAR(0), dd->data);
317 dd->data += 4;
318 dd->datalen -= AES_BLOCK_SIZE;
319
320 if (dd->datalen < AES_BLOCK_SIZE)
321 break;
322
323 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
324
325 isr = atmel_aes_read(dd, AES_ISR);
326 if (!(isr & AES_INT_DATARDY)) {
327 dd->resume = atmel_aes_cpu_transfer;
328 atmel_aes_write(dd, AES_IER, AES_INT_DATARDY);
329 return -EINPROGRESS;
330 }
331 }
332
333 if (!sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst),
334 dd->buf, dd->total))
335 err = -EINVAL;
336
337 if (err)
338 return atmel_aes_complete(dd, err);
339
340 return dd->cpu_transfer_complete(dd);
341 }
342
343 static int atmel_aes_cpu_start(struct atmel_aes_dev *dd,
344 struct scatterlist *src,
345 struct scatterlist *dst,
346 size_t len,
347 atmel_aes_fn_t resume)
348 {
349 size_t padlen = atmel_aes_padlen(len, AES_BLOCK_SIZE);
350
351 if (unlikely(len == 0))
352 return -EINVAL;
353
354 sg_copy_to_buffer(src, sg_nents(src), dd->buf, len);
355
356 dd->total = len;
357 dd->real_dst = dst;
358 dd->cpu_transfer_complete = resume;
359 dd->datalen = len + padlen;
360 dd->data = (u32 *)dd->buf;
361 atmel_aes_write_block(dd, AES_IDATAR(0), dd->data);
362 return atmel_aes_wait_for_data_ready(dd, atmel_aes_cpu_transfer);
363 }
364
365
366 /* DMA transfer */
367
368 static void atmel_aes_dma_callback(void *data);
369
370 static bool atmel_aes_check_aligned(struct atmel_aes_dev *dd,
371 struct scatterlist *sg,
372 size_t len,
373 struct atmel_aes_dma *dma)
374 {
375 int nents;
376
377 if (!IS_ALIGNED(len, dd->ctx->block_size))
378 return false;
379
380 for (nents = 0; sg; sg = sg_next(sg), ++nents) {
381 if (!IS_ALIGNED(sg->offset, sizeof(u32)))
382 return false;
383
384 if (len <= sg->length) {
385 if (!IS_ALIGNED(len, dd->ctx->block_size))
386 return false;
387
388 dma->nents = nents+1;
389 dma->remainder = sg->length - len;
390 sg->length = len;
391 return true;
392 }
393
394 if (!IS_ALIGNED(sg->length, dd->ctx->block_size))
395 return false;
396
397 len -= sg->length;
398 }
399
400 return false;
401 }
402
403 static inline void atmel_aes_restore_sg(const struct atmel_aes_dma *dma)
404 {
405 struct scatterlist *sg = dma->sg;
406 int nents = dma->nents;
407
408 if (!dma->remainder)
409 return;
410
411 while (--nents > 0 && sg)
412 sg = sg_next(sg);
413
414 if (!sg)
415 return;
416
417 sg->length += dma->remainder;
418 }
419
420 static int atmel_aes_map(struct atmel_aes_dev *dd,
421 struct scatterlist *src,
422 struct scatterlist *dst,
423 size_t len)
424 {
425 bool src_aligned, dst_aligned;
426 size_t padlen;
427
428 dd->total = len;
429 dd->src.sg = src;
430 dd->dst.sg = dst;
431 dd->real_dst = dst;
432
433 src_aligned = atmel_aes_check_aligned(dd, src, len, &dd->src);
434 if (src == dst)
435 dst_aligned = src_aligned;
436 else
437 dst_aligned = atmel_aes_check_aligned(dd, dst, len, &dd->dst);
438 if (!src_aligned || !dst_aligned) {
439 padlen = atmel_aes_padlen(len, dd->ctx->block_size);
440
441 if (dd->buflen < len + padlen)
442 return -ENOMEM;
443
444 if (!src_aligned) {
445 sg_copy_to_buffer(src, sg_nents(src), dd->buf, len);
446 dd->src.sg = &dd->aligned_sg;
447 dd->src.nents = 1;
448 dd->src.remainder = 0;
449 }
450
451 if (!dst_aligned) {
452 dd->dst.sg = &dd->aligned_sg;
453 dd->dst.nents = 1;
454 dd->dst.remainder = 0;
455 }
456
457 sg_init_table(&dd->aligned_sg, 1);
458 sg_set_buf(&dd->aligned_sg, dd->buf, len + padlen);
459 }
460
461 if (dd->src.sg == dd->dst.sg) {
462 dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents,
463 DMA_BIDIRECTIONAL);
464 dd->dst.sg_len = dd->src.sg_len;
465 if (!dd->src.sg_len)
466 return -EFAULT;
467 } else {
468 dd->src.sg_len = dma_map_sg(dd->dev, dd->src.sg, dd->src.nents,
469 DMA_TO_DEVICE);
470 if (!dd->src.sg_len)
471 return -EFAULT;
472
473 dd->dst.sg_len = dma_map_sg(dd->dev, dd->dst.sg, dd->dst.nents,
474 DMA_FROM_DEVICE);
475 if (!dd->dst.sg_len) {
476 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
477 DMA_TO_DEVICE);
478 return -EFAULT;
479 }
480 }
481
482 return 0;
483 }
484
485 static void atmel_aes_unmap(struct atmel_aes_dev *dd)
486 {
487 if (dd->src.sg == dd->dst.sg) {
488 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
489 DMA_BIDIRECTIONAL);
490
491 if (dd->src.sg != &dd->aligned_sg)
492 atmel_aes_restore_sg(&dd->src);
493 } else {
494 dma_unmap_sg(dd->dev, dd->dst.sg, dd->dst.nents,
495 DMA_FROM_DEVICE);
496
497 if (dd->dst.sg != &dd->aligned_sg)
498 atmel_aes_restore_sg(&dd->dst);
499
500 dma_unmap_sg(dd->dev, dd->src.sg, dd->src.nents,
501 DMA_TO_DEVICE);
502
503 if (dd->src.sg != &dd->aligned_sg)
504 atmel_aes_restore_sg(&dd->src);
505 }
506
507 if (dd->dst.sg == &dd->aligned_sg)
508 sg_copy_from_buffer(dd->real_dst, sg_nents(dd->real_dst),
509 dd->buf, dd->total);
510 }
511
512 static int atmel_aes_dma_transfer_start(struct atmel_aes_dev *dd,
513 enum dma_slave_buswidth addr_width,
514 enum dma_transfer_direction dir,
515 u32 maxburst)
516 {
517 struct dma_async_tx_descriptor *desc;
518 struct dma_slave_config config;
519 dma_async_tx_callback callback;
520 struct atmel_aes_dma *dma;
521 int err;
522
523 memset(&config, 0, sizeof(config));
524 config.direction = dir;
525 config.src_addr_width = addr_width;
526 config.dst_addr_width = addr_width;
527 config.src_maxburst = maxburst;
528 config.dst_maxburst = maxburst;
529
530 switch (dir) {
531 case DMA_MEM_TO_DEV:
532 dma = &dd->src;
533 callback = NULL;
534 config.dst_addr = dd->phys_base + AES_IDATAR(0);
535 break;
536
537 case DMA_DEV_TO_MEM:
538 dma = &dd->dst;
539 callback = atmel_aes_dma_callback;
540 config.src_addr = dd->phys_base + AES_ODATAR(0);
541 break;
542
543 default:
544 return -EINVAL;
545 }
546
547 err = dmaengine_slave_config(dma->chan, &config);
548 if (err)
549 return err;
550
551 desc = dmaengine_prep_slave_sg(dma->chan, dma->sg, dma->sg_len, dir,
552 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
553 if (!desc)
554 return -ENOMEM;
555
556 desc->callback = callback;
557 desc->callback_param = dd;
558 dmaengine_submit(desc);
559 dma_async_issue_pending(dma->chan);
560
561 return 0;
562 }
563
564 static void atmel_aes_dma_transfer_stop(struct atmel_aes_dev *dd,
565 enum dma_transfer_direction dir)
566 {
567 struct atmel_aes_dma *dma;
568
569 switch (dir) {
570 case DMA_MEM_TO_DEV:
571 dma = &dd->src;
572 break;
573
574 case DMA_DEV_TO_MEM:
575 dma = &dd->dst;
576 break;
577
578 default:
579 return;
580 }
581
582 dmaengine_terminate_all(dma->chan);
583 }
584
585 static int atmel_aes_dma_start(struct atmel_aes_dev *dd,
586 struct scatterlist *src,
587 struct scatterlist *dst,
588 size_t len,
589 atmel_aes_fn_t resume)
590 {
591 enum dma_slave_buswidth addr_width;
592 u32 maxburst;
593 int err;
594
595 switch (dd->ctx->block_size) {
596 case CFB8_BLOCK_SIZE:
597 addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
598 maxburst = 1;
599 break;
600
601 case CFB16_BLOCK_SIZE:
602 addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
603 maxburst = 1;
604 break;
605
606 case CFB32_BLOCK_SIZE:
607 case CFB64_BLOCK_SIZE:
608 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
609 maxburst = 1;
610 break;
611
612 case AES_BLOCK_SIZE:
613 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
614 maxburst = dd->caps.max_burst_size;
615 break;
616
617 default:
618 err = -EINVAL;
619 goto exit;
620 }
621
622 err = atmel_aes_map(dd, src, dst, len);
623 if (err)
624 goto exit;
625
626 dd->resume = resume;
627
628 /* Set output DMA transfer first */
629 err = atmel_aes_dma_transfer_start(dd, addr_width, DMA_DEV_TO_MEM,
630 maxburst);
631 if (err)
632 goto unmap;
633
634 /* Then set input DMA transfer */
635 err = atmel_aes_dma_transfer_start(dd, addr_width, DMA_MEM_TO_DEV,
636 maxburst);
637 if (err)
638 goto output_transfer_stop;
639
640 return -EINPROGRESS;
641
642 output_transfer_stop:
643 atmel_aes_dma_transfer_stop(dd, DMA_DEV_TO_MEM);
644 unmap:
645 atmel_aes_unmap(dd);
646 exit:
647 return atmel_aes_complete(dd, err);
648 }
649
650 static void atmel_aes_dma_stop(struct atmel_aes_dev *dd)
651 {
652 atmel_aes_dma_transfer_stop(dd, DMA_MEM_TO_DEV);
653 atmel_aes_dma_transfer_stop(dd, DMA_DEV_TO_MEM);
654 atmel_aes_unmap(dd);
655 }
656
657 static void atmel_aes_dma_callback(void *data)
658 {
659 struct atmel_aes_dev *dd = data;
660
661 atmel_aes_dma_stop(dd);
662 dd->is_async = true;
663 (void)dd->resume(dd);
664 }
665
666 static void atmel_aes_write_ctrl(struct atmel_aes_dev *dd, bool use_dma,
667 const u32 *iv)
668 {
669 u32 valmr = 0;
670
671 /* MR register must be set before IV registers */
672 if (dd->ctx->keylen == AES_KEYSIZE_128)
673 valmr |= AES_MR_KEYSIZE_128;
674 else if (dd->ctx->keylen == AES_KEYSIZE_192)
675 valmr |= AES_MR_KEYSIZE_192;
676 else
677 valmr |= AES_MR_KEYSIZE_256;
678
679 valmr |= dd->flags & AES_FLAGS_MODE_MASK;
680
681 if (use_dma) {
682 valmr |= AES_MR_SMOD_IDATAR0;
683 if (dd->caps.has_dualbuff)
684 valmr |= AES_MR_DUALBUFF;
685 } else {
686 valmr |= AES_MR_SMOD_AUTO;
687 }
688
689 atmel_aes_write(dd, AES_MR, valmr);
690
691 atmel_aes_write_n(dd, AES_KEYWR(0), dd->ctx->key,
692 dd->ctx->keylen >> 2);
693
694 if (iv && (valmr & AES_MR_OPMOD_MASK) != AES_MR_OPMOD_ECB)
695 atmel_aes_write_n(dd, AES_IVR(0), iv, 4);
696 }
697
698 static int atmel_aes_handle_queue(struct atmel_aes_dev *dd,
699 struct crypto_async_request *new_areq)
700 {
701 struct crypto_async_request *areq, *backlog;
702 struct atmel_aes_base_ctx *ctx;
703 unsigned long flags;
704 int err, ret = 0;
705
706 spin_lock_irqsave(&dd->lock, flags);
707 if (new_areq)
708 ret = crypto_enqueue_request(&dd->queue, new_areq);
709 if (dd->flags & AES_FLAGS_BUSY) {
710 spin_unlock_irqrestore(&dd->lock, flags);
711 return ret;
712 }
713 backlog = crypto_get_backlog(&dd->queue);
714 areq = crypto_dequeue_request(&dd->queue);
715 if (areq)
716 dd->flags |= AES_FLAGS_BUSY;
717 spin_unlock_irqrestore(&dd->lock, flags);
718
719 if (!areq)
720 return ret;
721
722 if (backlog)
723 backlog->complete(backlog, -EINPROGRESS);
724
725 ctx = crypto_tfm_ctx(areq->tfm);
726
727 dd->areq = areq;
728 dd->ctx = ctx;
729 dd->is_async = (areq != new_areq);
730
731 err = ctx->start(dd);
732 return (dd->is_async) ? ret : err;
733 }
734
735 static int atmel_aes_transfer_complete(struct atmel_aes_dev *dd)
736 {
737 return atmel_aes_complete(dd, 0);
738 }
739
740 static int atmel_aes_start(struct atmel_aes_dev *dd)
741 {
742 struct ablkcipher_request *req = ablkcipher_request_cast(dd->areq);
743 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
744 bool use_dma = (req->nbytes >= ATMEL_AES_DMA_THRESHOLD ||
745 dd->ctx->block_size != AES_BLOCK_SIZE);
746 int err;
747
748 atmel_aes_set_mode(dd, rctx);
749
750 err = atmel_aes_hw_init(dd);
751 if (err)
752 return atmel_aes_complete(dd, err);
753
754 atmel_aes_write_ctrl(dd, use_dma, req->info);
755 if (use_dma)
756 return atmel_aes_dma_start(dd, req->src, req->dst, req->nbytes,
757 atmel_aes_transfer_complete);
758
759 return atmel_aes_cpu_start(dd, req->src, req->dst, req->nbytes,
760 atmel_aes_transfer_complete);
761 }
762
763
764 static int atmel_aes_buff_init(struct atmel_aes_dev *dd)
765 {
766 dd->buf = (void *)__get_free_pages(GFP_KERNEL, ATMEL_AES_BUFFER_ORDER);
767 dd->buflen = ATMEL_AES_BUFFER_SIZE;
768 dd->buflen &= ~(AES_BLOCK_SIZE - 1);
769
770 if (!dd->buf) {
771 dev_err(dd->dev, "unable to alloc pages.\n");
772 return -ENOMEM;
773 }
774
775 return 0;
776 }
777
778 static void atmel_aes_buff_cleanup(struct atmel_aes_dev *dd)
779 {
780 free_page((unsigned long)dd->buf);
781 }
782
783 static int atmel_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
784 {
785 struct atmel_aes_base_ctx *ctx = crypto_ablkcipher_ctx(
786 crypto_ablkcipher_reqtfm(req));
787 struct atmel_aes_reqctx *rctx = ablkcipher_request_ctx(req);
788 struct atmel_aes_dev *dd;
789
790 switch (mode & AES_FLAGS_OPMODE_MASK) {
791 case AES_FLAGS_CFB8:
792 ctx->block_size = CFB8_BLOCK_SIZE;
793 break;
794
795 case AES_FLAGS_CFB16:
796 ctx->block_size = CFB16_BLOCK_SIZE;
797 break;
798
799 case AES_FLAGS_CFB32:
800 ctx->block_size = CFB32_BLOCK_SIZE;
801 break;
802
803 case AES_FLAGS_CFB64:
804 ctx->block_size = CFB64_BLOCK_SIZE;
805 break;
806
807 default:
808 ctx->block_size = AES_BLOCK_SIZE;
809 break;
810 }
811
812 dd = atmel_aes_find_dev(ctx);
813 if (!dd)
814 return -ENODEV;
815
816 rctx->mode = mode;
817
818 return atmel_aes_handle_queue(dd, &req->base);
819 }
820
821 static bool atmel_aes_filter(struct dma_chan *chan, void *slave)
822 {
823 struct at_dma_slave *sl = slave;
824
825 if (sl && sl->dma_dev == chan->device->dev) {
826 chan->private = sl;
827 return true;
828 } else {
829 return false;
830 }
831 }
832
833 static int atmel_aes_dma_init(struct atmel_aes_dev *dd,
834 struct crypto_platform_data *pdata)
835 {
836 struct at_dma_slave *slave;
837 int err = -ENOMEM;
838 dma_cap_mask_t mask;
839
840 dma_cap_zero(mask);
841 dma_cap_set(DMA_SLAVE, mask);
842
843 /* Try to grab 2 DMA channels */
844 slave = &pdata->dma_slave->rxdata;
845 dd->src.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter,
846 slave, dd->dev, "tx");
847 if (!dd->src.chan)
848 goto err_dma_in;
849
850 slave = &pdata->dma_slave->txdata;
851 dd->dst.chan = dma_request_slave_channel_compat(mask, atmel_aes_filter,
852 slave, dd->dev, "rx");
853 if (!dd->dst.chan)
854 goto err_dma_out;
855
856 return 0;
857
858 err_dma_out:
859 dma_release_channel(dd->src.chan);
860 err_dma_in:
861 dev_warn(dd->dev, "no DMA channel available\n");
862 return err;
863 }
864
865 static void atmel_aes_dma_cleanup(struct atmel_aes_dev *dd)
866 {
867 dma_release_channel(dd->dst.chan);
868 dma_release_channel(dd->src.chan);
869 }
870
871 static int atmel_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
872 unsigned int keylen)
873 {
874 struct atmel_aes_base_ctx *ctx = crypto_ablkcipher_ctx(tfm);
875
876 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
877 keylen != AES_KEYSIZE_256) {
878 crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
879 return -EINVAL;
880 }
881
882 memcpy(ctx->key, key, keylen);
883 ctx->keylen = keylen;
884
885 return 0;
886 }
887
888 static int atmel_aes_ecb_encrypt(struct ablkcipher_request *req)
889 {
890 return atmel_aes_crypt(req, AES_FLAGS_ECB | AES_FLAGS_ENCRYPT);
891 }
892
893 static int atmel_aes_ecb_decrypt(struct ablkcipher_request *req)
894 {
895 return atmel_aes_crypt(req, AES_FLAGS_ECB);
896 }
897
898 static int atmel_aes_cbc_encrypt(struct ablkcipher_request *req)
899 {
900 return atmel_aes_crypt(req,
901 AES_FLAGS_ENCRYPT | AES_FLAGS_CBC);
902 }
903
904 static int atmel_aes_cbc_decrypt(struct ablkcipher_request *req)
905 {
906 return atmel_aes_crypt(req,
907 AES_FLAGS_CBC);
908 }
909
910 static int atmel_aes_ofb_encrypt(struct ablkcipher_request *req)
911 {
912 return atmel_aes_crypt(req,
913 AES_FLAGS_ENCRYPT | AES_FLAGS_OFB);
914 }
915
916 static int atmel_aes_ofb_decrypt(struct ablkcipher_request *req)
917 {
918 return atmel_aes_crypt(req,
919 AES_FLAGS_OFB);
920 }
921
922 static int atmel_aes_cfb_encrypt(struct ablkcipher_request *req)
923 {
924 return atmel_aes_crypt(req, AES_FLAGS_CFB128 | AES_FLAGS_ENCRYPT);
925 }
926
927 static int atmel_aes_cfb_decrypt(struct ablkcipher_request *req)
928 {
929 return atmel_aes_crypt(req, AES_FLAGS_CFB128);
930 }
931
932 static int atmel_aes_cfb64_encrypt(struct ablkcipher_request *req)
933 {
934 return atmel_aes_crypt(req, AES_FLAGS_CFB64 | AES_FLAGS_ENCRYPT);
935 }
936
937 static int atmel_aes_cfb64_decrypt(struct ablkcipher_request *req)
938 {
939 return atmel_aes_crypt(req, AES_FLAGS_CFB64);
940 }
941
942 static int atmel_aes_cfb32_encrypt(struct ablkcipher_request *req)
943 {
944 return atmel_aes_crypt(req, AES_FLAGS_CFB32 | AES_FLAGS_ENCRYPT);
945 }
946
947 static int atmel_aes_cfb32_decrypt(struct ablkcipher_request *req)
948 {
949 return atmel_aes_crypt(req, AES_FLAGS_CFB32);
950 }
951
952 static int atmel_aes_cfb16_encrypt(struct ablkcipher_request *req)
953 {
954 return atmel_aes_crypt(req, AES_FLAGS_CFB16 | AES_FLAGS_ENCRYPT);
955 }
956
957 static int atmel_aes_cfb16_decrypt(struct ablkcipher_request *req)
958 {
959 return atmel_aes_crypt(req, AES_FLAGS_CFB16);
960 }
961
962 static int atmel_aes_cfb8_encrypt(struct ablkcipher_request *req)
963 {
964 return atmel_aes_crypt(req, AES_FLAGS_CFB8 | AES_FLAGS_ENCRYPT);
965 }
966
967 static int atmel_aes_cfb8_decrypt(struct ablkcipher_request *req)
968 {
969 return atmel_aes_crypt(req, AES_FLAGS_CFB8);
970 }
971
972 static int atmel_aes_ctr_encrypt(struct ablkcipher_request *req)
973 {
974 return atmel_aes_crypt(req,
975 AES_FLAGS_ENCRYPT | AES_FLAGS_CTR);
976 }
977
978 static int atmel_aes_ctr_decrypt(struct ablkcipher_request *req)
979 {
980 return atmel_aes_crypt(req,
981 AES_FLAGS_CTR);
982 }
983
984 static int atmel_aes_cra_init(struct crypto_tfm *tfm)
985 {
986 struct atmel_aes_ctx *ctx = crypto_tfm_ctx(tfm);
987
988 tfm->crt_ablkcipher.reqsize = sizeof(struct atmel_aes_reqctx);
989 ctx->base.start = atmel_aes_start;
990
991 return 0;
992 }
993
994 static void atmel_aes_cra_exit(struct crypto_tfm *tfm)
995 {
996 }
997
998 static struct crypto_alg aes_algs[] = {
999 {
1000 .cra_name = "ecb(aes)",
1001 .cra_driver_name = "atmel-ecb-aes",
1002 .cra_priority = ATMEL_AES_PRIORITY,
1003 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1004 .cra_blocksize = AES_BLOCK_SIZE,
1005 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1006 .cra_alignmask = 0xf,
1007 .cra_type = &crypto_ablkcipher_type,
1008 .cra_module = THIS_MODULE,
1009 .cra_init = atmel_aes_cra_init,
1010 .cra_exit = atmel_aes_cra_exit,
1011 .cra_u.ablkcipher = {
1012 .min_keysize = AES_MIN_KEY_SIZE,
1013 .max_keysize = AES_MAX_KEY_SIZE,
1014 .setkey = atmel_aes_setkey,
1015 .encrypt = atmel_aes_ecb_encrypt,
1016 .decrypt = atmel_aes_ecb_decrypt,
1017 }
1018 },
1019 {
1020 .cra_name = "cbc(aes)",
1021 .cra_driver_name = "atmel-cbc-aes",
1022 .cra_priority = ATMEL_AES_PRIORITY,
1023 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1024 .cra_blocksize = AES_BLOCK_SIZE,
1025 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1026 .cra_alignmask = 0xf,
1027 .cra_type = &crypto_ablkcipher_type,
1028 .cra_module = THIS_MODULE,
1029 .cra_init = atmel_aes_cra_init,
1030 .cra_exit = atmel_aes_cra_exit,
1031 .cra_u.ablkcipher = {
1032 .min_keysize = AES_MIN_KEY_SIZE,
1033 .max_keysize = AES_MAX_KEY_SIZE,
1034 .ivsize = AES_BLOCK_SIZE,
1035 .setkey = atmel_aes_setkey,
1036 .encrypt = atmel_aes_cbc_encrypt,
1037 .decrypt = atmel_aes_cbc_decrypt,
1038 }
1039 },
1040 {
1041 .cra_name = "ofb(aes)",
1042 .cra_driver_name = "atmel-ofb-aes",
1043 .cra_priority = ATMEL_AES_PRIORITY,
1044 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1045 .cra_blocksize = AES_BLOCK_SIZE,
1046 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1047 .cra_alignmask = 0xf,
1048 .cra_type = &crypto_ablkcipher_type,
1049 .cra_module = THIS_MODULE,
1050 .cra_init = atmel_aes_cra_init,
1051 .cra_exit = atmel_aes_cra_exit,
1052 .cra_u.ablkcipher = {
1053 .min_keysize = AES_MIN_KEY_SIZE,
1054 .max_keysize = AES_MAX_KEY_SIZE,
1055 .ivsize = AES_BLOCK_SIZE,
1056 .setkey = atmel_aes_setkey,
1057 .encrypt = atmel_aes_ofb_encrypt,
1058 .decrypt = atmel_aes_ofb_decrypt,
1059 }
1060 },
1061 {
1062 .cra_name = "cfb(aes)",
1063 .cra_driver_name = "atmel-cfb-aes",
1064 .cra_priority = ATMEL_AES_PRIORITY,
1065 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1066 .cra_blocksize = AES_BLOCK_SIZE,
1067 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1068 .cra_alignmask = 0xf,
1069 .cra_type = &crypto_ablkcipher_type,
1070 .cra_module = THIS_MODULE,
1071 .cra_init = atmel_aes_cra_init,
1072 .cra_exit = atmel_aes_cra_exit,
1073 .cra_u.ablkcipher = {
1074 .min_keysize = AES_MIN_KEY_SIZE,
1075 .max_keysize = AES_MAX_KEY_SIZE,
1076 .ivsize = AES_BLOCK_SIZE,
1077 .setkey = atmel_aes_setkey,
1078 .encrypt = atmel_aes_cfb_encrypt,
1079 .decrypt = atmel_aes_cfb_decrypt,
1080 }
1081 },
1082 {
1083 .cra_name = "cfb32(aes)",
1084 .cra_driver_name = "atmel-cfb32-aes",
1085 .cra_priority = ATMEL_AES_PRIORITY,
1086 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1087 .cra_blocksize = CFB32_BLOCK_SIZE,
1088 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1089 .cra_alignmask = 0x3,
1090 .cra_type = &crypto_ablkcipher_type,
1091 .cra_module = THIS_MODULE,
1092 .cra_init = atmel_aes_cra_init,
1093 .cra_exit = atmel_aes_cra_exit,
1094 .cra_u.ablkcipher = {
1095 .min_keysize = AES_MIN_KEY_SIZE,
1096 .max_keysize = AES_MAX_KEY_SIZE,
1097 .ivsize = AES_BLOCK_SIZE,
1098 .setkey = atmel_aes_setkey,
1099 .encrypt = atmel_aes_cfb32_encrypt,
1100 .decrypt = atmel_aes_cfb32_decrypt,
1101 }
1102 },
1103 {
1104 .cra_name = "cfb16(aes)",
1105 .cra_driver_name = "atmel-cfb16-aes",
1106 .cra_priority = ATMEL_AES_PRIORITY,
1107 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1108 .cra_blocksize = CFB16_BLOCK_SIZE,
1109 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1110 .cra_alignmask = 0x1,
1111 .cra_type = &crypto_ablkcipher_type,
1112 .cra_module = THIS_MODULE,
1113 .cra_init = atmel_aes_cra_init,
1114 .cra_exit = atmel_aes_cra_exit,
1115 .cra_u.ablkcipher = {
1116 .min_keysize = AES_MIN_KEY_SIZE,
1117 .max_keysize = AES_MAX_KEY_SIZE,
1118 .ivsize = AES_BLOCK_SIZE,
1119 .setkey = atmel_aes_setkey,
1120 .encrypt = atmel_aes_cfb16_encrypt,
1121 .decrypt = atmel_aes_cfb16_decrypt,
1122 }
1123 },
1124 {
1125 .cra_name = "cfb8(aes)",
1126 .cra_driver_name = "atmel-cfb8-aes",
1127 .cra_priority = ATMEL_AES_PRIORITY,
1128 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1129 .cra_blocksize = CFB8_BLOCK_SIZE,
1130 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1131 .cra_alignmask = 0x0,
1132 .cra_type = &crypto_ablkcipher_type,
1133 .cra_module = THIS_MODULE,
1134 .cra_init = atmel_aes_cra_init,
1135 .cra_exit = atmel_aes_cra_exit,
1136 .cra_u.ablkcipher = {
1137 .min_keysize = AES_MIN_KEY_SIZE,
1138 .max_keysize = AES_MAX_KEY_SIZE,
1139 .ivsize = AES_BLOCK_SIZE,
1140 .setkey = atmel_aes_setkey,
1141 .encrypt = atmel_aes_cfb8_encrypt,
1142 .decrypt = atmel_aes_cfb8_decrypt,
1143 }
1144 },
1145 {
1146 .cra_name = "ctr(aes)",
1147 .cra_driver_name = "atmel-ctr-aes",
1148 .cra_priority = ATMEL_AES_PRIORITY,
1149 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1150 .cra_blocksize = AES_BLOCK_SIZE,
1151 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1152 .cra_alignmask = 0xf,
1153 .cra_type = &crypto_ablkcipher_type,
1154 .cra_module = THIS_MODULE,
1155 .cra_init = atmel_aes_cra_init,
1156 .cra_exit = atmel_aes_cra_exit,
1157 .cra_u.ablkcipher = {
1158 .min_keysize = AES_MIN_KEY_SIZE,
1159 .max_keysize = AES_MAX_KEY_SIZE,
1160 .ivsize = AES_BLOCK_SIZE,
1161 .setkey = atmel_aes_setkey,
1162 .encrypt = atmel_aes_ctr_encrypt,
1163 .decrypt = atmel_aes_ctr_decrypt,
1164 }
1165 },
1166 };
1167
1168 static struct crypto_alg aes_cfb64_alg = {
1169 .cra_name = "cfb64(aes)",
1170 .cra_driver_name = "atmel-cfb64-aes",
1171 .cra_priority = ATMEL_AES_PRIORITY,
1172 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1173 .cra_blocksize = CFB64_BLOCK_SIZE,
1174 .cra_ctxsize = sizeof(struct atmel_aes_ctx),
1175 .cra_alignmask = 0x7,
1176 .cra_type = &crypto_ablkcipher_type,
1177 .cra_module = THIS_MODULE,
1178 .cra_init = atmel_aes_cra_init,
1179 .cra_exit = atmel_aes_cra_exit,
1180 .cra_u.ablkcipher = {
1181 .min_keysize = AES_MIN_KEY_SIZE,
1182 .max_keysize = AES_MAX_KEY_SIZE,
1183 .ivsize = AES_BLOCK_SIZE,
1184 .setkey = atmel_aes_setkey,
1185 .encrypt = atmel_aes_cfb64_encrypt,
1186 .decrypt = atmel_aes_cfb64_decrypt,
1187 }
1188 };
1189
1190 static void atmel_aes_queue_task(unsigned long data)
1191 {
1192 struct atmel_aes_dev *dd = (struct atmel_aes_dev *)data;
1193
1194 atmel_aes_handle_queue(dd, NULL);
1195 }
1196
1197 static void atmel_aes_done_task(unsigned long data)
1198 {
1199 struct atmel_aes_dev *dd = (struct atmel_aes_dev *) data;
1200
1201 dd->is_async = true;
1202 (void)dd->resume(dd);
1203 }
1204
1205 static irqreturn_t atmel_aes_irq(int irq, void *dev_id)
1206 {
1207 struct atmel_aes_dev *aes_dd = dev_id;
1208 u32 reg;
1209
1210 reg = atmel_aes_read(aes_dd, AES_ISR);
1211 if (reg & atmel_aes_read(aes_dd, AES_IMR)) {
1212 atmel_aes_write(aes_dd, AES_IDR, reg);
1213 if (AES_FLAGS_BUSY & aes_dd->flags)
1214 tasklet_schedule(&aes_dd->done_task);
1215 else
1216 dev_warn(aes_dd->dev, "AES interrupt when no active requests.\n");
1217 return IRQ_HANDLED;
1218 }
1219
1220 return IRQ_NONE;
1221 }
1222
1223 static void atmel_aes_unregister_algs(struct atmel_aes_dev *dd)
1224 {
1225 int i;
1226
1227 if (dd->caps.has_cfb64)
1228 crypto_unregister_alg(&aes_cfb64_alg);
1229
1230 for (i = 0; i < ARRAY_SIZE(aes_algs); i++)
1231 crypto_unregister_alg(&aes_algs[i]);
1232 }
1233
1234 static int atmel_aes_register_algs(struct atmel_aes_dev *dd)
1235 {
1236 int err, i, j;
1237
1238 for (i = 0; i < ARRAY_SIZE(aes_algs); i++) {
1239 err = crypto_register_alg(&aes_algs[i]);
1240 if (err)
1241 goto err_aes_algs;
1242 }
1243
1244 if (dd->caps.has_cfb64) {
1245 err = crypto_register_alg(&aes_cfb64_alg);
1246 if (err)
1247 goto err_aes_cfb64_alg;
1248 }
1249
1250 return 0;
1251
1252 err_aes_cfb64_alg:
1253 i = ARRAY_SIZE(aes_algs);
1254 err_aes_algs:
1255 for (j = 0; j < i; j++)
1256 crypto_unregister_alg(&aes_algs[j]);
1257
1258 return err;
1259 }
1260
1261 static void atmel_aes_get_cap(struct atmel_aes_dev *dd)
1262 {
1263 dd->caps.has_dualbuff = 0;
1264 dd->caps.has_cfb64 = 0;
1265 dd->caps.max_burst_size = 1;
1266
1267 /* keep only major version number */
1268 switch (dd->hw_version & 0xff0) {
1269 case 0x500:
1270 dd->caps.has_dualbuff = 1;
1271 dd->caps.has_cfb64 = 1;
1272 dd->caps.max_burst_size = 4;
1273 break;
1274 case 0x200:
1275 dd->caps.has_dualbuff = 1;
1276 dd->caps.has_cfb64 = 1;
1277 dd->caps.max_burst_size = 4;
1278 break;
1279 case 0x130:
1280 dd->caps.has_dualbuff = 1;
1281 dd->caps.has_cfb64 = 1;
1282 dd->caps.max_burst_size = 4;
1283 break;
1284 case 0x120:
1285 break;
1286 default:
1287 dev_warn(dd->dev,
1288 "Unmanaged aes version, set minimum capabilities\n");
1289 break;
1290 }
1291 }
1292
1293 #if defined(CONFIG_OF)
1294 static const struct of_device_id atmel_aes_dt_ids[] = {
1295 { .compatible = "atmel,at91sam9g46-aes" },
1296 { /* sentinel */ }
1297 };
1298 MODULE_DEVICE_TABLE(of, atmel_aes_dt_ids);
1299
1300 static struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev)
1301 {
1302 struct device_node *np = pdev->dev.of_node;
1303 struct crypto_platform_data *pdata;
1304
1305 if (!np) {
1306 dev_err(&pdev->dev, "device node not found\n");
1307 return ERR_PTR(-EINVAL);
1308 }
1309
1310 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1311 if (!pdata) {
1312 dev_err(&pdev->dev, "could not allocate memory for pdata\n");
1313 return ERR_PTR(-ENOMEM);
1314 }
1315
1316 pdata->dma_slave = devm_kzalloc(&pdev->dev,
1317 sizeof(*(pdata->dma_slave)),
1318 GFP_KERNEL);
1319 if (!pdata->dma_slave) {
1320 dev_err(&pdev->dev, "could not allocate memory for dma_slave\n");
1321 devm_kfree(&pdev->dev, pdata);
1322 return ERR_PTR(-ENOMEM);
1323 }
1324
1325 return pdata;
1326 }
1327 #else
1328 static inline struct crypto_platform_data *atmel_aes_of_init(struct platform_device *pdev)
1329 {
1330 return ERR_PTR(-EINVAL);
1331 }
1332 #endif
1333
1334 static int atmel_aes_probe(struct platform_device *pdev)
1335 {
1336 struct atmel_aes_dev *aes_dd;
1337 struct crypto_platform_data *pdata;
1338 struct device *dev = &pdev->dev;
1339 struct resource *aes_res;
1340 int err;
1341
1342 pdata = pdev->dev.platform_data;
1343 if (!pdata) {
1344 pdata = atmel_aes_of_init(pdev);
1345 if (IS_ERR(pdata)) {
1346 err = PTR_ERR(pdata);
1347 goto aes_dd_err;
1348 }
1349 }
1350
1351 if (!pdata->dma_slave) {
1352 err = -ENXIO;
1353 goto aes_dd_err;
1354 }
1355
1356 aes_dd = devm_kzalloc(&pdev->dev, sizeof(*aes_dd), GFP_KERNEL);
1357 if (aes_dd == NULL) {
1358 dev_err(dev, "unable to alloc data struct.\n");
1359 err = -ENOMEM;
1360 goto aes_dd_err;
1361 }
1362
1363 aes_dd->dev = dev;
1364
1365 platform_set_drvdata(pdev, aes_dd);
1366
1367 INIT_LIST_HEAD(&aes_dd->list);
1368 spin_lock_init(&aes_dd->lock);
1369
1370 tasklet_init(&aes_dd->done_task, atmel_aes_done_task,
1371 (unsigned long)aes_dd);
1372 tasklet_init(&aes_dd->queue_task, atmel_aes_queue_task,
1373 (unsigned long)aes_dd);
1374
1375 crypto_init_queue(&aes_dd->queue, ATMEL_AES_QUEUE_LENGTH);
1376
1377 aes_dd->irq = -1;
1378
1379 /* Get the base address */
1380 aes_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1381 if (!aes_res) {
1382 dev_err(dev, "no MEM resource info\n");
1383 err = -ENODEV;
1384 goto res_err;
1385 }
1386 aes_dd->phys_base = aes_res->start;
1387
1388 /* Get the IRQ */
1389 aes_dd->irq = platform_get_irq(pdev, 0);
1390 if (aes_dd->irq < 0) {
1391 dev_err(dev, "no IRQ resource info\n");
1392 err = aes_dd->irq;
1393 goto res_err;
1394 }
1395
1396 err = devm_request_irq(&pdev->dev, aes_dd->irq, atmel_aes_irq,
1397 IRQF_SHARED, "atmel-aes", aes_dd);
1398 if (err) {
1399 dev_err(dev, "unable to request aes irq.\n");
1400 goto res_err;
1401 }
1402
1403 /* Initializing the clock */
1404 aes_dd->iclk = devm_clk_get(&pdev->dev, "aes_clk");
1405 if (IS_ERR(aes_dd->iclk)) {
1406 dev_err(dev, "clock initialization failed.\n");
1407 err = PTR_ERR(aes_dd->iclk);
1408 goto res_err;
1409 }
1410
1411 aes_dd->io_base = devm_ioremap_resource(&pdev->dev, aes_res);
1412 if (!aes_dd->io_base) {
1413 dev_err(dev, "can't ioremap\n");
1414 err = -ENOMEM;
1415 goto res_err;
1416 }
1417
1418 err = atmel_aes_hw_version_init(aes_dd);
1419 if (err)
1420 goto res_err;
1421
1422 atmel_aes_get_cap(aes_dd);
1423
1424 err = atmel_aes_buff_init(aes_dd);
1425 if (err)
1426 goto err_aes_buff;
1427
1428 err = atmel_aes_dma_init(aes_dd, pdata);
1429 if (err)
1430 goto err_aes_dma;
1431
1432 spin_lock(&atmel_aes.lock);
1433 list_add_tail(&aes_dd->list, &atmel_aes.dev_list);
1434 spin_unlock(&atmel_aes.lock);
1435
1436 err = atmel_aes_register_algs(aes_dd);
1437 if (err)
1438 goto err_algs;
1439
1440 dev_info(dev, "Atmel AES - Using %s, %s for DMA transfers\n",
1441 dma_chan_name(aes_dd->src.chan),
1442 dma_chan_name(aes_dd->dst.chan));
1443
1444 return 0;
1445
1446 err_algs:
1447 spin_lock(&atmel_aes.lock);
1448 list_del(&aes_dd->list);
1449 spin_unlock(&atmel_aes.lock);
1450 atmel_aes_dma_cleanup(aes_dd);
1451 err_aes_dma:
1452 atmel_aes_buff_cleanup(aes_dd);
1453 err_aes_buff:
1454 res_err:
1455 tasklet_kill(&aes_dd->done_task);
1456 tasklet_kill(&aes_dd->queue_task);
1457 aes_dd_err:
1458 dev_err(dev, "initialization failed.\n");
1459
1460 return err;
1461 }
1462
1463 static int atmel_aes_remove(struct platform_device *pdev)
1464 {
1465 static struct atmel_aes_dev *aes_dd;
1466
1467 aes_dd = platform_get_drvdata(pdev);
1468 if (!aes_dd)
1469 return -ENODEV;
1470 spin_lock(&atmel_aes.lock);
1471 list_del(&aes_dd->list);
1472 spin_unlock(&atmel_aes.lock);
1473
1474 atmel_aes_unregister_algs(aes_dd);
1475
1476 tasklet_kill(&aes_dd->done_task);
1477 tasklet_kill(&aes_dd->queue_task);
1478
1479 atmel_aes_dma_cleanup(aes_dd);
1480 atmel_aes_buff_cleanup(aes_dd);
1481
1482 return 0;
1483 }
1484
1485 static struct platform_driver atmel_aes_driver = {
1486 .probe = atmel_aes_probe,
1487 .remove = atmel_aes_remove,
1488 .driver = {
1489 .name = "atmel_aes",
1490 .of_match_table = of_match_ptr(atmel_aes_dt_ids),
1491 },
1492 };
1493
1494 module_platform_driver(atmel_aes_driver);
1495
1496 MODULE_DESCRIPTION("Atmel AES hw acceleration support.");
1497 MODULE_LICENSE("GPL v2");
1498 MODULE_AUTHOR("Nicolas Royer - Eukréa Electromatique");
Linux kernel - Deliverables
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