drivers/crypto/caam/regs.h

   1 /*
   2  * CAAM hardware register-level view
   3  *
   4  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   5  */
   6
   7 #ifndef REGS_H
   8 #define REGS_H
   9
  10 #include <linux/types.h>
  11 #include <linux/io.h>
  12
  13 /*
  14  * Architecture-specific register access methods
  15  *
  16  * CAAM's bus-addressable registers are 64 bits internally.
  17  * They have been wired to be safely accessible on 32-bit
  18  * architectures, however. Registers were organized such
  19  * that (a) they can be contained in 32 bits, (b) if not, then they
  20  * can be treated as two 32-bit entities, or finally (c) if they
  21  * must be treated as a single 64-bit value, then this can safely
  22  * be done with two 32-bit cycles.
  23  *
  24  * For 32-bit operations on 64-bit values, CAAM follows the same
  25  * 64-bit register access conventions as it's predecessors, in that
  26  * writes are "triggered" by a write to the register at the numerically
  27  * higher address, thus, a full 64-bit write cycle requires a write
  28  * to the lower address, followed by a write to the higher address,
  29  * which will latch/execute the write cycle.
  30  *
  31  * For example, let's assume a SW reset of CAAM through the master
  32  * configuration register.
  33  * - SWRST is in bit 31 of MCFG.
  34  * - MCFG begins at base+0x0000.
  35  * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower)
  36  * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher)
  37  *
  38  * (and on Power, the convention is 0-31, 32-63, I know...)
  39  *
  40  * Assuming a 64-bit write to this MCFG to perform a software reset
  41  * would then require a write of 0 to base+0x0000, followed by a
  42  * write of 0x80000000 to base+0x0004, which would "execute" the
  43  * reset.
  44  *
  45  * Of course, since MCFG 63-32 is all zero, we could cheat and simply
  46  * write 0x8000000 to base+0x0004, and the reset would work fine.
  47  * However, since CAAM does contain some write-and-read-intended
  48  * 64-bit registers, this code defines 64-bit access methods for
  49  * the sake of internal consistency and simplicity, and so that a
  50  * clean transition to 64-bit is possible when it becomes necessary.
  51  *
  52  * There are limitations to this that the developer must recognize.
  53  * 32-bit architectures cannot enforce an atomic-64 operation,
  54  * Therefore:
  55  *
  56  * - On writes, since the HW is assumed to latch the cycle on the
  57  *   write of the higher-numeric-address word, then ordered
  58  *   writes work OK.
  59  *
  60  * - For reads, where a register contains a relevant value of more
  61  *   that 32 bits, the hardware employs logic to latch the other
  62  *   "half" of the data until read, ensuring an accurate value.
  63  *   This is of particular relevance when dealing with CAAM's
  64  *   performance counters.
  65  *
  66  */
  67
  68 #ifdef CONFIG_ARM
  69 /* These are common macros for Power, put here for ARM */
  70 #define setbits32(_addr, _v) writel((readl(_addr) | (_v)), (_addr))
  71 #define clrbits32(_addr, _v) writel((readl(_addr) & ~(_v)), (_addr))
  72
  73 #define out_arch(type, endian, a, v)    __raw_write##type(cpu_to_##endian(v), a)
  74 #define in_arch(type, endian, a)        endian##_to_cpu(__raw_read##type(a))
  75
  76 #define out_le32(a, v)  out_arch(l, le32, a, v)
  77 #define in_le32(a)      in_arch(l, le32, a)
  78
  79 #define out_be32(a, v)  out_arch(l, be32, a, v)
  80 #define in_be32(a)      in_arch(l, be32, a)
  81
  82 #define clrsetbits(type, addr, clear, set) \
  83         out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
  84
  85 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
  86 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
  87 #endif
  88
  89 #ifdef __BIG_ENDIAN
  90 #define wr_reg32(reg, data) out_be32(reg, data)
  91 #define rd_reg32(reg) in_be32(reg)
  92 #define clrsetbits_32(addr, clear, set) clrsetbits_be32(addr, clear, set)
  93 #ifdef CONFIG_64BIT
  94 #define wr_reg64(reg, data) out_be64(reg, data)
  95 #define rd_reg64(reg) in_be64(reg)
  96 #endif
  97 #else
  98 #ifdef __LITTLE_ENDIAN
  99 #define wr_reg32(reg, data) __raw_writel(data, reg)
 100 #define rd_reg32(reg) __raw_readl(reg)
 101 #define clrsetbits_32(addr, clear, set) clrsetbits_le32(addr, clear, set)
 102 #ifdef CONFIG_64BIT
 103 #define wr_reg64(reg, data) __raw_writeq(data, reg)
 104 #define rd_reg64(reg) __raw_readq(reg)
 105 #endif
 106 #endif
 107 #endif
 108
 109 /*
 110  * The only users of these wr/rd_reg64 functions is the Job Ring (JR).
 111  * The DMA address registers in the JR are a pair of 32-bit registers.
 112  * The layout is:
 113  *
 114  *    base + 0x0000 : most-significant 32 bits
 115  *    base + 0x0004 : least-significant 32 bits
 116  *
 117  * The 32-bit version of this core therefore has to write to base + 0x0004
 118  * to set the 32-bit wide DMA address. This seems to be independent of the
 119  * endianness of the written/read data.
 120  */
 121
 122 #ifndef CONFIG_64BIT
 123 #define REG64_MS32(reg) ((u32 __iomem *)(reg))
 124 #define REG64_LS32(reg) ((u32 __iomem *)(reg) + 1)
 125
 126 static inline void wr_reg64(u64 __iomem *reg, u64 data)
 127 {
 128         wr_reg32(REG64_MS32(reg), data >> 32);
 129         wr_reg32(REG64_LS32(reg), data);
 130 }
 131
 132 static inline u64 rd_reg64(u64 __iomem *reg)
 133 {
 134         return ((u64)rd_reg32(REG64_MS32(reg)) << 32 |
 135                 (u64)rd_reg32(REG64_LS32(reg)));
 136 }
 137 #endif
 138
 139 /*
 140  * jr_outentry
 141  * Represents each entry in a JobR output ring
 142  */
 143 struct jr_outentry {
 144         dma_addr_t desc;/* Pointer to completed descriptor */
 145         u32 jrstatus;   /* Status for completed descriptor */
 146 } __packed;
 147
 148 /*
 149  * caam_perfmon - Performance Monitor/Secure Memory Status/
 150  *                CAAM Global Status/Component Version IDs
 151  *
 152  * Spans f00-fff wherever instantiated
 153  */
 154
 155 /* Number of DECOs */
 156 #define CHA_NUM_MS_DECONUM_SHIFT        24
 157 #define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT)
 158
 159 /*
 160  * CHA version IDs / instantiation bitfields
 161  * Defined for use with the cha_id fields in perfmon, but the same shift/mask
 162  * selectors can be used to pull out the number of instantiated blocks within
 163  * cha_num fields in perfmon because the locations are the same.
 164  */
 165 #define CHA_ID_LS_AES_SHIFT     0
 166 #define CHA_ID_LS_AES_MASK      (0xfull << CHA_ID_LS_AES_SHIFT)
 167 #define CHA_ID_LS_AES_LP        (0x3ull << CHA_ID_LS_AES_SHIFT)
 168 #define CHA_ID_LS_AES_HP        (0x4ull << CHA_ID_LS_AES_SHIFT)
 169
 170 #define CHA_ID_LS_DES_SHIFT     4
 171 #define CHA_ID_LS_DES_MASK      (0xfull << CHA_ID_LS_DES_SHIFT)
 172
 173 #define CHA_ID_LS_ARC4_SHIFT    8
 174 #define CHA_ID_LS_ARC4_MASK     (0xfull << CHA_ID_LS_ARC4_SHIFT)
 175
 176 #define CHA_ID_LS_MD_SHIFT      12
 177 #define CHA_ID_LS_MD_MASK       (0xfull << CHA_ID_LS_MD_SHIFT)
 178 #define CHA_ID_LS_MD_LP256      (0x0ull << CHA_ID_LS_MD_SHIFT)
 179 #define CHA_ID_LS_MD_LP512      (0x1ull << CHA_ID_LS_MD_SHIFT)
 180 #define CHA_ID_LS_MD_HP         (0x2ull << CHA_ID_LS_MD_SHIFT)
 181
 182 #define CHA_ID_LS_RNG_SHIFT     16
 183 #define CHA_ID_LS_RNG_MASK      (0xfull << CHA_ID_LS_RNG_SHIFT)
 184
 185 #define CHA_ID_LS_SNW8_SHIFT    20
 186 #define CHA_ID_LS_SNW8_MASK     (0xfull << CHA_ID_LS_SNW8_SHIFT)
 187
 188 #define CHA_ID_LS_KAS_SHIFT     24
 189 #define CHA_ID_LS_KAS_MASK      (0xfull << CHA_ID_LS_KAS_SHIFT)
 190
 191 #define CHA_ID_LS_PK_SHIFT      28
 192 #define CHA_ID_LS_PK_MASK       (0xfull << CHA_ID_LS_PK_SHIFT)
 193
 194 #define CHA_ID_MS_CRC_SHIFT     0
 195 #define CHA_ID_MS_CRC_MASK      (0xfull << CHA_ID_MS_CRC_SHIFT)
 196
 197 #define CHA_ID_MS_SNW9_SHIFT    4
 198 #define CHA_ID_MS_SNW9_MASK     (0xfull << CHA_ID_MS_SNW9_SHIFT)
 199
 200 #define CHA_ID_MS_DECO_SHIFT    24
 201 #define CHA_ID_MS_DECO_MASK     (0xfull << CHA_ID_MS_DECO_SHIFT)
 202
 203 #define CHA_ID_MS_JR_SHIFT      28
 204 #define CHA_ID_MS_JR_MASK       (0xfull << CHA_ID_MS_JR_SHIFT)
 205
 206 struct sec_vid {
 207         u16 ip_id;
 208         u8 maj_rev;
 209         u8 min_rev;
 210 };
 211
 212 struct caam_perfmon {
 213         /* Performance Monitor Registers                        f00-f9f */
 214         u64 req_dequeued;       /* PC_REQ_DEQ - Dequeued Requests            */
 215         u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */
 216         u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests  */
 217         u64 ob_enc_bytes;       /* PC_OB_ENCRYPT - Outbound Bytes Encrypted  */
 218         u64 ob_prot_bytes;      /* PC_OB_PROTECT - Outbound Bytes Protected  */
 219         u64 ib_dec_bytes;       /* PC_IB_DECRYPT - Inbound Bytes Decrypted   */
 220         u64 ib_valid_bytes;     /* PC_IB_VALIDATED Inbound Bytes Validated   */
 221         u64 rsvd[13];
 222
 223         /* CAAM Hardware Instantiation Parameters               fa0-fbf */
 224         u32 cha_rev_ms;         /* CRNR - CHA Rev No. Most significant half*/
 225         u32 cha_rev_ls;         /* CRNR - CHA Rev No. Least significant half*/
 226 #define CTPR_MS_QI_SHIFT        25
 227 #define CTPR_MS_QI_MASK         (0x1ull << CTPR_MS_QI_SHIFT)
 228 #define CTPR_MS_VIRT_EN_INCL    0x00000001
 229 #define CTPR_MS_VIRT_EN_POR     0x00000002
 230 #define CTPR_MS_PG_SZ_MASK      0x10
 231 #define CTPR_MS_PG_SZ_SHIFT     4
 232         u32 comp_parms_ms;      /* CTPR - Compile Parameters Register   */
 233         u32 comp_parms_ls;      /* CTPR - Compile Parameters Register   */
 234         u64 rsvd1[2];
 235
 236         /* CAAM Global Status                                   fc0-fdf */
 237         u64 faultaddr;  /* FAR  - Fault Address         */
 238         u32 faultliodn; /* FALR - Fault Address LIODN   */
 239         u32 faultdetail;        /* FADR - Fault Addr Detail     */
 240         u32 rsvd2;
 241         u32 status;             /* CSTA - CAAM Status */
 242         u64 rsvd3;
 243
 244         /* Component Instantiation Parameters                   fe0-fff */
 245         u32 rtic_id;            /* RVID - RTIC Version ID       */
 246         u32 ccb_id;             /* CCBVID - CCB Version ID      */
 247         u32 cha_id_ms;          /* CHAVID - CHA Version ID Most Significant*/
 248         u32 cha_id_ls;          /* CHAVID - CHA Version ID Least Significant*/
 249         u32 cha_num_ms;         /* CHANUM - CHA Number Most Significant */
 250         u32 cha_num_ls;         /* CHANUM - CHA Number Least Significant*/
 251         u32 caam_id_ms;         /* CAAMVID - CAAM Version ID MS */
 252         u32 caam_id_ls;         /* CAAMVID - CAAM Version ID LS */
 253 };
 254
 255 /* LIODN programming for DMA configuration */
 256 #define MSTRID_LOCK_LIODN       0x80000000
 257 #define MSTRID_LOCK_MAKETRUSTED 0x00010000      /* only for JR masterid */
 258
 259 #define MSTRID_LIODN_MASK       0x0fff
 260 struct masterid {
 261         u32 liodn_ms;   /* lock and make-trusted control bits */
 262         u32 liodn_ls;   /* LIODN for non-sequence and seq access */
 263 };
 264
 265 /* Partition ID for DMA configuration */
 266 struct partid {
 267         u32 rsvd1;
 268         u32 pidr;       /* partition ID, DECO */
 269 };
 270
 271 /* RNGB test mode (replicated twice in some configurations) */
 272 /* Padded out to 0x100 */
 273 struct rngtst {
 274         u32 mode;               /* RTSTMODEx - Test mode */
 275         u32 rsvd1[3];
 276         u32 reset;              /* RTSTRESETx - Test reset control */
 277         u32 rsvd2[3];
 278         u32 status;             /* RTSTSSTATUSx - Test status */
 279         u32 rsvd3;
 280         u32 errstat;            /* RTSTERRSTATx - Test error status */
 281         u32 rsvd4;
 282         u32 errctl;             /* RTSTERRCTLx - Test error control */
 283         u32 rsvd5;
 284         u32 entropy;            /* RTSTENTROPYx - Test entropy */
 285         u32 rsvd6[15];
 286         u32 verifctl;   /* RTSTVERIFCTLx - Test verification control */
 287         u32 rsvd7;
 288         u32 verifstat;  /* RTSTVERIFSTATx - Test verification status */
 289         u32 rsvd8;
 290         u32 verifdata;  /* RTSTVERIFDx - Test verification data */
 291         u32 rsvd9;
 292         u32 xkey;               /* RTSTXKEYx - Test XKEY */
 293         u32 rsvd10;
 294         u32 oscctctl;   /* RTSTOSCCTCTLx - Test osc. counter control */
 295         u32 rsvd11;
 296         u32 oscct;              /* RTSTOSCCTx - Test oscillator counter */
 297         u32 rsvd12;
 298         u32 oscctstat;  /* RTSTODCCTSTATx - Test osc counter status */
 299         u32 rsvd13[2];
 300         u32 ofifo[4];   /* RTSTOFIFOx - Test output FIFO */
 301         u32 rsvd14[15];
 302 };
 303
 304 /* RNG4 TRNG test registers */
 305 struct rng4tst {
 306 #define RTMCTL_PRGM     0x00010000      /* 1 -> program mode, 0 -> run mode */
 307 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC      0 /* use von Neumann data in
 308                                                      both entropy shifter and
 309                                                      statistical checker */
 310 #define RTMCTL_SAMP_MODE_RAW_ES_SC              1 /* use raw data in both
 311                                                      entropy shifter and
 312                                                      statistical checker */
 313 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC  2 /* use von Neumann data in
 314                                                      entropy shifter, raw data
 315                                                      in statistical checker */
 316 #define RTMCTL_SAMP_MODE_INVALID                3 /* invalid combination */
 317         u32 rtmctl;             /* misc. control register */
 318         u32 rtscmisc;           /* statistical check misc. register */
 319         u32 rtpkrrng;           /* poker range register */
 320         union {
 321                 u32 rtpkrmax;   /* PRGM=1: poker max. limit register */
 322                 u32 rtpkrsq;    /* PRGM=0: poker square calc. result register */
 323         };
 324 #define RTSDCTL_ENT_DLY_SHIFT 16
 325 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
 326 #define RTSDCTL_ENT_DLY_MIN 3200
 327 #define RTSDCTL_ENT_DLY_MAX 12800
 328         u32 rtsdctl;            /* seed control register */
 329         union {
 330                 u32 rtsblim;    /* PRGM=1: sparse bit limit register */
 331                 u32 rttotsam;   /* PRGM=0: total samples register */
 332         };
 333         u32 rtfrqmin;           /* frequency count min. limit register */
 334 #define RTFRQMAX_DISABLE        (1 << 20)
 335         union {
 336                 u32 rtfrqmax;   /* PRGM=1: freq. count max. limit register */
 337                 u32 rtfrqcnt;   /* PRGM=0: freq. count register */
 338         };
 339         u32 rsvd1[40];
 340 #define RDSTA_SKVT 0x80000000
 341 #define RDSTA_SKVN 0x40000000
 342 #define RDSTA_IF0 0x00000001
 343 #define RDSTA_IF1 0x00000002
 344 #define RDSTA_IFMASK (RDSTA_IF1 | RDSTA_IF0)
 345         u32 rdsta;
 346         u32 rsvd2[15];
 347 };
 348
 349 /*
 350  * caam_ctrl - basic core configuration
 351  * starts base + 0x0000 padded out to 0x1000
 352  */
 353
 354 #define KEK_KEY_SIZE            8
 355 #define TKEK_KEY_SIZE           8
 356 #define TDSK_KEY_SIZE           8
 357
 358 #define DECO_RESET      1       /* Use with DECO reset/availability regs */
 359 #define DECO_RESET_0    (DECO_RESET << 0)
 360 #define DECO_RESET_1    (DECO_RESET << 1)
 361 #define DECO_RESET_2    (DECO_RESET << 2)
 362 #define DECO_RESET_3    (DECO_RESET << 3)
 363 #define DECO_RESET_4    (DECO_RESET << 4)
 364
 365 struct caam_ctrl {
 366         /* Basic Configuration Section                          000-01f */
 367         /* Read/Writable                                                */
 368         u32 rsvd1;
 369         u32 mcr;                /* MCFG      Master Config Register  */
 370         u32 rsvd2;
 371         u32 scfgr;              /* SCFGR, Security Config Register */
 372
 373         /* Bus Access Configuration Section                     010-11f */
 374         /* Read/Writable                                                */
 375         struct masterid jr_mid[4];      /* JRxLIODNR - JobR LIODN setup */
 376         u32 rsvd3[11];
 377         u32 jrstart;                    /* JRSTART - Job Ring Start Register */
 378         struct masterid rtic_mid[4];    /* RTICxLIODNR - RTIC LIODN setup */
 379         u32 rsvd4[5];
 380         u32 deco_rsr;                   /* DECORSR - Deco Request Source */
 381         u32 rsvd11;
 382         u32 deco_rq;                    /* DECORR - DECO Request */
 383         struct partid deco_mid[5];      /* DECOxLIODNR - 1 per DECO */
 384         u32 rsvd5[22];
 385
 386         /* DECO Availability/Reset Section                      120-3ff */
 387         u32 deco_avail;         /* DAR - DECO availability */
 388         u32 deco_reset;         /* DRR - DECO reset */
 389         u32 rsvd6[182];
 390
 391         /* Key Encryption/Decryption Configuration              400-5ff */
 392         /* Read/Writable only while in Non-secure mode                  */
 393         u32 kek[KEK_KEY_SIZE];  /* JDKEKR - Key Encryption Key */
 394         u32 tkek[TKEK_KEY_SIZE];        /* TDKEKR - Trusted Desc KEK */
 395         u32 tdsk[TDSK_KEY_SIZE];        /* TDSKR - Trusted Desc Signing Key */
 396         u32 rsvd7[32];
 397         u64 sknonce;                    /* SKNR - Secure Key Nonce */
 398         u32 rsvd8[70];
 399
 400         /* RNG Test/Verification/Debug Access                   600-7ff */
 401         /* (Useful in Test/Debug modes only...)                         */
 402         union {
 403                 struct rngtst rtst[2];
 404                 struct rng4tst r4tst[2];
 405         };
 406
 407         u32 rsvd9[448];
 408
 409         /* Performance Monitor                                  f00-fff */
 410         struct caam_perfmon perfmon;
 411 };
 412
 413 /*
 414  * Controller master config register defs
 415  */
 416 #define MCFGR_SWRESET           0x80000000 /* software reset */
 417 #define MCFGR_WDENABLE          0x40000000 /* DECO watchdog enable */
 418 #define MCFGR_WDFAIL            0x20000000 /* DECO watchdog force-fail */
 419 #define MCFGR_DMA_RESET         0x10000000
 420 #define MCFGR_LONG_PTR          0x00010000 /* Use >32-bit desc addressing */
 421 #define SCFGR_RDBENABLE         0x00000400
 422 #define SCFGR_VIRT_EN           0x00008000
 423 #define DECORR_RQD0ENABLE       0x00000001 /* Enable DECO0 for direct access */
 424 #define DECORSR_JR0             0x00000001 /* JR to supply TZ, SDID, ICID */
 425 #define DECORSR_VALID           0x80000000
 426 #define DECORR_DEN0             0x00010000 /* DECO0 available for access*/
 427
 428 /* AXI read cache control */
 429 #define MCFGR_ARCACHE_SHIFT     12
 430 #define MCFGR_ARCACHE_MASK      (0xf << MCFGR_ARCACHE_SHIFT)
 431 #define MCFGR_ARCACHE_BUFF      (0x1 << MCFGR_ARCACHE_SHIFT)
 432 #define MCFGR_ARCACHE_CACH      (0x2 << MCFGR_ARCACHE_SHIFT)
 433 #define MCFGR_ARCACHE_RALL      (0x4 << MCFGR_ARCACHE_SHIFT)
 434
 435 /* AXI write cache control */
 436 #define MCFGR_AWCACHE_SHIFT     8
 437 #define MCFGR_AWCACHE_MASK      (0xf << MCFGR_AWCACHE_SHIFT)
 438 #define MCFGR_AWCACHE_BUFF      (0x1 << MCFGR_AWCACHE_SHIFT)
 439 #define MCFGR_AWCACHE_CACH      (0x2 << MCFGR_AWCACHE_SHIFT)
 440 #define MCFGR_AWCACHE_WALL      (0x8 << MCFGR_AWCACHE_SHIFT)
 441
 442 /* AXI pipeline depth */
 443 #define MCFGR_AXIPIPE_SHIFT     4
 444 #define MCFGR_AXIPIPE_MASK      (0xf << MCFGR_AXIPIPE_SHIFT)
 445
 446 #define MCFGR_AXIPRI            0x00000008 /* Assert AXI priority sideband */
 447 #define MCFGR_BURST_64          0x00000001 /* Max burst size */
 448
 449 /* JRSTART register offsets */
 450 #define JRSTART_JR0_START       0x00000001 /* Start Job ring 0 */
 451 #define JRSTART_JR1_START       0x00000002 /* Start Job ring 1 */
 452 #define JRSTART_JR2_START       0x00000004 /* Start Job ring 2 */
 453 #define JRSTART_JR3_START       0x00000008 /* Start Job ring 3 */
 454
 455 /*
 456  * caam_job_ring - direct job ring setup
 457  * 1-4 possible per instantiation, base + 1000/2000/3000/4000
 458  * Padded out to 0x1000
 459  */
 460 struct caam_job_ring {
 461         /* Input ring */
 462         u64 inpring_base;       /* IRBAx -  Input desc ring baseaddr */
 463         u32 rsvd1;
 464         u32 inpring_size;       /* IRSx - Input ring size */
 465         u32 rsvd2;
 466         u32 inpring_avail;      /* IRSAx - Input ring room remaining */
 467         u32 rsvd3;
 468         u32 inpring_jobadd;     /* IRJAx - Input ring jobs added */
 469
 470         /* Output Ring */
 471         u64 outring_base;       /* ORBAx - Output status ring base addr */
 472         u32 rsvd4;
 473         u32 outring_size;       /* ORSx - Output ring size */
 474         u32 rsvd5;
 475         u32 outring_rmvd;       /* ORJRx - Output ring jobs removed */
 476         u32 rsvd6;
 477         u32 outring_used;       /* ORSFx - Output ring slots full */
 478
 479         /* Status/Configuration */
 480         u32 rsvd7;
 481         u32 jroutstatus;        /* JRSTAx - JobR output status */
 482         u32 rsvd8;
 483         u32 jrintstatus;        /* JRINTx - JobR interrupt status */
 484         u32 rconfig_hi; /* JRxCFG - Ring configuration */
 485         u32 rconfig_lo;
 486
 487         /* Indices. CAAM maintains as "heads" of each queue */
 488         u32 rsvd9;
 489         u32 inp_rdidx;  /* IRRIx - Input ring read index */
 490         u32 rsvd10;
 491         u32 out_wtidx;  /* ORWIx - Output ring write index */
 492
 493         /* Command/control */
 494         u32 rsvd11;
 495         u32 jrcommand;  /* JRCRx - JobR command */
 496
 497         u32 rsvd12[932];
 498
 499         /* Performance Monitor                                  f00-fff */
 500         struct caam_perfmon perfmon;
 501 };
 502
 503 #define JR_RINGSIZE_MASK        0x03ff
 504 /*
 505  * jrstatus - Job Ring Output Status
 506  * All values in lo word
 507  * Also note, same values written out as status through QI
 508  * in the command/status field of a frame descriptor
 509  */
 510 #define JRSTA_SSRC_SHIFT            28
 511 #define JRSTA_SSRC_MASK             0xf0000000
 512
 513 #define JRSTA_SSRC_NONE             0x00000000
 514 #define JRSTA_SSRC_CCB_ERROR        0x20000000
 515 #define JRSTA_SSRC_JUMP_HALT_USER   0x30000000
 516 #define JRSTA_SSRC_DECO             0x40000000
 517 #define JRSTA_SSRC_JRERROR          0x60000000
 518 #define JRSTA_SSRC_JUMP_HALT_CC     0x70000000
 519
 520 #define JRSTA_DECOERR_JUMP          0x08000000
 521 #define JRSTA_DECOERR_INDEX_SHIFT   8
 522 #define JRSTA_DECOERR_INDEX_MASK    0xff00
 523 #define JRSTA_DECOERR_ERROR_MASK    0x00ff
 524
 525 #define JRSTA_DECOERR_NONE          0x00
 526 #define JRSTA_DECOERR_LINKLEN       0x01
 527 #define JRSTA_DECOERR_LINKPTR       0x02
 528 #define JRSTA_DECOERR_JRCTRL        0x03
 529 #define JRSTA_DECOERR_DESCCMD       0x04
 530 #define JRSTA_DECOERR_ORDER         0x05
 531 #define JRSTA_DECOERR_KEYCMD        0x06
 532 #define JRSTA_DECOERR_LOADCMD       0x07
 533 #define JRSTA_DECOERR_STORECMD      0x08
 534 #define JRSTA_DECOERR_OPCMD         0x09
 535 #define JRSTA_DECOERR_FIFOLDCMD     0x0a
 536 #define JRSTA_DECOERR_FIFOSTCMD     0x0b
 537 #define JRSTA_DECOERR_MOVECMD       0x0c
 538 #define JRSTA_DECOERR_JUMPCMD       0x0d
 539 #define JRSTA_DECOERR_MATHCMD       0x0e
 540 #define JRSTA_DECOERR_SHASHCMD      0x0f
 541 #define JRSTA_DECOERR_SEQCMD        0x10
 542 #define JRSTA_DECOERR_DECOINTERNAL  0x11
 543 #define JRSTA_DECOERR_SHDESCHDR     0x12
 544 #define JRSTA_DECOERR_HDRLEN        0x13
 545 #define JRSTA_DECOERR_BURSTER       0x14
 546 #define JRSTA_DECOERR_DESCSIGNATURE 0x15
 547 #define JRSTA_DECOERR_DMA           0x16
 548 #define JRSTA_DECOERR_BURSTFIFO     0x17
 549 #define JRSTA_DECOERR_JRRESET       0x1a
 550 #define JRSTA_DECOERR_JOBFAIL       0x1b
 551 #define JRSTA_DECOERR_DNRERR        0x80
 552 #define JRSTA_DECOERR_UNDEFPCL      0x81
 553 #define JRSTA_DECOERR_PDBERR        0x82
 554 #define JRSTA_DECOERR_ANRPLY_LATE   0x83
 555 #define JRSTA_DECOERR_ANRPLY_REPLAY 0x84
 556 #define JRSTA_DECOERR_SEQOVF        0x85
 557 #define JRSTA_DECOERR_INVSIGN       0x86
 558 #define JRSTA_DECOERR_DSASIGN       0x87
 559
 560 #define JRSTA_CCBERR_JUMP           0x08000000
 561 #define JRSTA_CCBERR_INDEX_MASK     0xff00
 562 #define JRSTA_CCBERR_INDEX_SHIFT    8
 563 #define JRSTA_CCBERR_CHAID_MASK     0x00f0
 564 #define JRSTA_CCBERR_CHAID_SHIFT    4
 565 #define JRSTA_CCBERR_ERRID_MASK     0x000f
 566
 567 #define JRSTA_CCBERR_CHAID_AES      (0x01 << JRSTA_CCBERR_CHAID_SHIFT)
 568 #define JRSTA_CCBERR_CHAID_DES      (0x02 << JRSTA_CCBERR_CHAID_SHIFT)
 569 #define JRSTA_CCBERR_CHAID_ARC4     (0x03 << JRSTA_CCBERR_CHAID_SHIFT)
 570 #define JRSTA_CCBERR_CHAID_MD       (0x04 << JRSTA_CCBERR_CHAID_SHIFT)
 571 #define JRSTA_CCBERR_CHAID_RNG      (0x05 << JRSTA_CCBERR_CHAID_SHIFT)
 572 #define JRSTA_CCBERR_CHAID_SNOW     (0x06 << JRSTA_CCBERR_CHAID_SHIFT)
 573 #define JRSTA_CCBERR_CHAID_KASUMI   (0x07 << JRSTA_CCBERR_CHAID_SHIFT)
 574 #define JRSTA_CCBERR_CHAID_PK       (0x08 << JRSTA_CCBERR_CHAID_SHIFT)
 575 #define JRSTA_CCBERR_CHAID_CRC      (0x09 << JRSTA_CCBERR_CHAID_SHIFT)
 576
 577 #define JRSTA_CCBERR_ERRID_NONE     0x00
 578 #define JRSTA_CCBERR_ERRID_MODE     0x01
 579 #define JRSTA_CCBERR_ERRID_DATASIZ  0x02
 580 #define JRSTA_CCBERR_ERRID_KEYSIZ   0x03
 581 #define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04
 582 #define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05
 583 #define JRSTA_CCBERR_ERRID_SEQUENCE 0x06
 584 #define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07
 585 #define JRSTA_CCBERR_ERRID_PKMODEVN 0x08
 586 #define JRSTA_CCBERR_ERRID_KEYPARIT 0x09
 587 #define JRSTA_CCBERR_ERRID_ICVCHK   0x0a
 588 #define JRSTA_CCBERR_ERRID_HARDWARE 0x0b
 589 #define JRSTA_CCBERR_ERRID_CCMAAD   0x0c
 590 #define JRSTA_CCBERR_ERRID_INVCHA   0x0f
 591
 592 #define JRINT_ERR_INDEX_MASK        0x3fff0000
 593 #define JRINT_ERR_INDEX_SHIFT       16
 594 #define JRINT_ERR_TYPE_MASK         0xf00
 595 #define JRINT_ERR_TYPE_SHIFT        8
 596 #define JRINT_ERR_HALT_MASK         0xc
 597 #define JRINT_ERR_HALT_SHIFT        2
 598 #define JRINT_ERR_HALT_INPROGRESS   0x4
 599 #define JRINT_ERR_HALT_COMPLETE     0x8
 600 #define JRINT_JR_ERROR              0x02
 601 #define JRINT_JR_INT                0x01
 602
 603 #define JRINT_ERR_TYPE_WRITE        1
 604 #define JRINT_ERR_TYPE_BAD_INPADDR  3
 605 #define JRINT_ERR_TYPE_BAD_OUTADDR  4
 606 #define JRINT_ERR_TYPE_INV_INPWRT   5
 607 #define JRINT_ERR_TYPE_INV_OUTWRT   6
 608 #define JRINT_ERR_TYPE_RESET        7
 609 #define JRINT_ERR_TYPE_REMOVE_OFL   8
 610 #define JRINT_ERR_TYPE_ADD_OFL      9
 611
 612 #define JRCFG_SOE               0x04
 613 #define JRCFG_ICEN              0x02
 614 #define JRCFG_IMSK              0x01
 615 #define JRCFG_ICDCT_SHIFT       8
 616 #define JRCFG_ICTT_SHIFT        16
 617
 618 #define JRCR_RESET                  0x01
 619
 620 /*
 621  * caam_assurance - Assurance Controller View
 622  * base + 0x6000 padded out to 0x1000
 623  */
 624
 625 struct rtic_element {
 626         u64 address;
 627         u32 rsvd;
 628         u32 length;
 629 };
 630
 631 struct rtic_block {
 632         struct rtic_element element[2];
 633 };
 634
 635 struct rtic_memhash {
 636         u32 memhash_be[32];
 637         u32 memhash_le[32];
 638 };
 639
 640 struct caam_assurance {
 641     /* Status/Command/Watchdog */
 642         u32 rsvd1;
 643         u32 status;             /* RSTA - Status */
 644         u32 rsvd2;
 645         u32 cmd;                /* RCMD - Command */
 646         u32 rsvd3;
 647         u32 ctrl;               /* RCTL - Control */
 648         u32 rsvd4;
 649         u32 throttle;   /* RTHR - Throttle */
 650         u32 rsvd5[2];
 651         u64 watchdog;   /* RWDOG - Watchdog Timer */
 652         u32 rsvd6;
 653         u32 rend;               /* REND - Endian corrections */
 654         u32 rsvd7[50];
 655
 656         /* Block access/configuration @ 100/110/120/130 */
 657         struct rtic_block memblk[4];    /* Memory Blocks A-D */
 658         u32 rsvd8[32];
 659
 660         /* Block hashes @ 200/300/400/500 */
 661         struct rtic_memhash hash[4];    /* Block hash values A-D */
 662         u32 rsvd_3[640];
 663 };
 664
 665 /*
 666  * caam_queue_if - QI configuration and control
 667  * starts base + 0x7000, padded out to 0x1000 long
 668  */
 669
 670 struct caam_queue_if {
 671         u32 qi_control_hi;      /* QICTL  - QI Control */
 672         u32 qi_control_lo;
 673         u32 rsvd1;
 674         u32 qi_status;  /* QISTA  - QI Status */
 675         u32 qi_deq_cfg_hi;      /* QIDQC  - QI Dequeue Configuration */
 676         u32 qi_deq_cfg_lo;
 677         u32 qi_enq_cfg_hi;      /* QISEQC - QI Enqueue Command     */
 678         u32 qi_enq_cfg_lo;
 679         u32 rsvd2[1016];
 680 };
 681
 682 /* QI control bits - low word */
 683 #define QICTL_DQEN      0x01              /* Enable frame pop          */
 684 #define QICTL_STOP      0x02              /* Stop dequeue/enqueue      */
 685 #define QICTL_SOE       0x04              /* Stop on error             */
 686
 687 /* QI control bits - high word */
 688 #define QICTL_MBSI      0x01
 689 #define QICTL_MHWSI     0x02
 690 #define QICTL_MWSI      0x04
 691 #define QICTL_MDWSI     0x08
 692 #define QICTL_CBSI      0x10            /* CtrlDataByteSwapInput     */
 693 #define QICTL_CHWSI     0x20            /* CtrlDataHalfSwapInput     */
 694 #define QICTL_CWSI      0x40            /* CtrlDataWordSwapInput     */
 695 #define QICTL_CDWSI     0x80            /* CtrlDataDWordSwapInput    */
 696 #define QICTL_MBSO      0x0100
 697 #define QICTL_MHWSO     0x0200
 698 #define QICTL_MWSO      0x0400
 699 #define QICTL_MDWSO     0x0800
 700 #define QICTL_CBSO      0x1000          /* CtrlDataByteSwapOutput    */
 701 #define QICTL_CHWSO     0x2000          /* CtrlDataHalfSwapOutput    */
 702 #define QICTL_CWSO      0x4000          /* CtrlDataWordSwapOutput    */
 703 #define QICTL_CDWSO     0x8000          /* CtrlDataDWordSwapOutput   */
 704 #define QICTL_DMBS      0x010000
 705 #define QICTL_EPO       0x020000
 706
 707 /* QI status bits */
 708 #define QISTA_PHRDERR   0x01              /* PreHeader Read Error      */
 709 #define QISTA_CFRDERR   0x02              /* Compound Frame Read Error */
 710 #define QISTA_OFWRERR   0x04              /* Output Frame Read Error   */
 711 #define QISTA_BPDERR    0x08              /* Buffer Pool Depleted      */
 712 #define QISTA_BTSERR    0x10              /* Buffer Undersize          */
 713 #define QISTA_CFWRERR   0x20              /* Compound Frame Write Err  */
 714 #define QISTA_STOPD     0x80000000        /* QI Stopped (see QICTL)    */
 715
 716 /* deco_sg_table - DECO view of scatter/gather table */
 717 struct deco_sg_table {
 718         u64 addr;               /* Segment Address */
 719         u32 elen;               /* E, F bits + 30-bit length */
 720         u32 bpid_offset;        /* Buffer Pool ID + 16-bit length */
 721 };
 722
 723 /*
 724  * caam_deco - descriptor controller - CHA cluster block
 725  *
 726  * Only accessible when direct DECO access is turned on
 727  * (done in DECORR, via MID programmed in DECOxMID
 728  *
 729  * 5 typical, base + 0x8000/9000/a000/b000
 730  * Padded out to 0x1000 long
 731  */
 732 struct caam_deco {
 733         u32 rsvd1;
 734         u32 cls1_mode;  /* CxC1MR -  Class 1 Mode */
 735         u32 rsvd2;
 736         u32 cls1_keysize;       /* CxC1KSR - Class 1 Key Size */
 737         u32 cls1_datasize_hi;   /* CxC1DSR - Class 1 Data Size */
 738         u32 cls1_datasize_lo;
 739         u32 rsvd3;
 740         u32 cls1_icvsize;       /* CxC1ICVSR - Class 1 ICV size */
 741         u32 rsvd4[5];
 742         u32 cha_ctrl;   /* CCTLR - CHA control */
 743         u32 rsvd5;
 744         u32 irq_crtl;   /* CxCIRQ - CCB interrupt done/error/clear */
 745         u32 rsvd6;
 746         u32 clr_written;        /* CxCWR - Clear-Written */
 747         u32 ccb_status_hi;      /* CxCSTA - CCB Status/Error */
 748         u32 ccb_status_lo;
 749         u32 rsvd7[3];
 750         u32 aad_size;   /* CxAADSZR - Current AAD Size */
 751         u32 rsvd8;
 752         u32 cls1_iv_size;       /* CxC1IVSZR - Current Class 1 IV Size */
 753         u32 rsvd9[7];
 754         u32 pkha_a_size;        /* PKASZRx - Size of PKHA A */
 755         u32 rsvd10;
 756         u32 pkha_b_size;        /* PKBSZRx - Size of PKHA B */
 757         u32 rsvd11;
 758         u32 pkha_n_size;        /* PKNSZRx - Size of PKHA N */
 759         u32 rsvd12;
 760         u32 pkha_e_size;        /* PKESZRx - Size of PKHA E */
 761         u32 rsvd13[24];
 762         u32 cls1_ctx[16];       /* CxC1CTXR - Class 1 Context @100 */
 763         u32 rsvd14[48];
 764         u32 cls1_key[8];        /* CxC1KEYR - Class 1 Key @200 */
 765         u32 rsvd15[121];
 766         u32 cls2_mode;  /* CxC2MR - Class 2 Mode */
 767         u32 rsvd16;
 768         u32 cls2_keysize;       /* CxX2KSR - Class 2 Key Size */
 769         u32 cls2_datasize_hi;   /* CxC2DSR - Class 2 Data Size */
 770         u32 cls2_datasize_lo;
 771         u32 rsvd17;
 772         u32 cls2_icvsize;       /* CxC2ICVSZR - Class 2 ICV Size */
 773         u32 rsvd18[56];
 774         u32 cls2_ctx[18];       /* CxC2CTXR - Class 2 Context @500 */
 775         u32 rsvd19[46];
 776         u32 cls2_key[32];       /* CxC2KEYR - Class2 Key @600 */
 777         u32 rsvd20[84];
 778         u32 inp_infofifo_hi;    /* CxIFIFO - Input Info FIFO @7d0 */
 779         u32 inp_infofifo_lo;
 780         u32 rsvd21[2];
 781         u64 inp_datafifo;       /* CxDFIFO - Input Data FIFO */
 782         u32 rsvd22[2];
 783         u64 out_datafifo;       /* CxOFIFO - Output Data FIFO */
 784         u32 rsvd23[2];
 785         u32 jr_ctl_hi;  /* CxJRR - JobR Control Register      @800 */
 786         u32 jr_ctl_lo;
 787         u64 jr_descaddr;        /* CxDADR - JobR Descriptor Address */
 788 #define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF
 789         u32 op_status_hi;       /* DxOPSTA - DECO Operation Status */
 790         u32 op_status_lo;
 791         u32 rsvd24[2];
 792         u32 liodn;              /* DxLSR - DECO LIODN Status - non-seq */
 793         u32 td_liodn;   /* DxLSR - DECO LIODN Status - trustdesc */
 794         u32 rsvd26[6];
 795         u64 math[4];            /* DxMTH - Math register */
 796         u32 rsvd27[8];
 797         struct deco_sg_table gthr_tbl[4];       /* DxGTR - Gather Tables */
 798         u32 rsvd28[16];
 799         struct deco_sg_table sctr_tbl[4];       /* DxSTR - Scatter Tables */
 800         u32 rsvd29[48];
 801         u32 descbuf[64];        /* DxDESB - Descriptor buffer */
 802         u32 rscvd30[193];
 803 #define DESC_DBG_DECO_STAT_HOST_ERR     0x00D00000
 804 #define DESC_DBG_DECO_STAT_VALID        0x80000000
 805 #define DESC_DBG_DECO_STAT_MASK         0x00F00000
 806         u32 desc_dbg;           /* DxDDR - DECO Debug Register */
 807         u32 rsvd31[126];
 808 };
 809
 810 #define DECO_JQCR_WHL           0x20000000
 811 #define DECO_JQCR_FOUR          0x10000000
 812
 813 #define JR_BLOCK_NUMBER         1
 814 #define ASSURE_BLOCK_NUMBER     6
 815 #define QI_BLOCK_NUMBER         7
 816 #define DECO_BLOCK_NUMBER       8
 817 #define PG_SIZE_4K              0x1000
 818 #define PG_SIZE_64K             0x10000
 819 #endif /* REGS_H */