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[deliverable/linux.git] / drivers / crypto / ixp4xx_crypto.c
1 /*
2 * Intel IXP4xx NPE-C crypto driver
3 *
4 * Copyright (C) 2008 Christian Hohnstaedt <chohnstaedt@innominate.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
9 *
10 */
11
12 #include <linux/platform_device.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/dmapool.h>
15 #include <linux/crypto.h>
16 #include <linux/kernel.h>
17 #include <linux/rtnetlink.h>
18 #include <linux/interrupt.h>
19 #include <linux/spinlock.h>
20 #include <linux/gfp.h>
21 #include <linux/module.h>
22
23 #include <crypto/ctr.h>
24 #include <crypto/des.h>
25 #include <crypto/aes.h>
26 #include <crypto/sha.h>
27 #include <crypto/algapi.h>
28 #include <crypto/internal/aead.h>
29 #include <crypto/authenc.h>
30 #include <crypto/scatterwalk.h>
31
32 #include <mach/npe.h>
33 #include <mach/qmgr.h>
34
35 #define MAX_KEYLEN 32
36
37 /* hash: cfgword + 2 * digestlen; crypt: keylen + cfgword */
38 #define NPE_CTX_LEN 80
39 #define AES_BLOCK128 16
40
41 #define NPE_OP_HASH_VERIFY 0x01
42 #define NPE_OP_CCM_ENABLE 0x04
43 #define NPE_OP_CRYPT_ENABLE 0x08
44 #define NPE_OP_HASH_ENABLE 0x10
45 #define NPE_OP_NOT_IN_PLACE 0x20
46 #define NPE_OP_HMAC_DISABLE 0x40
47 #define NPE_OP_CRYPT_ENCRYPT 0x80
48
49 #define NPE_OP_CCM_GEN_MIC 0xcc
50 #define NPE_OP_HASH_GEN_ICV 0x50
51 #define NPE_OP_ENC_GEN_KEY 0xc9
52
53 #define MOD_ECB 0x0000
54 #define MOD_CTR 0x1000
55 #define MOD_CBC_ENC 0x2000
56 #define MOD_CBC_DEC 0x3000
57 #define MOD_CCM_ENC 0x4000
58 #define MOD_CCM_DEC 0x5000
59
60 #define KEYLEN_128 4
61 #define KEYLEN_192 6
62 #define KEYLEN_256 8
63
64 #define CIPH_DECR 0x0000
65 #define CIPH_ENCR 0x0400
66
67 #define MOD_DES 0x0000
68 #define MOD_TDEA2 0x0100
69 #define MOD_3DES 0x0200
70 #define MOD_AES 0x0800
71 #define MOD_AES128 (0x0800 | KEYLEN_128)
72 #define MOD_AES192 (0x0900 | KEYLEN_192)
73 #define MOD_AES256 (0x0a00 | KEYLEN_256)
74
75 #define MAX_IVLEN 16
76 #define NPE_ID 2 /* NPE C */
77 #define NPE_QLEN 16
78 /* Space for registering when the first
79 * NPE_QLEN crypt_ctl are busy */
80 #define NPE_QLEN_TOTAL 64
81
82 #define SEND_QID 29
83 #define RECV_QID 30
84
85 #define CTL_FLAG_UNUSED 0x0000
86 #define CTL_FLAG_USED 0x1000
87 #define CTL_FLAG_PERFORM_ABLK 0x0001
88 #define CTL_FLAG_GEN_ICV 0x0002
89 #define CTL_FLAG_GEN_REVAES 0x0004
90 #define CTL_FLAG_PERFORM_AEAD 0x0008
91 #define CTL_FLAG_MASK 0x000f
92
93 #define HMAC_IPAD_VALUE 0x36
94 #define HMAC_OPAD_VALUE 0x5C
95 #define HMAC_PAD_BLOCKLEN SHA1_BLOCK_SIZE
96
97 #define MD5_DIGEST_SIZE 16
98
99 struct buffer_desc {
100 u32 phys_next;
101 #ifdef __ARMEB__
102 u16 buf_len;
103 u16 pkt_len;
104 #else
105 u16 pkt_len;
106 u16 buf_len;
107 #endif
108 u32 phys_addr;
109 u32 __reserved[4];
110 struct buffer_desc *next;
111 enum dma_data_direction dir;
112 };
113
114 struct crypt_ctl {
115 #ifdef __ARMEB__
116 u8 mode; /* NPE_OP_* operation mode */
117 u8 init_len;
118 u16 reserved;
119 #else
120 u16 reserved;
121 u8 init_len;
122 u8 mode; /* NPE_OP_* operation mode */
123 #endif
124 u8 iv[MAX_IVLEN]; /* IV for CBC mode or CTR IV for CTR mode */
125 u32 icv_rev_aes; /* icv or rev aes */
126 u32 src_buf;
127 u32 dst_buf;
128 #ifdef __ARMEB__
129 u16 auth_offs; /* Authentication start offset */
130 u16 auth_len; /* Authentication data length */
131 u16 crypt_offs; /* Cryption start offset */
132 u16 crypt_len; /* Cryption data length */
133 #else
134 u16 auth_len; /* Authentication data length */
135 u16 auth_offs; /* Authentication start offset */
136 u16 crypt_len; /* Cryption data length */
137 u16 crypt_offs; /* Cryption start offset */
138 #endif
139 u32 aadAddr; /* Additional Auth Data Addr for CCM mode */
140 u32 crypto_ctx; /* NPE Crypto Param structure address */
141
142 /* Used by Host: 4*4 bytes*/
143 unsigned ctl_flags;
144 union {
145 struct ablkcipher_request *ablk_req;
146 struct aead_request *aead_req;
147 struct crypto_tfm *tfm;
148 } data;
149 struct buffer_desc *regist_buf;
150 u8 *regist_ptr;
151 };
152
153 struct ablk_ctx {
154 struct buffer_desc *src;
155 struct buffer_desc *dst;
156 };
157
158 struct aead_ctx {
159 struct buffer_desc *buffer;
160 struct scatterlist ivlist;
161 /* used when the hmac is not on one sg entry */
162 u8 *hmac_virt;
163 int encrypt;
164 };
165
166 struct ix_hash_algo {
167 u32 cfgword;
168 unsigned char *icv;
169 };
170
171 struct ix_sa_dir {
172 unsigned char *npe_ctx;
173 dma_addr_t npe_ctx_phys;
174 int npe_ctx_idx;
175 u8 npe_mode;
176 };
177
178 struct ixp_ctx {
179 struct ix_sa_dir encrypt;
180 struct ix_sa_dir decrypt;
181 int authkey_len;
182 u8 authkey[MAX_KEYLEN];
183 int enckey_len;
184 u8 enckey[MAX_KEYLEN];
185 u8 salt[MAX_IVLEN];
186 u8 nonce[CTR_RFC3686_NONCE_SIZE];
187 unsigned salted;
188 atomic_t configuring;
189 struct completion completion;
190 };
191
192 struct ixp_alg {
193 struct crypto_alg crypto;
194 const struct ix_hash_algo *hash;
195 u32 cfg_enc;
196 u32 cfg_dec;
197
198 int registered;
199 };
200
201 static const struct ix_hash_algo hash_alg_md5 = {
202 .cfgword = 0xAA010004,
203 .icv = "\x01\x23\x45\x67\x89\xAB\xCD\xEF"
204 "\xFE\xDC\xBA\x98\x76\x54\x32\x10",
205 };
206 static const struct ix_hash_algo hash_alg_sha1 = {
207 .cfgword = 0x00000005,
208 .icv = "\x67\x45\x23\x01\xEF\xCD\xAB\x89\x98\xBA"
209 "\xDC\xFE\x10\x32\x54\x76\xC3\xD2\xE1\xF0",
210 };
211
212 static struct npe *npe_c;
213 static struct dma_pool *buffer_pool = NULL;
214 static struct dma_pool *ctx_pool = NULL;
215
216 static struct crypt_ctl *crypt_virt = NULL;
217 static dma_addr_t crypt_phys;
218
219 static int support_aes = 1;
220
221 #define DRIVER_NAME "ixp4xx_crypto"
222
223 static struct platform_device *pdev;
224
225 static inline dma_addr_t crypt_virt2phys(struct crypt_ctl *virt)
226 {
227 return crypt_phys + (virt - crypt_virt) * sizeof(struct crypt_ctl);
228 }
229
230 static inline struct crypt_ctl *crypt_phys2virt(dma_addr_t phys)
231 {
232 return crypt_virt + (phys - crypt_phys) / sizeof(struct crypt_ctl);
233 }
234
235 static inline u32 cipher_cfg_enc(struct crypto_tfm *tfm)
236 {
237 return container_of(tfm->__crt_alg, struct ixp_alg,crypto)->cfg_enc;
238 }
239
240 static inline u32 cipher_cfg_dec(struct crypto_tfm *tfm)
241 {
242 return container_of(tfm->__crt_alg, struct ixp_alg,crypto)->cfg_dec;
243 }
244
245 static inline const struct ix_hash_algo *ix_hash(struct crypto_tfm *tfm)
246 {
247 return container_of(tfm->__crt_alg, struct ixp_alg, crypto)->hash;
248 }
249
250 static int setup_crypt_desc(void)
251 {
252 struct device *dev = &pdev->dev;
253 BUILD_BUG_ON(sizeof(struct crypt_ctl) != 64);
254 crypt_virt = dma_alloc_coherent(dev,
255 NPE_QLEN * sizeof(struct crypt_ctl),
256 &crypt_phys, GFP_ATOMIC);
257 if (!crypt_virt)
258 return -ENOMEM;
259 memset(crypt_virt, 0, NPE_QLEN * sizeof(struct crypt_ctl));
260 return 0;
261 }
262
263 static spinlock_t desc_lock;
264 static struct crypt_ctl *get_crypt_desc(void)
265 {
266 int i;
267 static int idx = 0;
268 unsigned long flags;
269
270 spin_lock_irqsave(&desc_lock, flags);
271
272 if (unlikely(!crypt_virt))
273 setup_crypt_desc();
274 if (unlikely(!crypt_virt)) {
275 spin_unlock_irqrestore(&desc_lock, flags);
276 return NULL;
277 }
278 i = idx;
279 if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) {
280 if (++idx >= NPE_QLEN)
281 idx = 0;
282 crypt_virt[i].ctl_flags = CTL_FLAG_USED;
283 spin_unlock_irqrestore(&desc_lock, flags);
284 return crypt_virt +i;
285 } else {
286 spin_unlock_irqrestore(&desc_lock, flags);
287 return NULL;
288 }
289 }
290
291 static spinlock_t emerg_lock;
292 static struct crypt_ctl *get_crypt_desc_emerg(void)
293 {
294 int i;
295 static int idx = NPE_QLEN;
296 struct crypt_ctl *desc;
297 unsigned long flags;
298
299 desc = get_crypt_desc();
300 if (desc)
301 return desc;
302 if (unlikely(!crypt_virt))
303 return NULL;
304
305 spin_lock_irqsave(&emerg_lock, flags);
306 i = idx;
307 if (crypt_virt[i].ctl_flags == CTL_FLAG_UNUSED) {
308 if (++idx >= NPE_QLEN_TOTAL)
309 idx = NPE_QLEN;
310 crypt_virt[i].ctl_flags = CTL_FLAG_USED;
311 spin_unlock_irqrestore(&emerg_lock, flags);
312 return crypt_virt +i;
313 } else {
314 spin_unlock_irqrestore(&emerg_lock, flags);
315 return NULL;
316 }
317 }
318
319 static void free_buf_chain(struct device *dev, struct buffer_desc *buf,u32 phys)
320 {
321 while (buf) {
322 struct buffer_desc *buf1;
323 u32 phys1;
324
325 buf1 = buf->next;
326 phys1 = buf->phys_next;
327 dma_unmap_single(dev, buf->phys_next, buf->buf_len, buf->dir);
328 dma_pool_free(buffer_pool, buf, phys);
329 buf = buf1;
330 phys = phys1;
331 }
332 }
333
334 static struct tasklet_struct crypto_done_tasklet;
335
336 static void finish_scattered_hmac(struct crypt_ctl *crypt)
337 {
338 struct aead_request *req = crypt->data.aead_req;
339 struct aead_ctx *req_ctx = aead_request_ctx(req);
340 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
341 int authsize = crypto_aead_authsize(tfm);
342 int decryptlen = req->cryptlen - authsize;
343
344 if (req_ctx->encrypt) {
345 scatterwalk_map_and_copy(req_ctx->hmac_virt,
346 req->src, decryptlen, authsize, 1);
347 }
348 dma_pool_free(buffer_pool, req_ctx->hmac_virt, crypt->icv_rev_aes);
349 }
350
351 static void one_packet(dma_addr_t phys)
352 {
353 struct device *dev = &pdev->dev;
354 struct crypt_ctl *crypt;
355 struct ixp_ctx *ctx;
356 int failed;
357
358 failed = phys & 0x1 ? -EBADMSG : 0;
359 phys &= ~0x3;
360 crypt = crypt_phys2virt(phys);
361
362 switch (crypt->ctl_flags & CTL_FLAG_MASK) {
363 case CTL_FLAG_PERFORM_AEAD: {
364 struct aead_request *req = crypt->data.aead_req;
365 struct aead_ctx *req_ctx = aead_request_ctx(req);
366
367 free_buf_chain(dev, req_ctx->buffer, crypt->src_buf);
368 if (req_ctx->hmac_virt) {
369 finish_scattered_hmac(crypt);
370 }
371 req->base.complete(&req->base, failed);
372 break;
373 }
374 case CTL_FLAG_PERFORM_ABLK: {
375 struct ablkcipher_request *req = crypt->data.ablk_req;
376 struct ablk_ctx *req_ctx = ablkcipher_request_ctx(req);
377
378 if (req_ctx->dst) {
379 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
380 }
381 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
382 req->base.complete(&req->base, failed);
383 break;
384 }
385 case CTL_FLAG_GEN_ICV:
386 ctx = crypto_tfm_ctx(crypt->data.tfm);
387 dma_pool_free(ctx_pool, crypt->regist_ptr,
388 crypt->regist_buf->phys_addr);
389 dma_pool_free(buffer_pool, crypt->regist_buf, crypt->src_buf);
390 if (atomic_dec_and_test(&ctx->configuring))
391 complete(&ctx->completion);
392 break;
393 case CTL_FLAG_GEN_REVAES:
394 ctx = crypto_tfm_ctx(crypt->data.tfm);
395 *(u32*)ctx->decrypt.npe_ctx &= cpu_to_be32(~CIPH_ENCR);
396 if (atomic_dec_and_test(&ctx->configuring))
397 complete(&ctx->completion);
398 break;
399 default:
400 BUG();
401 }
402 crypt->ctl_flags = CTL_FLAG_UNUSED;
403 }
404
405 static void irqhandler(void *_unused)
406 {
407 tasklet_schedule(&crypto_done_tasklet);
408 }
409
410 static void crypto_done_action(unsigned long arg)
411 {
412 int i;
413
414 for(i=0; i<4; i++) {
415 dma_addr_t phys = qmgr_get_entry(RECV_QID);
416 if (!phys)
417 return;
418 one_packet(phys);
419 }
420 tasklet_schedule(&crypto_done_tasklet);
421 }
422
423 static int init_ixp_crypto(struct device *dev)
424 {
425 int ret = -ENODEV;
426 u32 msg[2] = { 0, 0 };
427
428 if (! ( ~(*IXP4XX_EXP_CFG2) & (IXP4XX_FEATURE_HASH |
429 IXP4XX_FEATURE_AES | IXP4XX_FEATURE_DES))) {
430 printk(KERN_ERR "ixp_crypto: No HW crypto available\n");
431 return ret;
432 }
433 npe_c = npe_request(NPE_ID);
434 if (!npe_c)
435 return ret;
436
437 if (!npe_running(npe_c)) {
438 ret = npe_load_firmware(npe_c, npe_name(npe_c), dev);
439 if (ret) {
440 return ret;
441 }
442 if (npe_recv_message(npe_c, msg, "STATUS_MSG"))
443 goto npe_error;
444 } else {
445 if (npe_send_message(npe_c, msg, "STATUS_MSG"))
446 goto npe_error;
447
448 if (npe_recv_message(npe_c, msg, "STATUS_MSG"))
449 goto npe_error;
450 }
451
452 switch ((msg[1]>>16) & 0xff) {
453 case 3:
454 printk(KERN_WARNING "Firmware of %s lacks AES support\n",
455 npe_name(npe_c));
456 support_aes = 0;
457 break;
458 case 4:
459 case 5:
460 support_aes = 1;
461 break;
462 default:
463 printk(KERN_ERR "Firmware of %s lacks crypto support\n",
464 npe_name(npe_c));
465 return -ENODEV;
466 }
467 /* buffer_pool will also be used to sometimes store the hmac,
468 * so assure it is large enough
469 */
470 BUILD_BUG_ON(SHA1_DIGEST_SIZE > sizeof(struct buffer_desc));
471 buffer_pool = dma_pool_create("buffer", dev,
472 sizeof(struct buffer_desc), 32, 0);
473 ret = -ENOMEM;
474 if (!buffer_pool) {
475 goto err;
476 }
477 ctx_pool = dma_pool_create("context", dev,
478 NPE_CTX_LEN, 16, 0);
479 if (!ctx_pool) {
480 goto err;
481 }
482 ret = qmgr_request_queue(SEND_QID, NPE_QLEN_TOTAL, 0, 0,
483 "ixp_crypto:out", NULL);
484 if (ret)
485 goto err;
486 ret = qmgr_request_queue(RECV_QID, NPE_QLEN, 0, 0,
487 "ixp_crypto:in", NULL);
488 if (ret) {
489 qmgr_release_queue(SEND_QID);
490 goto err;
491 }
492 qmgr_set_irq(RECV_QID, QUEUE_IRQ_SRC_NOT_EMPTY, irqhandler, NULL);
493 tasklet_init(&crypto_done_tasklet, crypto_done_action, 0);
494
495 qmgr_enable_irq(RECV_QID);
496 return 0;
497
498 npe_error:
499 printk(KERN_ERR "%s not responding\n", npe_name(npe_c));
500 ret = -EIO;
501 err:
502 if (ctx_pool)
503 dma_pool_destroy(ctx_pool);
504 if (buffer_pool)
505 dma_pool_destroy(buffer_pool);
506 npe_release(npe_c);
507 return ret;
508 }
509
510 static void release_ixp_crypto(struct device *dev)
511 {
512 qmgr_disable_irq(RECV_QID);
513 tasklet_kill(&crypto_done_tasklet);
514
515 qmgr_release_queue(SEND_QID);
516 qmgr_release_queue(RECV_QID);
517
518 dma_pool_destroy(ctx_pool);
519 dma_pool_destroy(buffer_pool);
520
521 npe_release(npe_c);
522
523 if (crypt_virt) {
524 dma_free_coherent(dev,
525 NPE_QLEN_TOTAL * sizeof( struct crypt_ctl),
526 crypt_virt, crypt_phys);
527 }
528 return;
529 }
530
531 static void reset_sa_dir(struct ix_sa_dir *dir)
532 {
533 memset(dir->npe_ctx, 0, NPE_CTX_LEN);
534 dir->npe_ctx_idx = 0;
535 dir->npe_mode = 0;
536 }
537
538 static int init_sa_dir(struct ix_sa_dir *dir)
539 {
540 dir->npe_ctx = dma_pool_alloc(ctx_pool, GFP_KERNEL, &dir->npe_ctx_phys);
541 if (!dir->npe_ctx) {
542 return -ENOMEM;
543 }
544 reset_sa_dir(dir);
545 return 0;
546 }
547
548 static void free_sa_dir(struct ix_sa_dir *dir)
549 {
550 memset(dir->npe_ctx, 0, NPE_CTX_LEN);
551 dma_pool_free(ctx_pool, dir->npe_ctx, dir->npe_ctx_phys);
552 }
553
554 static int init_tfm(struct crypto_tfm *tfm)
555 {
556 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
557 int ret;
558
559 atomic_set(&ctx->configuring, 0);
560 ret = init_sa_dir(&ctx->encrypt);
561 if (ret)
562 return ret;
563 ret = init_sa_dir(&ctx->decrypt);
564 if (ret) {
565 free_sa_dir(&ctx->encrypt);
566 }
567 return ret;
568 }
569
570 static int init_tfm_ablk(struct crypto_tfm *tfm)
571 {
572 tfm->crt_ablkcipher.reqsize = sizeof(struct ablk_ctx);
573 return init_tfm(tfm);
574 }
575
576 static int init_tfm_aead(struct crypto_tfm *tfm)
577 {
578 crypto_aead_set_reqsize(__crypto_aead_cast(tfm),
579 sizeof(struct aead_ctx));
580 return init_tfm(tfm);
581 }
582
583 static void exit_tfm(struct crypto_tfm *tfm)
584 {
585 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
586 free_sa_dir(&ctx->encrypt);
587 free_sa_dir(&ctx->decrypt);
588 }
589
590 static int register_chain_var(struct crypto_tfm *tfm, u8 xpad, u32 target,
591 int init_len, u32 ctx_addr, const u8 *key, int key_len)
592 {
593 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
594 struct crypt_ctl *crypt;
595 struct buffer_desc *buf;
596 int i;
597 u8 *pad;
598 u32 pad_phys, buf_phys;
599
600 BUILD_BUG_ON(NPE_CTX_LEN < HMAC_PAD_BLOCKLEN);
601 pad = dma_pool_alloc(ctx_pool, GFP_KERNEL, &pad_phys);
602 if (!pad)
603 return -ENOMEM;
604 buf = dma_pool_alloc(buffer_pool, GFP_KERNEL, &buf_phys);
605 if (!buf) {
606 dma_pool_free(ctx_pool, pad, pad_phys);
607 return -ENOMEM;
608 }
609 crypt = get_crypt_desc_emerg();
610 if (!crypt) {
611 dma_pool_free(ctx_pool, pad, pad_phys);
612 dma_pool_free(buffer_pool, buf, buf_phys);
613 return -EAGAIN;
614 }
615
616 memcpy(pad, key, key_len);
617 memset(pad + key_len, 0, HMAC_PAD_BLOCKLEN - key_len);
618 for (i = 0; i < HMAC_PAD_BLOCKLEN; i++) {
619 pad[i] ^= xpad;
620 }
621
622 crypt->data.tfm = tfm;
623 crypt->regist_ptr = pad;
624 crypt->regist_buf = buf;
625
626 crypt->auth_offs = 0;
627 crypt->auth_len = HMAC_PAD_BLOCKLEN;
628 crypt->crypto_ctx = ctx_addr;
629 crypt->src_buf = buf_phys;
630 crypt->icv_rev_aes = target;
631 crypt->mode = NPE_OP_HASH_GEN_ICV;
632 crypt->init_len = init_len;
633 crypt->ctl_flags |= CTL_FLAG_GEN_ICV;
634
635 buf->next = 0;
636 buf->buf_len = HMAC_PAD_BLOCKLEN;
637 buf->pkt_len = 0;
638 buf->phys_addr = pad_phys;
639
640 atomic_inc(&ctx->configuring);
641 qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
642 BUG_ON(qmgr_stat_overflow(SEND_QID));
643 return 0;
644 }
645
646 static int setup_auth(struct crypto_tfm *tfm, int encrypt, unsigned authsize,
647 const u8 *key, int key_len, unsigned digest_len)
648 {
649 u32 itarget, otarget, npe_ctx_addr;
650 unsigned char *cinfo;
651 int init_len, ret = 0;
652 u32 cfgword;
653 struct ix_sa_dir *dir;
654 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
655 const struct ix_hash_algo *algo;
656
657 dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
658 cinfo = dir->npe_ctx + dir->npe_ctx_idx;
659 algo = ix_hash(tfm);
660
661 /* write cfg word to cryptinfo */
662 cfgword = algo->cfgword | ( authsize << 6); /* (authsize/4) << 8 */
663 #ifndef __ARMEB__
664 cfgword ^= 0xAA000000; /* change the "byte swap" flags */
665 #endif
666 *(u32*)cinfo = cpu_to_be32(cfgword);
667 cinfo += sizeof(cfgword);
668
669 /* write ICV to cryptinfo */
670 memcpy(cinfo, algo->icv, digest_len);
671 cinfo += digest_len;
672
673 itarget = dir->npe_ctx_phys + dir->npe_ctx_idx
674 + sizeof(algo->cfgword);
675 otarget = itarget + digest_len;
676 init_len = cinfo - (dir->npe_ctx + dir->npe_ctx_idx);
677 npe_ctx_addr = dir->npe_ctx_phys + dir->npe_ctx_idx;
678
679 dir->npe_ctx_idx += init_len;
680 dir->npe_mode |= NPE_OP_HASH_ENABLE;
681
682 if (!encrypt)
683 dir->npe_mode |= NPE_OP_HASH_VERIFY;
684
685 ret = register_chain_var(tfm, HMAC_OPAD_VALUE, otarget,
686 init_len, npe_ctx_addr, key, key_len);
687 if (ret)
688 return ret;
689 return register_chain_var(tfm, HMAC_IPAD_VALUE, itarget,
690 init_len, npe_ctx_addr, key, key_len);
691 }
692
693 static int gen_rev_aes_key(struct crypto_tfm *tfm)
694 {
695 struct crypt_ctl *crypt;
696 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
697 struct ix_sa_dir *dir = &ctx->decrypt;
698
699 crypt = get_crypt_desc_emerg();
700 if (!crypt) {
701 return -EAGAIN;
702 }
703 *(u32*)dir->npe_ctx |= cpu_to_be32(CIPH_ENCR);
704
705 crypt->data.tfm = tfm;
706 crypt->crypt_offs = 0;
707 crypt->crypt_len = AES_BLOCK128;
708 crypt->src_buf = 0;
709 crypt->crypto_ctx = dir->npe_ctx_phys;
710 crypt->icv_rev_aes = dir->npe_ctx_phys + sizeof(u32);
711 crypt->mode = NPE_OP_ENC_GEN_KEY;
712 crypt->init_len = dir->npe_ctx_idx;
713 crypt->ctl_flags |= CTL_FLAG_GEN_REVAES;
714
715 atomic_inc(&ctx->configuring);
716 qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
717 BUG_ON(qmgr_stat_overflow(SEND_QID));
718 return 0;
719 }
720
721 static int setup_cipher(struct crypto_tfm *tfm, int encrypt,
722 const u8 *key, int key_len)
723 {
724 u8 *cinfo;
725 u32 cipher_cfg;
726 u32 keylen_cfg = 0;
727 struct ix_sa_dir *dir;
728 struct ixp_ctx *ctx = crypto_tfm_ctx(tfm);
729 u32 *flags = &tfm->crt_flags;
730
731 dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
732 cinfo = dir->npe_ctx;
733
734 if (encrypt) {
735 cipher_cfg = cipher_cfg_enc(tfm);
736 dir->npe_mode |= NPE_OP_CRYPT_ENCRYPT;
737 } else {
738 cipher_cfg = cipher_cfg_dec(tfm);
739 }
740 if (cipher_cfg & MOD_AES) {
741 switch (key_len) {
742 case 16: keylen_cfg = MOD_AES128; break;
743 case 24: keylen_cfg = MOD_AES192; break;
744 case 32: keylen_cfg = MOD_AES256; break;
745 default:
746 *flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
747 return -EINVAL;
748 }
749 cipher_cfg |= keylen_cfg;
750 } else if (cipher_cfg & MOD_3DES) {
751 const u32 *K = (const u32 *)key;
752 if (unlikely(!((K[0] ^ K[2]) | (K[1] ^ K[3])) ||
753 !((K[2] ^ K[4]) | (K[3] ^ K[5]))))
754 {
755 *flags |= CRYPTO_TFM_RES_BAD_KEY_SCHED;
756 return -EINVAL;
757 }
758 } else {
759 u32 tmp[DES_EXPKEY_WORDS];
760 if (des_ekey(tmp, key) == 0) {
761 *flags |= CRYPTO_TFM_RES_WEAK_KEY;
762 }
763 }
764 /* write cfg word to cryptinfo */
765 *(u32*)cinfo = cpu_to_be32(cipher_cfg);
766 cinfo += sizeof(cipher_cfg);
767
768 /* write cipher key to cryptinfo */
769 memcpy(cinfo, key, key_len);
770 /* NPE wants keylen set to DES3_EDE_KEY_SIZE even for single DES */
771 if (key_len < DES3_EDE_KEY_SIZE && !(cipher_cfg & MOD_AES)) {
772 memset(cinfo + key_len, 0, DES3_EDE_KEY_SIZE -key_len);
773 key_len = DES3_EDE_KEY_SIZE;
774 }
775 dir->npe_ctx_idx = sizeof(cipher_cfg) + key_len;
776 dir->npe_mode |= NPE_OP_CRYPT_ENABLE;
777 if ((cipher_cfg & MOD_AES) && !encrypt) {
778 return gen_rev_aes_key(tfm);
779 }
780 return 0;
781 }
782
783 static struct buffer_desc *chainup_buffers(struct device *dev,
784 struct scatterlist *sg, unsigned nbytes,
785 struct buffer_desc *buf, gfp_t flags,
786 enum dma_data_direction dir)
787 {
788 for (; nbytes > 0; sg = sg_next(sg)) {
789 unsigned len = min(nbytes, sg->length);
790 struct buffer_desc *next_buf;
791 u32 next_buf_phys;
792 void *ptr;
793
794 nbytes -= len;
795 ptr = page_address(sg_page(sg)) + sg->offset;
796 next_buf = dma_pool_alloc(buffer_pool, flags, &next_buf_phys);
797 if (!next_buf) {
798 buf = NULL;
799 break;
800 }
801 sg_dma_address(sg) = dma_map_single(dev, ptr, len, dir);
802 buf->next = next_buf;
803 buf->phys_next = next_buf_phys;
804 buf = next_buf;
805
806 buf->phys_addr = sg_dma_address(sg);
807 buf->buf_len = len;
808 buf->dir = dir;
809 }
810 buf->next = NULL;
811 buf->phys_next = 0;
812 return buf;
813 }
814
815 static int ablk_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
816 unsigned int key_len)
817 {
818 struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
819 u32 *flags = &tfm->base.crt_flags;
820 int ret;
821
822 init_completion(&ctx->completion);
823 atomic_inc(&ctx->configuring);
824
825 reset_sa_dir(&ctx->encrypt);
826 reset_sa_dir(&ctx->decrypt);
827
828 ctx->encrypt.npe_mode = NPE_OP_HMAC_DISABLE;
829 ctx->decrypt.npe_mode = NPE_OP_HMAC_DISABLE;
830
831 ret = setup_cipher(&tfm->base, 0, key, key_len);
832 if (ret)
833 goto out;
834 ret = setup_cipher(&tfm->base, 1, key, key_len);
835 if (ret)
836 goto out;
837
838 if (*flags & CRYPTO_TFM_RES_WEAK_KEY) {
839 if (*flags & CRYPTO_TFM_REQ_WEAK_KEY) {
840 ret = -EINVAL;
841 } else {
842 *flags &= ~CRYPTO_TFM_RES_WEAK_KEY;
843 }
844 }
845 out:
846 if (!atomic_dec_and_test(&ctx->configuring))
847 wait_for_completion(&ctx->completion);
848 return ret;
849 }
850
851 static int ablk_rfc3686_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
852 unsigned int key_len)
853 {
854 struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
855
856 /* the nonce is stored in bytes at end of key */
857 if (key_len < CTR_RFC3686_NONCE_SIZE)
858 return -EINVAL;
859
860 memcpy(ctx->nonce, key + (key_len - CTR_RFC3686_NONCE_SIZE),
861 CTR_RFC3686_NONCE_SIZE);
862
863 key_len -= CTR_RFC3686_NONCE_SIZE;
864 return ablk_setkey(tfm, key, key_len);
865 }
866
867 static int ablk_perform(struct ablkcipher_request *req, int encrypt)
868 {
869 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
870 struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
871 unsigned ivsize = crypto_ablkcipher_ivsize(tfm);
872 struct ix_sa_dir *dir;
873 struct crypt_ctl *crypt;
874 unsigned int nbytes = req->nbytes;
875 enum dma_data_direction src_direction = DMA_BIDIRECTIONAL;
876 struct ablk_ctx *req_ctx = ablkcipher_request_ctx(req);
877 struct buffer_desc src_hook;
878 struct device *dev = &pdev->dev;
879 gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
880 GFP_KERNEL : GFP_ATOMIC;
881
882 if (qmgr_stat_full(SEND_QID))
883 return -EAGAIN;
884 if (atomic_read(&ctx->configuring))
885 return -EAGAIN;
886
887 dir = encrypt ? &ctx->encrypt : &ctx->decrypt;
888
889 crypt = get_crypt_desc();
890 if (!crypt)
891 return -ENOMEM;
892
893 crypt->data.ablk_req = req;
894 crypt->crypto_ctx = dir->npe_ctx_phys;
895 crypt->mode = dir->npe_mode;
896 crypt->init_len = dir->npe_ctx_idx;
897
898 crypt->crypt_offs = 0;
899 crypt->crypt_len = nbytes;
900
901 BUG_ON(ivsize && !req->info);
902 memcpy(crypt->iv, req->info, ivsize);
903 if (req->src != req->dst) {
904 struct buffer_desc dst_hook;
905 crypt->mode |= NPE_OP_NOT_IN_PLACE;
906 /* This was never tested by Intel
907 * for more than one dst buffer, I think. */
908 BUG_ON(req->dst->length < nbytes);
909 req_ctx->dst = NULL;
910 if (!chainup_buffers(dev, req->dst, nbytes, &dst_hook,
911 flags, DMA_FROM_DEVICE))
912 goto free_buf_dest;
913 src_direction = DMA_TO_DEVICE;
914 req_ctx->dst = dst_hook.next;
915 crypt->dst_buf = dst_hook.phys_next;
916 } else {
917 req_ctx->dst = NULL;
918 }
919 req_ctx->src = NULL;
920 if (!chainup_buffers(dev, req->src, nbytes, &src_hook,
921 flags, src_direction))
922 goto free_buf_src;
923
924 req_ctx->src = src_hook.next;
925 crypt->src_buf = src_hook.phys_next;
926 crypt->ctl_flags |= CTL_FLAG_PERFORM_ABLK;
927 qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
928 BUG_ON(qmgr_stat_overflow(SEND_QID));
929 return -EINPROGRESS;
930
931 free_buf_src:
932 free_buf_chain(dev, req_ctx->src, crypt->src_buf);
933 free_buf_dest:
934 if (req->src != req->dst) {
935 free_buf_chain(dev, req_ctx->dst, crypt->dst_buf);
936 }
937 crypt->ctl_flags = CTL_FLAG_UNUSED;
938 return -ENOMEM;
939 }
940
941 static int ablk_encrypt(struct ablkcipher_request *req)
942 {
943 return ablk_perform(req, 1);
944 }
945
946 static int ablk_decrypt(struct ablkcipher_request *req)
947 {
948 return ablk_perform(req, 0);
949 }
950
951 static int ablk_rfc3686_crypt(struct ablkcipher_request *req)
952 {
953 struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
954 struct ixp_ctx *ctx = crypto_ablkcipher_ctx(tfm);
955 u8 iv[CTR_RFC3686_BLOCK_SIZE];
956 u8 *info = req->info;
957 int ret;
958
959 /* set up counter block */
960 memcpy(iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE);
961 memcpy(iv + CTR_RFC3686_NONCE_SIZE, info, CTR_RFC3686_IV_SIZE);
962
963 /* initialize counter portion of counter block */
964 *(__be32 *)(iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =
965 cpu_to_be32(1);
966
967 req->info = iv;
968 ret = ablk_perform(req, 1);
969 req->info = info;
970 return ret;
971 }
972
973 static int hmac_inconsistent(struct scatterlist *sg, unsigned start,
974 unsigned int nbytes)
975 {
976 int offset = 0;
977
978 if (!nbytes)
979 return 0;
980
981 for (;;) {
982 if (start < offset + sg->length)
983 break;
984
985 offset += sg->length;
986 sg = sg_next(sg);
987 }
988 return (start + nbytes > offset + sg->length);
989 }
990
991 static int aead_perform(struct aead_request *req, int encrypt,
992 int cryptoffset, int eff_cryptlen, u8 *iv)
993 {
994 struct crypto_aead *tfm = crypto_aead_reqtfm(req);
995 struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
996 unsigned ivsize = crypto_aead_ivsize(tfm);
997 unsigned authsize = crypto_aead_authsize(tfm);
998 struct ix_sa_dir *dir;
999 struct crypt_ctl *crypt;
1000 unsigned int cryptlen;
1001 struct buffer_desc *buf, src_hook;
1002 struct aead_ctx *req_ctx = aead_request_ctx(req);
1003 struct device *dev = &pdev->dev;
1004 gfp_t flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ?
1005 GFP_KERNEL : GFP_ATOMIC;
1006
1007 if (qmgr_stat_full(SEND_QID))
1008 return -EAGAIN;
1009 if (atomic_read(&ctx->configuring))
1010 return -EAGAIN;
1011
1012 if (encrypt) {
1013 dir = &ctx->encrypt;
1014 cryptlen = req->cryptlen;
1015 } else {
1016 dir = &ctx->decrypt;
1017 /* req->cryptlen includes the authsize when decrypting */
1018 cryptlen = req->cryptlen -authsize;
1019 eff_cryptlen -= authsize;
1020 }
1021 crypt = get_crypt_desc();
1022 if (!crypt)
1023 return -ENOMEM;
1024
1025 crypt->data.aead_req = req;
1026 crypt->crypto_ctx = dir->npe_ctx_phys;
1027 crypt->mode = dir->npe_mode;
1028 crypt->init_len = dir->npe_ctx_idx;
1029
1030 crypt->crypt_offs = cryptoffset;
1031 crypt->crypt_len = eff_cryptlen;
1032
1033 crypt->auth_offs = 0;
1034 crypt->auth_len = req->assoclen + ivsize + cryptlen;
1035 BUG_ON(ivsize && !req->iv);
1036 memcpy(crypt->iv, req->iv, ivsize);
1037
1038 if (req->src != req->dst) {
1039 BUG(); /* -ENOTSUP because of my laziness */
1040 }
1041
1042 /* ASSOC data */
1043 buf = chainup_buffers(dev, req->assoc, req->assoclen, &src_hook,
1044 flags, DMA_TO_DEVICE);
1045 req_ctx->buffer = src_hook.next;
1046 crypt->src_buf = src_hook.phys_next;
1047 if (!buf)
1048 goto out;
1049 /* IV */
1050 sg_init_table(&req_ctx->ivlist, 1);
1051 sg_set_buf(&req_ctx->ivlist, iv, ivsize);
1052 buf = chainup_buffers(dev, &req_ctx->ivlist, ivsize, buf, flags,
1053 DMA_BIDIRECTIONAL);
1054 if (!buf)
1055 goto free_chain;
1056 if (unlikely(hmac_inconsistent(req->src, cryptlen, authsize))) {
1057 /* The 12 hmac bytes are scattered,
1058 * we need to copy them into a safe buffer */
1059 req_ctx->hmac_virt = dma_pool_alloc(buffer_pool, flags,
1060 &crypt->icv_rev_aes);
1061 if (unlikely(!req_ctx->hmac_virt))
1062 goto free_chain;
1063 if (!encrypt) {
1064 scatterwalk_map_and_copy(req_ctx->hmac_virt,
1065 req->src, cryptlen, authsize, 0);
1066 }
1067 req_ctx->encrypt = encrypt;
1068 } else {
1069 req_ctx->hmac_virt = NULL;
1070 }
1071 /* Crypt */
1072 buf = chainup_buffers(dev, req->src, cryptlen + authsize, buf, flags,
1073 DMA_BIDIRECTIONAL);
1074 if (!buf)
1075 goto free_hmac_virt;
1076 if (!req_ctx->hmac_virt) {
1077 crypt->icv_rev_aes = buf->phys_addr + buf->buf_len - authsize;
1078 }
1079
1080 crypt->ctl_flags |= CTL_FLAG_PERFORM_AEAD;
1081 qmgr_put_entry(SEND_QID, crypt_virt2phys(crypt));
1082 BUG_ON(qmgr_stat_overflow(SEND_QID));
1083 return -EINPROGRESS;
1084 free_hmac_virt:
1085 if (req_ctx->hmac_virt) {
1086 dma_pool_free(buffer_pool, req_ctx->hmac_virt,
1087 crypt->icv_rev_aes);
1088 }
1089 free_chain:
1090 free_buf_chain(dev, req_ctx->buffer, crypt->src_buf);
1091 out:
1092 crypt->ctl_flags = CTL_FLAG_UNUSED;
1093 return -ENOMEM;
1094 }
1095
1096 static int aead_setup(struct crypto_aead *tfm, unsigned int authsize)
1097 {
1098 struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1099 u32 *flags = &tfm->base.crt_flags;
1100 unsigned digest_len = crypto_aead_maxauthsize(tfm);
1101 int ret;
1102
1103 if (!ctx->enckey_len && !ctx->authkey_len)
1104 return 0;
1105 init_completion(&ctx->completion);
1106 atomic_inc(&ctx->configuring);
1107
1108 reset_sa_dir(&ctx->encrypt);
1109 reset_sa_dir(&ctx->decrypt);
1110
1111 ret = setup_cipher(&tfm->base, 0, ctx->enckey, ctx->enckey_len);
1112 if (ret)
1113 goto out;
1114 ret = setup_cipher(&tfm->base, 1, ctx->enckey, ctx->enckey_len);
1115 if (ret)
1116 goto out;
1117 ret = setup_auth(&tfm->base, 0, authsize, ctx->authkey,
1118 ctx->authkey_len, digest_len);
1119 if (ret)
1120 goto out;
1121 ret = setup_auth(&tfm->base, 1, authsize, ctx->authkey,
1122 ctx->authkey_len, digest_len);
1123 if (ret)
1124 goto out;
1125
1126 if (*flags & CRYPTO_TFM_RES_WEAK_KEY) {
1127 if (*flags & CRYPTO_TFM_REQ_WEAK_KEY) {
1128 ret = -EINVAL;
1129 goto out;
1130 } else {
1131 *flags &= ~CRYPTO_TFM_RES_WEAK_KEY;
1132 }
1133 }
1134 out:
1135 if (!atomic_dec_and_test(&ctx->configuring))
1136 wait_for_completion(&ctx->completion);
1137 return ret;
1138 }
1139
1140 static int aead_setauthsize(struct crypto_aead *tfm, unsigned int authsize)
1141 {
1142 int max = crypto_aead_maxauthsize(tfm) >> 2;
1143
1144 if ((authsize>>2) < 1 || (authsize>>2) > max || (authsize & 3))
1145 return -EINVAL;
1146 return aead_setup(tfm, authsize);
1147 }
1148
1149 static int aead_setkey(struct crypto_aead *tfm, const u8 *key,
1150 unsigned int keylen)
1151 {
1152 struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1153 struct crypto_authenc_keys keys;
1154
1155 if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
1156 goto badkey;
1157
1158 if (keys.authkeylen > sizeof(ctx->authkey))
1159 goto badkey;
1160
1161 if (keys.enckeylen > sizeof(ctx->enckey))
1162 goto badkey;
1163
1164 memcpy(ctx->authkey, keys.authkey, keys.authkeylen);
1165 memcpy(ctx->enckey, keys.enckey, keys.enckeylen);
1166 ctx->authkey_len = keys.authkeylen;
1167 ctx->enckey_len = keys.enckeylen;
1168
1169 return aead_setup(tfm, crypto_aead_authsize(tfm));
1170 badkey:
1171 crypto_aead_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
1172 return -EINVAL;
1173 }
1174
1175 static int aead_encrypt(struct aead_request *req)
1176 {
1177 unsigned ivsize = crypto_aead_ivsize(crypto_aead_reqtfm(req));
1178 return aead_perform(req, 1, req->assoclen + ivsize,
1179 req->cryptlen, req->iv);
1180 }
1181
1182 static int aead_decrypt(struct aead_request *req)
1183 {
1184 unsigned ivsize = crypto_aead_ivsize(crypto_aead_reqtfm(req));
1185 return aead_perform(req, 0, req->assoclen + ivsize,
1186 req->cryptlen, req->iv);
1187 }
1188
1189 static int aead_givencrypt(struct aead_givcrypt_request *req)
1190 {
1191 struct crypto_aead *tfm = aead_givcrypt_reqtfm(req);
1192 struct ixp_ctx *ctx = crypto_aead_ctx(tfm);
1193 unsigned len, ivsize = crypto_aead_ivsize(tfm);
1194 __be64 seq;
1195
1196 /* copied from eseqiv.c */
1197 if (!ctx->salted) {
1198 get_random_bytes(ctx->salt, ivsize);
1199 ctx->salted = 1;
1200 }
1201 memcpy(req->areq.iv, ctx->salt, ivsize);
1202 len = ivsize;
1203 if (ivsize > sizeof(u64)) {
1204 memset(req->giv, 0, ivsize - sizeof(u64));
1205 len = sizeof(u64);
1206 }
1207 seq = cpu_to_be64(req->seq);
1208 memcpy(req->giv + ivsize - len, &seq, len);
1209 return aead_perform(&req->areq, 1, req->areq.assoclen,
1210 req->areq.cryptlen +ivsize, req->giv);
1211 }
1212
1213 static struct ixp_alg ixp4xx_algos[] = {
1214 {
1215 .crypto = {
1216 .cra_name = "cbc(des)",
1217 .cra_blocksize = DES_BLOCK_SIZE,
1218 .cra_u = { .ablkcipher = {
1219 .min_keysize = DES_KEY_SIZE,
1220 .max_keysize = DES_KEY_SIZE,
1221 .ivsize = DES_BLOCK_SIZE,
1222 .geniv = "eseqiv",
1223 }
1224 }
1225 },
1226 .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1227 .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1228
1229 }, {
1230 .crypto = {
1231 .cra_name = "ecb(des)",
1232 .cra_blocksize = DES_BLOCK_SIZE,
1233 .cra_u = { .ablkcipher = {
1234 .min_keysize = DES_KEY_SIZE,
1235 .max_keysize = DES_KEY_SIZE,
1236 }
1237 }
1238 },
1239 .cfg_enc = CIPH_ENCR | MOD_DES | MOD_ECB | KEYLEN_192,
1240 .cfg_dec = CIPH_DECR | MOD_DES | MOD_ECB | KEYLEN_192,
1241 }, {
1242 .crypto = {
1243 .cra_name = "cbc(des3_ede)",
1244 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1245 .cra_u = { .ablkcipher = {
1246 .min_keysize = DES3_EDE_KEY_SIZE,
1247 .max_keysize = DES3_EDE_KEY_SIZE,
1248 .ivsize = DES3_EDE_BLOCK_SIZE,
1249 .geniv = "eseqiv",
1250 }
1251 }
1252 },
1253 .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1254 .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1255 }, {
1256 .crypto = {
1257 .cra_name = "ecb(des3_ede)",
1258 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1259 .cra_u = { .ablkcipher = {
1260 .min_keysize = DES3_EDE_KEY_SIZE,
1261 .max_keysize = DES3_EDE_KEY_SIZE,
1262 }
1263 }
1264 },
1265 .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_ECB | KEYLEN_192,
1266 .cfg_dec = CIPH_DECR | MOD_3DES | MOD_ECB | KEYLEN_192,
1267 }, {
1268 .crypto = {
1269 .cra_name = "cbc(aes)",
1270 .cra_blocksize = AES_BLOCK_SIZE,
1271 .cra_u = { .ablkcipher = {
1272 .min_keysize = AES_MIN_KEY_SIZE,
1273 .max_keysize = AES_MAX_KEY_SIZE,
1274 .ivsize = AES_BLOCK_SIZE,
1275 .geniv = "eseqiv",
1276 }
1277 }
1278 },
1279 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1280 .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1281 }, {
1282 .crypto = {
1283 .cra_name = "ecb(aes)",
1284 .cra_blocksize = AES_BLOCK_SIZE,
1285 .cra_u = { .ablkcipher = {
1286 .min_keysize = AES_MIN_KEY_SIZE,
1287 .max_keysize = AES_MAX_KEY_SIZE,
1288 }
1289 }
1290 },
1291 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_ECB,
1292 .cfg_dec = CIPH_DECR | MOD_AES | MOD_ECB,
1293 }, {
1294 .crypto = {
1295 .cra_name = "ctr(aes)",
1296 .cra_blocksize = AES_BLOCK_SIZE,
1297 .cra_u = { .ablkcipher = {
1298 .min_keysize = AES_MIN_KEY_SIZE,
1299 .max_keysize = AES_MAX_KEY_SIZE,
1300 .ivsize = AES_BLOCK_SIZE,
1301 .geniv = "eseqiv",
1302 }
1303 }
1304 },
1305 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR,
1306 .cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR,
1307 }, {
1308 .crypto = {
1309 .cra_name = "rfc3686(ctr(aes))",
1310 .cra_blocksize = AES_BLOCK_SIZE,
1311 .cra_u = { .ablkcipher = {
1312 .min_keysize = AES_MIN_KEY_SIZE,
1313 .max_keysize = AES_MAX_KEY_SIZE,
1314 .ivsize = AES_BLOCK_SIZE,
1315 .geniv = "eseqiv",
1316 .setkey = ablk_rfc3686_setkey,
1317 .encrypt = ablk_rfc3686_crypt,
1318 .decrypt = ablk_rfc3686_crypt }
1319 }
1320 },
1321 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CTR,
1322 .cfg_dec = CIPH_ENCR | MOD_AES | MOD_CTR,
1323 }, {
1324 .crypto = {
1325 .cra_name = "authenc(hmac(md5),cbc(des))",
1326 .cra_blocksize = DES_BLOCK_SIZE,
1327 .cra_u = { .aead = {
1328 .ivsize = DES_BLOCK_SIZE,
1329 .maxauthsize = MD5_DIGEST_SIZE,
1330 }
1331 }
1332 },
1333 .hash = &hash_alg_md5,
1334 .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1335 .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1336 }, {
1337 .crypto = {
1338 .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
1339 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1340 .cra_u = { .aead = {
1341 .ivsize = DES3_EDE_BLOCK_SIZE,
1342 .maxauthsize = MD5_DIGEST_SIZE,
1343 }
1344 }
1345 },
1346 .hash = &hash_alg_md5,
1347 .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1348 .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1349 }, {
1350 .crypto = {
1351 .cra_name = "authenc(hmac(sha1),cbc(des))",
1352 .cra_blocksize = DES_BLOCK_SIZE,
1353 .cra_u = { .aead = {
1354 .ivsize = DES_BLOCK_SIZE,
1355 .maxauthsize = SHA1_DIGEST_SIZE,
1356 }
1357 }
1358 },
1359 .hash = &hash_alg_sha1,
1360 .cfg_enc = CIPH_ENCR | MOD_DES | MOD_CBC_ENC | KEYLEN_192,
1361 .cfg_dec = CIPH_DECR | MOD_DES | MOD_CBC_DEC | KEYLEN_192,
1362 }, {
1363 .crypto = {
1364 .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1365 .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1366 .cra_u = { .aead = {
1367 .ivsize = DES3_EDE_BLOCK_SIZE,
1368 .maxauthsize = SHA1_DIGEST_SIZE,
1369 }
1370 }
1371 },
1372 .hash = &hash_alg_sha1,
1373 .cfg_enc = CIPH_ENCR | MOD_3DES | MOD_CBC_ENC | KEYLEN_192,
1374 .cfg_dec = CIPH_DECR | MOD_3DES | MOD_CBC_DEC | KEYLEN_192,
1375 }, {
1376 .crypto = {
1377 .cra_name = "authenc(hmac(md5),cbc(aes))",
1378 .cra_blocksize = AES_BLOCK_SIZE,
1379 .cra_u = { .aead = {
1380 .ivsize = AES_BLOCK_SIZE,
1381 .maxauthsize = MD5_DIGEST_SIZE,
1382 }
1383 }
1384 },
1385 .hash = &hash_alg_md5,
1386 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1387 .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1388 }, {
1389 .crypto = {
1390 .cra_name = "authenc(hmac(sha1),cbc(aes))",
1391 .cra_blocksize = AES_BLOCK_SIZE,
1392 .cra_u = { .aead = {
1393 .ivsize = AES_BLOCK_SIZE,
1394 .maxauthsize = SHA1_DIGEST_SIZE,
1395 }
1396 }
1397 },
1398 .hash = &hash_alg_sha1,
1399 .cfg_enc = CIPH_ENCR | MOD_AES | MOD_CBC_ENC,
1400 .cfg_dec = CIPH_DECR | MOD_AES | MOD_CBC_DEC,
1401 } };
1402
1403 #define IXP_POSTFIX "-ixp4xx"
1404
1405 static const struct platform_device_info ixp_dev_info __initdata = {
1406 .name = DRIVER_NAME,
1407 .id = 0,
1408 .dma_mask = DMA_BIT_MASK(32),
1409 };
1410
1411 static int __init ixp_module_init(void)
1412 {
1413 int num = ARRAY_SIZE(ixp4xx_algos);
1414 int i, err;
1415
1416 pdev = platform_device_register_full(&ixp_dev_info);
1417 if (IS_ERR(pdev))
1418 return PTR_ERR(pdev);
1419
1420 spin_lock_init(&desc_lock);
1421 spin_lock_init(&emerg_lock);
1422
1423 err = init_ixp_crypto(&pdev->dev);
1424 if (err) {
1425 platform_device_unregister(pdev);
1426 return err;
1427 }
1428 for (i=0; i< num; i++) {
1429 struct crypto_alg *cra = &ixp4xx_algos[i].crypto;
1430
1431 if (snprintf(cra->cra_driver_name, CRYPTO_MAX_ALG_NAME,
1432 "%s"IXP_POSTFIX, cra->cra_name) >=
1433 CRYPTO_MAX_ALG_NAME)
1434 {
1435 continue;
1436 }
1437 if (!support_aes && (ixp4xx_algos[i].cfg_enc & MOD_AES)) {
1438 continue;
1439 }
1440 if (!ixp4xx_algos[i].hash) {
1441 /* block ciphers */
1442 cra->cra_type = &crypto_ablkcipher_type;
1443 cra->cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1444 CRYPTO_ALG_KERN_DRIVER_ONLY |
1445 CRYPTO_ALG_ASYNC;
1446 if (!cra->cra_ablkcipher.setkey)
1447 cra->cra_ablkcipher.setkey = ablk_setkey;
1448 if (!cra->cra_ablkcipher.encrypt)
1449 cra->cra_ablkcipher.encrypt = ablk_encrypt;
1450 if (!cra->cra_ablkcipher.decrypt)
1451 cra->cra_ablkcipher.decrypt = ablk_decrypt;
1452 cra->cra_init = init_tfm_ablk;
1453 } else {
1454 /* authenc */
1455 cra->cra_type = &crypto_aead_type;
1456 cra->cra_flags = CRYPTO_ALG_TYPE_AEAD |
1457 CRYPTO_ALG_KERN_DRIVER_ONLY |
1458 CRYPTO_ALG_ASYNC;
1459 cra->cra_aead.setkey = aead_setkey;
1460 cra->cra_aead.setauthsize = aead_setauthsize;
1461 cra->cra_aead.encrypt = aead_encrypt;
1462 cra->cra_aead.decrypt = aead_decrypt;
1463 cra->cra_aead.givencrypt = aead_givencrypt;
1464 cra->cra_init = init_tfm_aead;
1465 }
1466 cra->cra_ctxsize = sizeof(struct ixp_ctx);
1467 cra->cra_module = THIS_MODULE;
1468 cra->cra_alignmask = 3;
1469 cra->cra_priority = 300;
1470 cra->cra_exit = exit_tfm;
1471 if (crypto_register_alg(cra))
1472 printk(KERN_ERR "Failed to register '%s'\n",
1473 cra->cra_name);
1474 else
1475 ixp4xx_algos[i].registered = 1;
1476 }
1477 return 0;
1478 }
1479
1480 static void __exit ixp_module_exit(void)
1481 {
1482 int num = ARRAY_SIZE(ixp4xx_algos);
1483 int i;
1484
1485 for (i=0; i< num; i++) {
1486 if (ixp4xx_algos[i].registered)
1487 crypto_unregister_alg(&ixp4xx_algos[i].crypto);
1488 }
1489 release_ixp_crypto(&pdev->dev);
1490 platform_device_unregister(pdev);
1491 }
1492
1493 module_init(ixp_module_init);
1494 module_exit(ixp_module_exit);
1495
1496 MODULE_LICENSE("GPL");
1497 MODULE_AUTHOR("Christian Hohnstaedt <chohnstaedt@innominate.com>");
1498 MODULE_DESCRIPTION("IXP4xx hardware crypto");
1499
Linux kernel - Deliverables
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