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drm/amdgpu: fix warning in scheduler
[deliverable/linux.git] / drivers / crypto / omap-aes.c
1 /*
2 * Cryptographic API.
3 *
4 * Support for OMAP AES HW acceleration.
5 *
6 * Copyright (c) 2010 Nokia Corporation
7 * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
8 * Copyright (c) 2011 Texas Instruments Incorporated
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as published
12 * by the Free Software Foundation.
13 *
14 */
15
16 #define pr_fmt(fmt) "%20s: " fmt, __func__
17 #define prn(num) pr_debug(#num "=%d\n", num)
18 #define prx(num) pr_debug(#num "=%x\n", num)
19
20 #include <linux/err.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/errno.h>
24 #include <linux/kernel.h>
25 #include <linux/platform_device.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/dmaengine.h>
29 #include <linux/omap-dma.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/of.h>
32 #include <linux/of_device.h>
33 #include <linux/of_address.h>
34 #include <linux/io.h>
35 #include <linux/crypto.h>
36 #include <linux/interrupt.h>
37 #include <crypto/scatterwalk.h>
38 #include <crypto/aes.h>
39
40 #define DST_MAXBURST 4
41 #define DMA_MIN (DST_MAXBURST * sizeof(u32))
42
43 #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
44
45 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
46 number. For example 7:0 */
47 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
48 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
49
50 #define AES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
51 ((x ^ 0x01) * 0x04))
52 #define AES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
53
54 #define AES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
55 #define AES_REG_CTRL_CTR_WIDTH_MASK (3 << 7)
56 #define AES_REG_CTRL_CTR_WIDTH_32 (0 << 7)
57 #define AES_REG_CTRL_CTR_WIDTH_64 (1 << 7)
58 #define AES_REG_CTRL_CTR_WIDTH_96 (2 << 7)
59 #define AES_REG_CTRL_CTR_WIDTH_128 (3 << 7)
60 #define AES_REG_CTRL_CTR (1 << 6)
61 #define AES_REG_CTRL_CBC (1 << 5)
62 #define AES_REG_CTRL_KEY_SIZE (3 << 3)
63 #define AES_REG_CTRL_DIRECTION (1 << 2)
64 #define AES_REG_CTRL_INPUT_READY (1 << 1)
65 #define AES_REG_CTRL_OUTPUT_READY (1 << 0)
66
67 #define AES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
68
69 #define AES_REG_REV(dd) ((dd)->pdata->rev_ofs)
70
71 #define AES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
72 #define AES_REG_MASK_SIDLE (1 << 6)
73 #define AES_REG_MASK_START (1 << 5)
74 #define AES_REG_MASK_DMA_OUT_EN (1 << 3)
75 #define AES_REG_MASK_DMA_IN_EN (1 << 2)
76 #define AES_REG_MASK_SOFTRESET (1 << 1)
77 #define AES_REG_AUTOIDLE (1 << 0)
78
79 #define AES_REG_LENGTH_N(x) (0x54 + ((x) * 0x04))
80
81 #define AES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs)
82 #define AES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs)
83 #define AES_REG_IRQ_DATA_IN BIT(1)
84 #define AES_REG_IRQ_DATA_OUT BIT(2)
85 #define DEFAULT_TIMEOUT (5*HZ)
86
87 #define FLAGS_MODE_MASK 0x000f
88 #define FLAGS_ENCRYPT BIT(0)
89 #define FLAGS_CBC BIT(1)
90 #define FLAGS_GIV BIT(2)
91 #define FLAGS_CTR BIT(3)
92
93 #define FLAGS_INIT BIT(4)
94 #define FLAGS_FAST BIT(5)
95 #define FLAGS_BUSY BIT(6)
96
97 #define AES_BLOCK_WORDS (AES_BLOCK_SIZE >> 2)
98
99 struct omap_aes_ctx {
100 struct omap_aes_dev *dd;
101
102 int keylen;
103 u32 key[AES_KEYSIZE_256 / sizeof(u32)];
104 unsigned long flags;
105 };
106
107 struct omap_aes_reqctx {
108 unsigned long mode;
109 };
110
111 #define OMAP_AES_QUEUE_LENGTH 1
112 #define OMAP_AES_CACHE_SIZE 0
113
114 struct omap_aes_algs_info {
115 struct crypto_alg *algs_list;
116 unsigned int size;
117 unsigned int registered;
118 };
119
120 struct omap_aes_pdata {
121 struct omap_aes_algs_info *algs_info;
122 unsigned int algs_info_size;
123
124 void (*trigger)(struct omap_aes_dev *dd, int length);
125
126 u32 key_ofs;
127 u32 iv_ofs;
128 u32 ctrl_ofs;
129 u32 data_ofs;
130 u32 rev_ofs;
131 u32 mask_ofs;
132 u32 irq_enable_ofs;
133 u32 irq_status_ofs;
134
135 u32 dma_enable_in;
136 u32 dma_enable_out;
137 u32 dma_start;
138
139 u32 major_mask;
140 u32 major_shift;
141 u32 minor_mask;
142 u32 minor_shift;
143 };
144
145 struct omap_aes_dev {
146 struct list_head list;
147 unsigned long phys_base;
148 void __iomem *io_base;
149 struct omap_aes_ctx *ctx;
150 struct device *dev;
151 unsigned long flags;
152 int err;
153
154 spinlock_t lock;
155 struct crypto_queue queue;
156
157 struct tasklet_struct done_task;
158 struct tasklet_struct queue_task;
159
160 struct ablkcipher_request *req;
161
162 /*
163 * total is used by PIO mode for book keeping so introduce
164 * variable total_save as need it to calc page_order
165 */
166 size_t total;
167 size_t total_save;
168
169 struct scatterlist *in_sg;
170 struct scatterlist *out_sg;
171
172 /* Buffers for copying for unaligned cases */
173 struct scatterlist in_sgl;
174 struct scatterlist out_sgl;
175 struct scatterlist *orig_out;
176 int sgs_copied;
177
178 struct scatter_walk in_walk;
179 struct scatter_walk out_walk;
180 int dma_in;
181 struct dma_chan *dma_lch_in;
182 int dma_out;
183 struct dma_chan *dma_lch_out;
184 int in_sg_len;
185 int out_sg_len;
186 int pio_only;
187 const struct omap_aes_pdata *pdata;
188 };
189
190 /* keep registered devices data here */
191 static LIST_HEAD(dev_list);
192 static DEFINE_SPINLOCK(list_lock);
193
194 #ifdef DEBUG
195 #define omap_aes_read(dd, offset) \
196 ({ \
197 int _read_ret; \
198 _read_ret = __raw_readl(dd->io_base + offset); \
199 pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \
200 offset, _read_ret); \
201 _read_ret; \
202 })
203 #else
204 static inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
205 {
206 return __raw_readl(dd->io_base + offset);
207 }
208 #endif
209
210 #ifdef DEBUG
211 #define omap_aes_write(dd, offset, value) \
212 do { \
213 pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
214 offset, value); \
215 __raw_writel(value, dd->io_base + offset); \
216 } while (0)
217 #else
218 static inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
219 u32 value)
220 {
221 __raw_writel(value, dd->io_base + offset);
222 }
223 #endif
224
225 static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
226 u32 value, u32 mask)
227 {
228 u32 val;
229
230 val = omap_aes_read(dd, offset);
231 val &= ~mask;
232 val |= value;
233 omap_aes_write(dd, offset, val);
234 }
235
236 static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
237 u32 *value, int count)
238 {
239 for (; count--; value++, offset += 4)
240 omap_aes_write(dd, offset, *value);
241 }
242
243 static int omap_aes_hw_init(struct omap_aes_dev *dd)
244 {
245 if (!(dd->flags & FLAGS_INIT)) {
246 dd->flags |= FLAGS_INIT;
247 dd->err = 0;
248 }
249
250 return 0;
251 }
252
253 static int omap_aes_write_ctrl(struct omap_aes_dev *dd)
254 {
255 unsigned int key32;
256 int i, err;
257 u32 val, mask = 0;
258
259 err = omap_aes_hw_init(dd);
260 if (err)
261 return err;
262
263 key32 = dd->ctx->keylen / sizeof(u32);
264
265 /* it seems a key should always be set even if it has not changed */
266 for (i = 0; i < key32; i++) {
267 omap_aes_write(dd, AES_REG_KEY(dd, i),
268 __le32_to_cpu(dd->ctx->key[i]));
269 }
270
271 if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->info)
272 omap_aes_write_n(dd, AES_REG_IV(dd, 0), dd->req->info, 4);
273
274 val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
275 if (dd->flags & FLAGS_CBC)
276 val |= AES_REG_CTRL_CBC;
277 if (dd->flags & FLAGS_CTR) {
278 val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128;
279 mask = AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_MASK;
280 }
281 if (dd->flags & FLAGS_ENCRYPT)
282 val |= AES_REG_CTRL_DIRECTION;
283
284 mask |= AES_REG_CTRL_CBC | AES_REG_CTRL_DIRECTION |
285 AES_REG_CTRL_KEY_SIZE;
286
287 omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, mask);
288
289 return 0;
290 }
291
292 static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
293 {
294 u32 mask, val;
295
296 val = dd->pdata->dma_start;
297
298 if (dd->dma_lch_out != NULL)
299 val |= dd->pdata->dma_enable_out;
300 if (dd->dma_lch_in != NULL)
301 val |= dd->pdata->dma_enable_in;
302
303 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
304 dd->pdata->dma_start;
305
306 omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
307
308 }
309
310 static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
311 {
312 omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
313 omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
314
315 omap_aes_dma_trigger_omap2(dd, length);
316 }
317
318 static void omap_aes_dma_stop(struct omap_aes_dev *dd)
319 {
320 u32 mask;
321
322 mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
323 dd->pdata->dma_start;
324
325 omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
326 }
327
328 static struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_ctx *ctx)
329 {
330 struct omap_aes_dev *dd = NULL, *tmp;
331
332 spin_lock_bh(&list_lock);
333 if (!ctx->dd) {
334 list_for_each_entry(tmp, &dev_list, list) {
335 /* FIXME: take fist available aes core */
336 dd = tmp;
337 break;
338 }
339 ctx->dd = dd;
340 } else {
341 /* already found before */
342 dd = ctx->dd;
343 }
344 spin_unlock_bh(&list_lock);
345
346 return dd;
347 }
348
349 static void omap_aes_dma_out_callback(void *data)
350 {
351 struct omap_aes_dev *dd = data;
352
353 /* dma_lch_out - completed */
354 tasklet_schedule(&dd->done_task);
355 }
356
357 static int omap_aes_dma_init(struct omap_aes_dev *dd)
358 {
359 int err = -ENOMEM;
360 dma_cap_mask_t mask;
361
362 dd->dma_lch_out = NULL;
363 dd->dma_lch_in = NULL;
364
365 dma_cap_zero(mask);
366 dma_cap_set(DMA_SLAVE, mask);
367
368 dd->dma_lch_in = dma_request_slave_channel_compat(mask,
369 omap_dma_filter_fn,
370 &dd->dma_in,
371 dd->dev, "rx");
372 if (!dd->dma_lch_in) {
373 dev_err(dd->dev, "Unable to request in DMA channel\n");
374 goto err_dma_in;
375 }
376
377 dd->dma_lch_out = dma_request_slave_channel_compat(mask,
378 omap_dma_filter_fn,
379 &dd->dma_out,
380 dd->dev, "tx");
381 if (!dd->dma_lch_out) {
382 dev_err(dd->dev, "Unable to request out DMA channel\n");
383 goto err_dma_out;
384 }
385
386 return 0;
387
388 err_dma_out:
389 dma_release_channel(dd->dma_lch_in);
390 err_dma_in:
391 if (err)
392 pr_err("error: %d\n", err);
393 return err;
394 }
395
396 static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
397 {
398 dma_release_channel(dd->dma_lch_out);
399 dma_release_channel(dd->dma_lch_in);
400 }
401
402 static void sg_copy_buf(void *buf, struct scatterlist *sg,
403 unsigned int start, unsigned int nbytes, int out)
404 {
405 struct scatter_walk walk;
406
407 if (!nbytes)
408 return;
409
410 scatterwalk_start(&walk, sg);
411 scatterwalk_advance(&walk, start);
412 scatterwalk_copychunks(buf, &walk, nbytes, out);
413 scatterwalk_done(&walk, out, 0);
414 }
415
416 static int omap_aes_crypt_dma(struct crypto_tfm *tfm,
417 struct scatterlist *in_sg, struct scatterlist *out_sg,
418 int in_sg_len, int out_sg_len)
419 {
420 struct omap_aes_ctx *ctx = crypto_tfm_ctx(tfm);
421 struct omap_aes_dev *dd = ctx->dd;
422 struct dma_async_tx_descriptor *tx_in, *tx_out;
423 struct dma_slave_config cfg;
424 int ret;
425
426 if (dd->pio_only) {
427 scatterwalk_start(&dd->in_walk, dd->in_sg);
428 scatterwalk_start(&dd->out_walk, dd->out_sg);
429
430 /* Enable DATAIN interrupt and let it take
431 care of the rest */
432 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
433 return 0;
434 }
435
436 dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
437
438 memset(&cfg, 0, sizeof(cfg));
439
440 cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
441 cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
442 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
443 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
444 cfg.src_maxburst = DST_MAXBURST;
445 cfg.dst_maxburst = DST_MAXBURST;
446
447 /* IN */
448 ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
449 if (ret) {
450 dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
451 ret);
452 return ret;
453 }
454
455 tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
456 DMA_MEM_TO_DEV,
457 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
458 if (!tx_in) {
459 dev_err(dd->dev, "IN prep_slave_sg() failed\n");
460 return -EINVAL;
461 }
462
463 /* No callback necessary */
464 tx_in->callback_param = dd;
465
466 /* OUT */
467 ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
468 if (ret) {
469 dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
470 ret);
471 return ret;
472 }
473
474 tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
475 DMA_DEV_TO_MEM,
476 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
477 if (!tx_out) {
478 dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
479 return -EINVAL;
480 }
481
482 tx_out->callback = omap_aes_dma_out_callback;
483 tx_out->callback_param = dd;
484
485 dmaengine_submit(tx_in);
486 dmaengine_submit(tx_out);
487
488 dma_async_issue_pending(dd->dma_lch_in);
489 dma_async_issue_pending(dd->dma_lch_out);
490
491 /* start DMA */
492 dd->pdata->trigger(dd, dd->total);
493
494 return 0;
495 }
496
497 static int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
498 {
499 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(
500 crypto_ablkcipher_reqtfm(dd->req));
501 int err;
502
503 pr_debug("total: %d\n", dd->total);
504
505 if (!dd->pio_only) {
506 err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
507 DMA_TO_DEVICE);
508 if (!err) {
509 dev_err(dd->dev, "dma_map_sg() error\n");
510 return -EINVAL;
511 }
512
513 err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
514 DMA_FROM_DEVICE);
515 if (!err) {
516 dev_err(dd->dev, "dma_map_sg() error\n");
517 return -EINVAL;
518 }
519 }
520
521 err = omap_aes_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
522 dd->out_sg_len);
523 if (err && !dd->pio_only) {
524 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
525 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
526 DMA_FROM_DEVICE);
527 }
528
529 return err;
530 }
531
532 static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
533 {
534 struct ablkcipher_request *req = dd->req;
535
536 pr_debug("err: %d\n", err);
537
538 dd->flags &= ~FLAGS_BUSY;
539
540 req->base.complete(&req->base, err);
541 }
542
543 static int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
544 {
545 int err = 0;
546
547 pr_debug("total: %d\n", dd->total);
548
549 omap_aes_dma_stop(dd);
550
551 dmaengine_terminate_all(dd->dma_lch_in);
552 dmaengine_terminate_all(dd->dma_lch_out);
553
554 return err;
555 }
556
557 static int omap_aes_check_aligned(struct scatterlist *sg, int total)
558 {
559 int len = 0;
560
561 while (sg) {
562 if (!IS_ALIGNED(sg->offset, 4))
563 return -1;
564 if (!IS_ALIGNED(sg->length, AES_BLOCK_SIZE))
565 return -1;
566
567 len += sg->length;
568 sg = sg_next(sg);
569 }
570
571 if (len != total)
572 return -1;
573
574 return 0;
575 }
576
577 static int omap_aes_copy_sgs(struct omap_aes_dev *dd)
578 {
579 void *buf_in, *buf_out;
580 int pages;
581
582 pages = get_order(dd->total);
583
584 buf_in = (void *)__get_free_pages(GFP_ATOMIC, pages);
585 buf_out = (void *)__get_free_pages(GFP_ATOMIC, pages);
586
587 if (!buf_in || !buf_out) {
588 pr_err("Couldn't allocated pages for unaligned cases.\n");
589 return -1;
590 }
591
592 dd->orig_out = dd->out_sg;
593
594 sg_copy_buf(buf_in, dd->in_sg, 0, dd->total, 0);
595
596 sg_init_table(&dd->in_sgl, 1);
597 sg_set_buf(&dd->in_sgl, buf_in, dd->total);
598 dd->in_sg = &dd->in_sgl;
599
600 sg_init_table(&dd->out_sgl, 1);
601 sg_set_buf(&dd->out_sgl, buf_out, dd->total);
602 dd->out_sg = &dd->out_sgl;
603
604 return 0;
605 }
606
607 static int omap_aes_handle_queue(struct omap_aes_dev *dd,
608 struct ablkcipher_request *req)
609 {
610 struct crypto_async_request *async_req, *backlog;
611 struct omap_aes_ctx *ctx;
612 struct omap_aes_reqctx *rctx;
613 unsigned long flags;
614 int err, ret = 0;
615
616 spin_lock_irqsave(&dd->lock, flags);
617 if (req)
618 ret = ablkcipher_enqueue_request(&dd->queue, req);
619 if (dd->flags & FLAGS_BUSY) {
620 spin_unlock_irqrestore(&dd->lock, flags);
621 return ret;
622 }
623 backlog = crypto_get_backlog(&dd->queue);
624 async_req = crypto_dequeue_request(&dd->queue);
625 if (async_req)
626 dd->flags |= FLAGS_BUSY;
627 spin_unlock_irqrestore(&dd->lock, flags);
628
629 if (!async_req)
630 return ret;
631
632 if (backlog)
633 backlog->complete(backlog, -EINPROGRESS);
634
635 req = ablkcipher_request_cast(async_req);
636
637 /* assign new request to device */
638 dd->req = req;
639 dd->total = req->nbytes;
640 dd->total_save = req->nbytes;
641 dd->in_sg = req->src;
642 dd->out_sg = req->dst;
643
644 if (omap_aes_check_aligned(dd->in_sg, dd->total) ||
645 omap_aes_check_aligned(dd->out_sg, dd->total)) {
646 if (omap_aes_copy_sgs(dd))
647 pr_err("Failed to copy SGs for unaligned cases\n");
648 dd->sgs_copied = 1;
649 } else {
650 dd->sgs_copied = 0;
651 }
652
653 dd->in_sg_len = scatterwalk_bytes_sglen(dd->in_sg, dd->total);
654 dd->out_sg_len = scatterwalk_bytes_sglen(dd->out_sg, dd->total);
655 BUG_ON(dd->in_sg_len < 0 || dd->out_sg_len < 0);
656
657 rctx = ablkcipher_request_ctx(req);
658 ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
659 rctx->mode &= FLAGS_MODE_MASK;
660 dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
661
662 dd->ctx = ctx;
663 ctx->dd = dd;
664
665 err = omap_aes_write_ctrl(dd);
666 if (!err)
667 err = omap_aes_crypt_dma_start(dd);
668 if (err) {
669 /* aes_task will not finish it, so do it here */
670 omap_aes_finish_req(dd, err);
671 tasklet_schedule(&dd->queue_task);
672 }
673
674 return ret; /* return ret, which is enqueue return value */
675 }
676
677 static void omap_aes_done_task(unsigned long data)
678 {
679 struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
680 void *buf_in, *buf_out;
681 int pages;
682
683 pr_debug("enter done_task\n");
684
685 if (!dd->pio_only) {
686 dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
687 DMA_FROM_DEVICE);
688 dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
689 dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
690 DMA_FROM_DEVICE);
691 omap_aes_crypt_dma_stop(dd);
692 }
693
694 if (dd->sgs_copied) {
695 buf_in = sg_virt(&dd->in_sgl);
696 buf_out = sg_virt(&dd->out_sgl);
697
698 sg_copy_buf(buf_out, dd->orig_out, 0, dd->total_save, 1);
699
700 pages = get_order(dd->total_save);
701 free_pages((unsigned long)buf_in, pages);
702 free_pages((unsigned long)buf_out, pages);
703 }
704
705 omap_aes_finish_req(dd, 0);
706 omap_aes_handle_queue(dd, NULL);
707
708 pr_debug("exit\n");
709 }
710
711 static void omap_aes_queue_task(unsigned long data)
712 {
713 struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
714
715 omap_aes_handle_queue(dd, NULL);
716 }
717
718 static int omap_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
719 {
720 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(
721 crypto_ablkcipher_reqtfm(req));
722 struct omap_aes_reqctx *rctx = ablkcipher_request_ctx(req);
723 struct omap_aes_dev *dd;
724
725 pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->nbytes,
726 !!(mode & FLAGS_ENCRYPT),
727 !!(mode & FLAGS_CBC));
728
729 if (!IS_ALIGNED(req->nbytes, AES_BLOCK_SIZE)) {
730 pr_err("request size is not exact amount of AES blocks\n");
731 return -EINVAL;
732 }
733
734 dd = omap_aes_find_dev(ctx);
735 if (!dd)
736 return -ENODEV;
737
738 rctx->mode = mode;
739
740 return omap_aes_handle_queue(dd, req);
741 }
742
743 /* ********************** ALG API ************************************ */
744
745 static int omap_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
746 unsigned int keylen)
747 {
748 struct omap_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
749
750 if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
751 keylen != AES_KEYSIZE_256)
752 return -EINVAL;
753
754 pr_debug("enter, keylen: %d\n", keylen);
755
756 memcpy(ctx->key, key, keylen);
757 ctx->keylen = keylen;
758
759 return 0;
760 }
761
762 static int omap_aes_ecb_encrypt(struct ablkcipher_request *req)
763 {
764 return omap_aes_crypt(req, FLAGS_ENCRYPT);
765 }
766
767 static int omap_aes_ecb_decrypt(struct ablkcipher_request *req)
768 {
769 return omap_aes_crypt(req, 0);
770 }
771
772 static int omap_aes_cbc_encrypt(struct ablkcipher_request *req)
773 {
774 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
775 }
776
777 static int omap_aes_cbc_decrypt(struct ablkcipher_request *req)
778 {
779 return omap_aes_crypt(req, FLAGS_CBC);
780 }
781
782 static int omap_aes_ctr_encrypt(struct ablkcipher_request *req)
783 {
784 return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
785 }
786
787 static int omap_aes_ctr_decrypt(struct ablkcipher_request *req)
788 {
789 return omap_aes_crypt(req, FLAGS_CTR);
790 }
791
792 static int omap_aes_cra_init(struct crypto_tfm *tfm)
793 {
794 struct omap_aes_dev *dd = NULL;
795 int err;
796
797 /* Find AES device, currently picks the first device */
798 spin_lock_bh(&list_lock);
799 list_for_each_entry(dd, &dev_list, list) {
800 break;
801 }
802 spin_unlock_bh(&list_lock);
803
804 err = pm_runtime_get_sync(dd->dev);
805 if (err < 0) {
806 dev_err(dd->dev, "%s: failed to get_sync(%d)\n",
807 __func__, err);
808 return err;
809 }
810
811 tfm->crt_ablkcipher.reqsize = sizeof(struct omap_aes_reqctx);
812
813 return 0;
814 }
815
816 static void omap_aes_cra_exit(struct crypto_tfm *tfm)
817 {
818 struct omap_aes_dev *dd = NULL;
819
820 /* Find AES device, currently picks the first device */
821 spin_lock_bh(&list_lock);
822 list_for_each_entry(dd, &dev_list, list) {
823 break;
824 }
825 spin_unlock_bh(&list_lock);
826
827 pm_runtime_put_sync(dd->dev);
828 }
829
830 /* ********************** ALGS ************************************ */
831
832 static struct crypto_alg algs_ecb_cbc[] = {
833 {
834 .cra_name = "ecb(aes)",
835 .cra_driver_name = "ecb-aes-omap",
836 .cra_priority = 100,
837 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
838 CRYPTO_ALG_KERN_DRIVER_ONLY |
839 CRYPTO_ALG_ASYNC,
840 .cra_blocksize = AES_BLOCK_SIZE,
841 .cra_ctxsize = sizeof(struct omap_aes_ctx),
842 .cra_alignmask = 0,
843 .cra_type = &crypto_ablkcipher_type,
844 .cra_module = THIS_MODULE,
845 .cra_init = omap_aes_cra_init,
846 .cra_exit = omap_aes_cra_exit,
847 .cra_u.ablkcipher = {
848 .min_keysize = AES_MIN_KEY_SIZE,
849 .max_keysize = AES_MAX_KEY_SIZE,
850 .setkey = omap_aes_setkey,
851 .encrypt = omap_aes_ecb_encrypt,
852 .decrypt = omap_aes_ecb_decrypt,
853 }
854 },
855 {
856 .cra_name = "cbc(aes)",
857 .cra_driver_name = "cbc-aes-omap",
858 .cra_priority = 100,
859 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
860 CRYPTO_ALG_KERN_DRIVER_ONLY |
861 CRYPTO_ALG_ASYNC,
862 .cra_blocksize = AES_BLOCK_SIZE,
863 .cra_ctxsize = sizeof(struct omap_aes_ctx),
864 .cra_alignmask = 0,
865 .cra_type = &crypto_ablkcipher_type,
866 .cra_module = THIS_MODULE,
867 .cra_init = omap_aes_cra_init,
868 .cra_exit = omap_aes_cra_exit,
869 .cra_u.ablkcipher = {
870 .min_keysize = AES_MIN_KEY_SIZE,
871 .max_keysize = AES_MAX_KEY_SIZE,
872 .ivsize = AES_BLOCK_SIZE,
873 .setkey = omap_aes_setkey,
874 .encrypt = omap_aes_cbc_encrypt,
875 .decrypt = omap_aes_cbc_decrypt,
876 }
877 }
878 };
879
880 static struct crypto_alg algs_ctr[] = {
881 {
882 .cra_name = "ctr(aes)",
883 .cra_driver_name = "ctr-aes-omap",
884 .cra_priority = 100,
885 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
886 CRYPTO_ALG_KERN_DRIVER_ONLY |
887 CRYPTO_ALG_ASYNC,
888 .cra_blocksize = AES_BLOCK_SIZE,
889 .cra_ctxsize = sizeof(struct omap_aes_ctx),
890 .cra_alignmask = 0,
891 .cra_type = &crypto_ablkcipher_type,
892 .cra_module = THIS_MODULE,
893 .cra_init = omap_aes_cra_init,
894 .cra_exit = omap_aes_cra_exit,
895 .cra_u.ablkcipher = {
896 .min_keysize = AES_MIN_KEY_SIZE,
897 .max_keysize = AES_MAX_KEY_SIZE,
898 .geniv = "eseqiv",
899 .ivsize = AES_BLOCK_SIZE,
900 .setkey = omap_aes_setkey,
901 .encrypt = omap_aes_ctr_encrypt,
902 .decrypt = omap_aes_ctr_decrypt,
903 }
904 } ,
905 };
906
907 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
908 {
909 .algs_list = algs_ecb_cbc,
910 .size = ARRAY_SIZE(algs_ecb_cbc),
911 },
912 };
913
914 static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
915 .algs_info = omap_aes_algs_info_ecb_cbc,
916 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
917 .trigger = omap_aes_dma_trigger_omap2,
918 .key_ofs = 0x1c,
919 .iv_ofs = 0x20,
920 .ctrl_ofs = 0x30,
921 .data_ofs = 0x34,
922 .rev_ofs = 0x44,
923 .mask_ofs = 0x48,
924 .dma_enable_in = BIT(2),
925 .dma_enable_out = BIT(3),
926 .dma_start = BIT(5),
927 .major_mask = 0xf0,
928 .major_shift = 4,
929 .minor_mask = 0x0f,
930 .minor_shift = 0,
931 };
932
933 #ifdef CONFIG_OF
934 static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
935 {
936 .algs_list = algs_ecb_cbc,
937 .size = ARRAY_SIZE(algs_ecb_cbc),
938 },
939 {
940 .algs_list = algs_ctr,
941 .size = ARRAY_SIZE(algs_ctr),
942 },
943 };
944
945 static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
946 .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
947 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
948 .trigger = omap_aes_dma_trigger_omap2,
949 .key_ofs = 0x1c,
950 .iv_ofs = 0x20,
951 .ctrl_ofs = 0x30,
952 .data_ofs = 0x34,
953 .rev_ofs = 0x44,
954 .mask_ofs = 0x48,
955 .dma_enable_in = BIT(2),
956 .dma_enable_out = BIT(3),
957 .dma_start = BIT(5),
958 .major_mask = 0xf0,
959 .major_shift = 4,
960 .minor_mask = 0x0f,
961 .minor_shift = 0,
962 };
963
964 static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
965 .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
966 .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
967 .trigger = omap_aes_dma_trigger_omap4,
968 .key_ofs = 0x3c,
969 .iv_ofs = 0x40,
970 .ctrl_ofs = 0x50,
971 .data_ofs = 0x60,
972 .rev_ofs = 0x80,
973 .mask_ofs = 0x84,
974 .irq_status_ofs = 0x8c,
975 .irq_enable_ofs = 0x90,
976 .dma_enable_in = BIT(5),
977 .dma_enable_out = BIT(6),
978 .major_mask = 0x0700,
979 .major_shift = 8,
980 .minor_mask = 0x003f,
981 .minor_shift = 0,
982 };
983
984 static irqreturn_t omap_aes_irq(int irq, void *dev_id)
985 {
986 struct omap_aes_dev *dd = dev_id;
987 u32 status, i;
988 u32 *src, *dst;
989
990 status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd));
991 if (status & AES_REG_IRQ_DATA_IN) {
992 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
993
994 BUG_ON(!dd->in_sg);
995
996 BUG_ON(_calc_walked(in) > dd->in_sg->length);
997
998 src = sg_virt(dd->in_sg) + _calc_walked(in);
999
1000 for (i = 0; i < AES_BLOCK_WORDS; i++) {
1001 omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src);
1002
1003 scatterwalk_advance(&dd->in_walk, 4);
1004 if (dd->in_sg->length == _calc_walked(in)) {
1005 dd->in_sg = sg_next(dd->in_sg);
1006 if (dd->in_sg) {
1007 scatterwalk_start(&dd->in_walk,
1008 dd->in_sg);
1009 src = sg_virt(dd->in_sg) +
1010 _calc_walked(in);
1011 }
1012 } else {
1013 src++;
1014 }
1015 }
1016
1017 /* Clear IRQ status */
1018 status &= ~AES_REG_IRQ_DATA_IN;
1019 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
1020
1021 /* Enable DATA_OUT interrupt */
1022 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4);
1023
1024 } else if (status & AES_REG_IRQ_DATA_OUT) {
1025 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
1026
1027 BUG_ON(!dd->out_sg);
1028
1029 BUG_ON(_calc_walked(out) > dd->out_sg->length);
1030
1031 dst = sg_virt(dd->out_sg) + _calc_walked(out);
1032
1033 for (i = 0; i < AES_BLOCK_WORDS; i++) {
1034 *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i));
1035 scatterwalk_advance(&dd->out_walk, 4);
1036 if (dd->out_sg->length == _calc_walked(out)) {
1037 dd->out_sg = sg_next(dd->out_sg);
1038 if (dd->out_sg) {
1039 scatterwalk_start(&dd->out_walk,
1040 dd->out_sg);
1041 dst = sg_virt(dd->out_sg) +
1042 _calc_walked(out);
1043 }
1044 } else {
1045 dst++;
1046 }
1047 }
1048
1049 dd->total -= AES_BLOCK_SIZE;
1050
1051 BUG_ON(dd->total < 0);
1052
1053 /* Clear IRQ status */
1054 status &= ~AES_REG_IRQ_DATA_OUT;
1055 omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
1056
1057 if (!dd->total)
1058 /* All bytes read! */
1059 tasklet_schedule(&dd->done_task);
1060 else
1061 /* Enable DATA_IN interrupt for next block */
1062 omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
1063 }
1064
1065 return IRQ_HANDLED;
1066 }
1067
1068 static const struct of_device_id omap_aes_of_match[] = {
1069 {
1070 .compatible = "ti,omap2-aes",
1071 .data = &omap_aes_pdata_omap2,
1072 },
1073 {
1074 .compatible = "ti,omap3-aes",
1075 .data = &omap_aes_pdata_omap3,
1076 },
1077 {
1078 .compatible = "ti,omap4-aes",
1079 .data = &omap_aes_pdata_omap4,
1080 },
1081 {},
1082 };
1083 MODULE_DEVICE_TABLE(of, omap_aes_of_match);
1084
1085 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1086 struct device *dev, struct resource *res)
1087 {
1088 struct device_node *node = dev->of_node;
1089 const struct of_device_id *match;
1090 int err = 0;
1091
1092 match = of_match_device(of_match_ptr(omap_aes_of_match), dev);
1093 if (!match) {
1094 dev_err(dev, "no compatible OF match\n");
1095 err = -EINVAL;
1096 goto err;
1097 }
1098
1099 err = of_address_to_resource(node, 0, res);
1100 if (err < 0) {
1101 dev_err(dev, "can't translate OF node address\n");
1102 err = -EINVAL;
1103 goto err;
1104 }
1105
1106 dd->dma_out = -1; /* Dummy value that's unused */
1107 dd->dma_in = -1; /* Dummy value that's unused */
1108
1109 dd->pdata = match->data;
1110
1111 err:
1112 return err;
1113 }
1114 #else
1115 static const struct of_device_id omap_aes_of_match[] = {
1116 {},
1117 };
1118
1119 static int omap_aes_get_res_of(struct omap_aes_dev *dd,
1120 struct device *dev, struct resource *res)
1121 {
1122 return -EINVAL;
1123 }
1124 #endif
1125
1126 static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
1127 struct platform_device *pdev, struct resource *res)
1128 {
1129 struct device *dev = &pdev->dev;
1130 struct resource *r;
1131 int err = 0;
1132
1133 /* Get the base address */
1134 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1135 if (!r) {
1136 dev_err(dev, "no MEM resource info\n");
1137 err = -ENODEV;
1138 goto err;
1139 }
1140 memcpy(res, r, sizeof(*res));
1141
1142 /* Get the DMA out channel */
1143 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1144 if (!r) {
1145 dev_err(dev, "no DMA out resource info\n");
1146 err = -ENODEV;
1147 goto err;
1148 }
1149 dd->dma_out = r->start;
1150
1151 /* Get the DMA in channel */
1152 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1153 if (!r) {
1154 dev_err(dev, "no DMA in resource info\n");
1155 err = -ENODEV;
1156 goto err;
1157 }
1158 dd->dma_in = r->start;
1159
1160 /* Only OMAP2/3 can be non-DT */
1161 dd->pdata = &omap_aes_pdata_omap2;
1162
1163 err:
1164 return err;
1165 }
1166
1167 static int omap_aes_probe(struct platform_device *pdev)
1168 {
1169 struct device *dev = &pdev->dev;
1170 struct omap_aes_dev *dd;
1171 struct crypto_alg *algp;
1172 struct resource res;
1173 int err = -ENOMEM, i, j, irq = -1;
1174 u32 reg;
1175
1176 dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL);
1177 if (dd == NULL) {
1178 dev_err(dev, "unable to alloc data struct.\n");
1179 goto err_data;
1180 }
1181 dd->dev = dev;
1182 platform_set_drvdata(pdev, dd);
1183
1184 spin_lock_init(&dd->lock);
1185 crypto_init_queue(&dd->queue, OMAP_AES_QUEUE_LENGTH);
1186
1187 err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
1188 omap_aes_get_res_pdev(dd, pdev, &res);
1189 if (err)
1190 goto err_res;
1191
1192 dd->io_base = devm_ioremap_resource(dev, &res);
1193 if (IS_ERR(dd->io_base)) {
1194 err = PTR_ERR(dd->io_base);
1195 goto err_res;
1196 }
1197 dd->phys_base = res.start;
1198
1199 pm_runtime_enable(dev);
1200 err = pm_runtime_get_sync(dev);
1201 if (err < 0) {
1202 dev_err(dev, "%s: failed to get_sync(%d)\n",
1203 __func__, err);
1204 goto err_res;
1205 }
1206
1207 omap_aes_dma_stop(dd);
1208
1209 reg = omap_aes_read(dd, AES_REG_REV(dd));
1210
1211 pm_runtime_put_sync(dev);
1212
1213 dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
1214 (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
1215 (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
1216
1217 tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
1218 tasklet_init(&dd->queue_task, omap_aes_queue_task, (unsigned long)dd);
1219
1220 err = omap_aes_dma_init(dd);
1221 if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) {
1222 dd->pio_only = 1;
1223
1224 irq = platform_get_irq(pdev, 0);
1225 if (irq < 0) {
1226 dev_err(dev, "can't get IRQ resource\n");
1227 goto err_irq;
1228 }
1229
1230 err = devm_request_irq(dev, irq, omap_aes_irq, 0,
1231 dev_name(dev), dd);
1232 if (err) {
1233 dev_err(dev, "Unable to grab omap-aes IRQ\n");
1234 goto err_irq;
1235 }
1236 }
1237
1238
1239 INIT_LIST_HEAD(&dd->list);
1240 spin_lock(&list_lock);
1241 list_add_tail(&dd->list, &dev_list);
1242 spin_unlock(&list_lock);
1243
1244 for (i = 0; i < dd->pdata->algs_info_size; i++) {
1245 for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
1246 algp = &dd->pdata->algs_info[i].algs_list[j];
1247
1248 pr_debug("reg alg: %s\n", algp->cra_name);
1249 INIT_LIST_HEAD(&algp->cra_list);
1250
1251 err = crypto_register_alg(algp);
1252 if (err)
1253 goto err_algs;
1254
1255 dd->pdata->algs_info[i].registered++;
1256 }
1257 }
1258
1259 return 0;
1260 err_algs:
1261 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1262 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1263 crypto_unregister_alg(
1264 &dd->pdata->algs_info[i].algs_list[j]);
1265 if (!dd->pio_only)
1266 omap_aes_dma_cleanup(dd);
1267 err_irq:
1268 tasklet_kill(&dd->done_task);
1269 tasklet_kill(&dd->queue_task);
1270 pm_runtime_disable(dev);
1271 err_res:
1272 dd = NULL;
1273 err_data:
1274 dev_err(dev, "initialization failed.\n");
1275 return err;
1276 }
1277
1278 static int omap_aes_remove(struct platform_device *pdev)
1279 {
1280 struct omap_aes_dev *dd = platform_get_drvdata(pdev);
1281 int i, j;
1282
1283 if (!dd)
1284 return -ENODEV;
1285
1286 spin_lock(&list_lock);
1287 list_del(&dd->list);
1288 spin_unlock(&list_lock);
1289
1290 for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
1291 for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
1292 crypto_unregister_alg(
1293 &dd->pdata->algs_info[i].algs_list[j]);
1294
1295 tasklet_kill(&dd->done_task);
1296 tasklet_kill(&dd->queue_task);
1297 omap_aes_dma_cleanup(dd);
1298 pm_runtime_disable(dd->dev);
1299 dd = NULL;
1300
1301 return 0;
1302 }
1303
1304 #ifdef CONFIG_PM_SLEEP
1305 static int omap_aes_suspend(struct device *dev)
1306 {
1307 pm_runtime_put_sync(dev);
1308 return 0;
1309 }
1310
1311 static int omap_aes_resume(struct device *dev)
1312 {
1313 pm_runtime_get_sync(dev);
1314 return 0;
1315 }
1316 #endif
1317
1318 static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume);
1319
1320 static struct platform_driver omap_aes_driver = {
1321 .probe = omap_aes_probe,
1322 .remove = omap_aes_remove,
1323 .driver = {
1324 .name = "omap-aes",
1325 .pm = &omap_aes_pm_ops,
1326 .of_match_table = omap_aes_of_match,
1327 },
1328 };
1329
1330 module_platform_driver(omap_aes_driver);
1331
1332 MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
1333 MODULE_LICENSE("GPL v2");
1334 MODULE_AUTHOR("Dmitry Kasatkin");
1335
Linux kernel - Deliverables
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