2 * Freescale SEC (talitos) device register and descriptor header defines
4 * Copyright (c) 2006-2010 Freescale Semiconductor, Inc.
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32 * TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
35 /* global register offset addresses */
36 #define TALITOS_MCR 0x1030 /* master control register */
37 #define TALITOS_MCR_LO 0x1038
38 #define TALITOS_MCR_SWR 0x1 /* s/w reset */
39 #define TALITOS_IMR 0x1008 /* interrupt mask register */
40 #define TALITOS_IMR_INIT 0x100ff /* enable channel IRQs */
41 #define TALITOS_IMR_DONE 0x00055 /* done IRQs */
42 #define TALITOS_IMR_LO 0x100C
43 #define TALITOS_IMR_LO_INIT 0x20000 /* allow RNGU error IRQs */
44 #define TALITOS_ISR 0x1010 /* interrupt status register */
45 #define TALITOS_ISR_CHERR 0xaa /* channel errors mask */
46 #define TALITOS_ISR_CHDONE 0x55 /* channel done mask */
47 #define TALITOS_ISR_LO 0x1014
48 #define TALITOS_ICR 0x1018 /* interrupt clear register */
49 #define TALITOS_ICR_LO 0x101C
51 /* channel register address stride */
52 #define TALITOS_CH_STRIDE 0x100
54 /* channel configuration register */
55 #define TALITOS_CCCR(ch) (ch * TALITOS_CH_STRIDE + 0x1108)
56 #define TALITOS_CCCR_CONT 0x2 /* channel continue */
57 #define TALITOS_CCCR_RESET 0x1 /* channel reset */
58 #define TALITOS_CCCR_LO(ch) (ch * TALITOS_CH_STRIDE + 0x110c)
59 #define TALITOS_CCCR_LO_IWSE 0x80 /* chan. ICCR writeback enab. */
60 #define TALITOS_CCCR_LO_EAE 0x20 /* extended address enable */
61 #define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */
62 #define TALITOS_CCCR_LO_NT 0x4 /* notification type */
63 #define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */
65 /* CCPSR: channel pointer status register */
66 #define TALITOS_CCPSR(ch) (ch * TALITOS_CH_STRIDE + 0x1110)
67 #define TALITOS_CCPSR_LO(ch) (ch * TALITOS_CH_STRIDE + 0x1114)
68 #define TALITOS_CCPSR_LO_DOF 0x8000 /* double FF write oflow error */
69 #define TALITOS_CCPSR_LO_SOF 0x4000 /* single FF write oflow error */
70 #define TALITOS_CCPSR_LO_MDTE 0x2000 /* master data transfer error */
71 #define TALITOS_CCPSR_LO_SGDLZ 0x1000 /* s/g data len zero error */
72 #define TALITOS_CCPSR_LO_FPZ 0x0800 /* fetch ptr zero error */
73 #define TALITOS_CCPSR_LO_IDH 0x0400 /* illegal desc hdr error */
74 #define TALITOS_CCPSR_LO_IEU 0x0200 /* invalid EU error */
75 #define TALITOS_CCPSR_LO_EU 0x0100 /* EU error detected */
76 #define TALITOS_CCPSR_LO_GB 0x0080 /* gather boundary error */
77 #define TALITOS_CCPSR_LO_GRL 0x0040 /* gather return/length error */
78 #define TALITOS_CCPSR_LO_SB 0x0020 /* scatter boundary error */
79 #define TALITOS_CCPSR_LO_SRL 0x0010 /* scatter return/length error */
81 /* channel fetch fifo register */
82 #define TALITOS_FF(ch) (ch * TALITOS_CH_STRIDE + 0x1148)
83 #define TALITOS_FF_LO(ch) (ch * TALITOS_CH_STRIDE + 0x114c)
85 /* current descriptor pointer register */
86 #define TALITOS_CDPR(ch) (ch * TALITOS_CH_STRIDE + 0x1140)
87 #define TALITOS_CDPR_LO(ch) (ch * TALITOS_CH_STRIDE + 0x1144)
89 /* descriptor buffer register */
90 #define TALITOS_DESCBUF(ch) (ch * TALITOS_CH_STRIDE + 0x1180)
91 #define TALITOS_DESCBUF_LO(ch) (ch * TALITOS_CH_STRIDE + 0x1184)
93 /* gather link table */
94 #define TALITOS_GATHER(ch) (ch * TALITOS_CH_STRIDE + 0x11c0)
95 #define TALITOS_GATHER_LO(ch) (ch * TALITOS_CH_STRIDE + 0x11c4)
97 /* scatter link table */
98 #define TALITOS_SCATTER(ch) (ch * TALITOS_CH_STRIDE + 0x11e0)
99 #define TALITOS_SCATTER_LO(ch) (ch * TALITOS_CH_STRIDE + 0x11e4)
101 /* execution unit interrupt status registers */
102 #define TALITOS_DEUISR 0x2030 /* DES unit */
103 #define TALITOS_DEUISR_LO 0x2034
104 #define TALITOS_AESUISR 0x4030 /* AES unit */
105 #define TALITOS_AESUISR_LO 0x4034
106 #define TALITOS_MDEUISR 0x6030 /* message digest unit */
107 #define TALITOS_MDEUISR_LO 0x6034
108 #define TALITOS_MDEUICR 0x6038 /* interrupt control */
109 #define TALITOS_MDEUICR_LO 0x603c
110 #define TALITOS_MDEUICR_LO_ICE 0x4000 /* integrity check IRQ enable */
111 #define TALITOS_AFEUISR 0x8030 /* arc4 unit */
112 #define TALITOS_AFEUISR_LO 0x8034
113 #define TALITOS_RNGUISR 0xa030 /* random number unit */
114 #define TALITOS_RNGUISR_LO 0xa034
115 #define TALITOS_RNGUSR 0xa028 /* rng status */
116 #define TALITOS_RNGUSR_LO 0xa02c
117 #define TALITOS_RNGUSR_LO_RD 0x1 /* reset done */
118 #define TALITOS_RNGUSR_LO_OFL 0xff0000/* output FIFO length */
119 #define TALITOS_RNGUDSR 0xa010 /* data size */
120 #define TALITOS_RNGUDSR_LO 0xa014
121 #define TALITOS_RNGU_FIFO 0xa800 /* output FIFO */
122 #define TALITOS_RNGU_FIFO_LO 0xa804 /* output FIFO */
123 #define TALITOS_RNGURCR 0xa018 /* reset control */
124 #define TALITOS_RNGURCR_LO 0xa01c
125 #define TALITOS_RNGURCR_LO_SR 0x1 /* software reset */
126 #define TALITOS_PKEUISR 0xc030 /* public key unit */
127 #define TALITOS_PKEUISR_LO 0xc034
128 #define TALITOS_KEUISR 0xe030 /* kasumi unit */
129 #define TALITOS_KEUISR_LO 0xe034
130 #define TALITOS_CRCUISR 0xf030 /* cyclic redundancy check unit*/
131 #define TALITOS_CRCUISR_LO 0xf034
133 #define TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 0x28
134 #define TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512 0x48
137 * talitos descriptor header (hdr) bits
140 /* written back when done */
141 #define DESC_HDR_DONE cpu_to_be32(0xff000000)
142 #define DESC_HDR_LO_ICCR1_MASK cpu_to_be32(0x00180000)
143 #define DESC_HDR_LO_ICCR1_PASS cpu_to_be32(0x00080000)
144 #define DESC_HDR_LO_ICCR1_FAIL cpu_to_be32(0x00100000)
146 /* primary execution unit select */
147 #define DESC_HDR_SEL0_MASK cpu_to_be32(0xf0000000)
148 #define DESC_HDR_SEL0_AFEU cpu_to_be32(0x10000000)
149 #define DESC_HDR_SEL0_DEU cpu_to_be32(0x20000000)
150 #define DESC_HDR_SEL0_MDEUA cpu_to_be32(0x30000000)
151 #define DESC_HDR_SEL0_MDEUB cpu_to_be32(0xb0000000)
152 #define DESC_HDR_SEL0_RNG cpu_to_be32(0x40000000)
153 #define DESC_HDR_SEL0_PKEU cpu_to_be32(0x50000000)
154 #define DESC_HDR_SEL0_AESU cpu_to_be32(0x60000000)
155 #define DESC_HDR_SEL0_KEU cpu_to_be32(0x70000000)
156 #define DESC_HDR_SEL0_CRCU cpu_to_be32(0x80000000)
158 /* primary execution unit mode (MODE0) and derivatives */
159 #define DESC_HDR_MODE0_ENCRYPT cpu_to_be32(0x00100000)
160 #define DESC_HDR_MODE0_AESU_CBC cpu_to_be32(0x00200000)
161 #define DESC_HDR_MODE0_DEU_CBC cpu_to_be32(0x00400000)
162 #define DESC_HDR_MODE0_DEU_3DES cpu_to_be32(0x00200000)
163 #define DESC_HDR_MODE0_MDEU_CONT cpu_to_be32(0x08000000)
164 #define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000)
165 #define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000)
166 #define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000)
167 #define DESC_HDR_MODE0_MDEU_SHA224 cpu_to_be32(0x00300000)
168 #define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000)
169 #define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000)
170 #define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000)
171 #define DESC_HDR_MODE0_MDEUB_SHA384 cpu_to_be32(0x00000000)
172 #define DESC_HDR_MODE0_MDEUB_SHA512 cpu_to_be32(0x00200000)
173 #define DESC_HDR_MODE0_MDEU_MD5_HMAC (DESC_HDR_MODE0_MDEU_MD5 | \
174 DESC_HDR_MODE0_MDEU_HMAC)
175 #define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \
176 DESC_HDR_MODE0_MDEU_HMAC)
177 #define DESC_HDR_MODE0_MDEU_SHA1_HMAC (DESC_HDR_MODE0_MDEU_SHA1 | \
178 DESC_HDR_MODE0_MDEU_HMAC)
180 /* secondary execution unit select (SEL1) */
181 #define DESC_HDR_SEL1_MASK cpu_to_be32(0x000f0000)
182 #define DESC_HDR_SEL1_MDEUA cpu_to_be32(0x00030000)
183 #define DESC_HDR_SEL1_MDEUB cpu_to_be32(0x000b0000)
184 #define DESC_HDR_SEL1_CRCU cpu_to_be32(0x00080000)
186 /* secondary execution unit mode (MODE1) and derivatives */
187 #define DESC_HDR_MODE1_MDEU_CICV cpu_to_be32(0x00004000)
188 #define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000)
189 #define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800)
190 #define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400)
191 #define DESC_HDR_MODE1_MDEU_SHA224 cpu_to_be32(0x00000300)
192 #define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200)
193 #define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100)
194 #define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000)
195 #define DESC_HDR_MODE1_MDEUB_SHA384 cpu_to_be32(0x00000000)
196 #define DESC_HDR_MODE1_MDEUB_SHA512 cpu_to_be32(0x00000200)
197 #define DESC_HDR_MODE1_MDEU_MD5_HMAC (DESC_HDR_MODE1_MDEU_MD5 | \
198 DESC_HDR_MODE1_MDEU_HMAC)
199 #define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \
200 DESC_HDR_MODE1_MDEU_HMAC)
201 #define DESC_HDR_MODE1_MDEU_SHA1_HMAC (DESC_HDR_MODE1_MDEU_SHA1 | \
202 DESC_HDR_MODE1_MDEU_HMAC)
204 /* direction of overall data flow (DIR) */
205 #define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002)
207 /* request done notification (DN) */
208 #define DESC_HDR_DONE_NOTIFY cpu_to_be32(0x00000001)
210 /* descriptor types */
211 #define DESC_HDR_TYPE_AESU_CTR_NONSNOOP cpu_to_be32(0 << 3)
212 #define DESC_HDR_TYPE_IPSEC_ESP cpu_to_be32(1 << 3)
213 #define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU cpu_to_be32(2 << 3)
214 #define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU cpu_to_be32(4 << 3)
216 /* link table extent field bits */
217 #define DESC_PTR_LNKTBL_JUMP 0x80
218 #define DESC_PTR_LNKTBL_RETURN 0x02
219 #define DESC_PTR_LNKTBL_NEXT 0x01
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