2 * Driver for the Atmel Extensible DMA Controller (aka XDMAC on AT91 systems)
4 * Copyright (C) 2014 Atmel Corporation
6 * Author: Ludovic Desroches <ludovic.desroches@atmel.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <asm/barrier.h>
22 #include <dt-bindings/dma/at91.h>
23 #include <linux/clk.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dmapool.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
28 #include <linux/kernel.h>
29 #include <linux/list.h>
30 #include <linux/module.h>
31 #include <linux/of_dma.h>
32 #include <linux/of_platform.h>
33 #include <linux/platform_device.h>
36 #include "dmaengine.h"
38 /* Global registers */
39 #define AT_XDMAC_GTYPE 0x00 /* Global Type Register */
40 #define AT_XDMAC_NB_CH(i) (((i) & 0x1F) + 1) /* Number of Channels Minus One */
41 #define AT_XDMAC_FIFO_SZ(i) (((i) >> 5) & 0x7FF) /* Number of Bytes */
42 #define AT_XDMAC_NB_REQ(i) ((((i) >> 16) & 0x3F) + 1) /* Number of Peripheral Requests Minus One */
43 #define AT_XDMAC_GCFG 0x04 /* Global Configuration Register */
44 #define AT_XDMAC_GWAC 0x08 /* Global Weighted Arbiter Configuration Register */
45 #define AT_XDMAC_GIE 0x0C /* Global Interrupt Enable Register */
46 #define AT_XDMAC_GID 0x10 /* Global Interrupt Disable Register */
47 #define AT_XDMAC_GIM 0x14 /* Global Interrupt Mask Register */
48 #define AT_XDMAC_GIS 0x18 /* Global Interrupt Status Register */
49 #define AT_XDMAC_GE 0x1C /* Global Channel Enable Register */
50 #define AT_XDMAC_GD 0x20 /* Global Channel Disable Register */
51 #define AT_XDMAC_GS 0x24 /* Global Channel Status Register */
52 #define AT_XDMAC_GRS 0x28 /* Global Channel Read Suspend Register */
53 #define AT_XDMAC_GWS 0x2C /* Global Write Suspend Register */
54 #define AT_XDMAC_GRWS 0x30 /* Global Channel Read Write Suspend Register */
55 #define AT_XDMAC_GRWR 0x34 /* Global Channel Read Write Resume Register */
56 #define AT_XDMAC_GSWR 0x38 /* Global Channel Software Request Register */
57 #define AT_XDMAC_GSWS 0x3C /* Global channel Software Request Status Register */
58 #define AT_XDMAC_GSWF 0x40 /* Global Channel Software Flush Request Register */
59 #define AT_XDMAC_VERSION 0xFFC /* XDMAC Version Register */
61 /* Channel relative registers offsets */
62 #define AT_XDMAC_CIE 0x00 /* Channel Interrupt Enable Register */
63 #define AT_XDMAC_CIE_BIE BIT(0) /* End of Block Interrupt Enable Bit */
64 #define AT_XDMAC_CIE_LIE BIT(1) /* End of Linked List Interrupt Enable Bit */
65 #define AT_XDMAC_CIE_DIE BIT(2) /* End of Disable Interrupt Enable Bit */
66 #define AT_XDMAC_CIE_FIE BIT(3) /* End of Flush Interrupt Enable Bit */
67 #define AT_XDMAC_CIE_RBEIE BIT(4) /* Read Bus Error Interrupt Enable Bit */
68 #define AT_XDMAC_CIE_WBEIE BIT(5) /* Write Bus Error Interrupt Enable Bit */
69 #define AT_XDMAC_CIE_ROIE BIT(6) /* Request Overflow Interrupt Enable Bit */
70 #define AT_XDMAC_CID 0x04 /* Channel Interrupt Disable Register */
71 #define AT_XDMAC_CID_BID BIT(0) /* End of Block Interrupt Disable Bit */
72 #define AT_XDMAC_CID_LID BIT(1) /* End of Linked List Interrupt Disable Bit */
73 #define AT_XDMAC_CID_DID BIT(2) /* End of Disable Interrupt Disable Bit */
74 #define AT_XDMAC_CID_FID BIT(3) /* End of Flush Interrupt Disable Bit */
75 #define AT_XDMAC_CID_RBEID BIT(4) /* Read Bus Error Interrupt Disable Bit */
76 #define AT_XDMAC_CID_WBEID BIT(5) /* Write Bus Error Interrupt Disable Bit */
77 #define AT_XDMAC_CID_ROID BIT(6) /* Request Overflow Interrupt Disable Bit */
78 #define AT_XDMAC_CIM 0x08 /* Channel Interrupt Mask Register */
79 #define AT_XDMAC_CIM_BIM BIT(0) /* End of Block Interrupt Mask Bit */
80 #define AT_XDMAC_CIM_LIM BIT(1) /* End of Linked List Interrupt Mask Bit */
81 #define AT_XDMAC_CIM_DIM BIT(2) /* End of Disable Interrupt Mask Bit */
82 #define AT_XDMAC_CIM_FIM BIT(3) /* End of Flush Interrupt Mask Bit */
83 #define AT_XDMAC_CIM_RBEIM BIT(4) /* Read Bus Error Interrupt Mask Bit */
84 #define AT_XDMAC_CIM_WBEIM BIT(5) /* Write Bus Error Interrupt Mask Bit */
85 #define AT_XDMAC_CIM_ROIM BIT(6) /* Request Overflow Interrupt Mask Bit */
86 #define AT_XDMAC_CIS 0x0C /* Channel Interrupt Status Register */
87 #define AT_XDMAC_CIS_BIS BIT(0) /* End of Block Interrupt Status Bit */
88 #define AT_XDMAC_CIS_LIS BIT(1) /* End of Linked List Interrupt Status Bit */
89 #define AT_XDMAC_CIS_DIS BIT(2) /* End of Disable Interrupt Status Bit */
90 #define AT_XDMAC_CIS_FIS BIT(3) /* End of Flush Interrupt Status Bit */
91 #define AT_XDMAC_CIS_RBEIS BIT(4) /* Read Bus Error Interrupt Status Bit */
92 #define AT_XDMAC_CIS_WBEIS BIT(5) /* Write Bus Error Interrupt Status Bit */
93 #define AT_XDMAC_CIS_ROIS BIT(6) /* Request Overflow Interrupt Status Bit */
94 #define AT_XDMAC_CSA 0x10 /* Channel Source Address Register */
95 #define AT_XDMAC_CDA 0x14 /* Channel Destination Address Register */
96 #define AT_XDMAC_CNDA 0x18 /* Channel Next Descriptor Address Register */
97 #define AT_XDMAC_CNDA_NDAIF(i) ((i) & 0x1) /* Channel x Next Descriptor Interface */
98 #define AT_XDMAC_CNDA_NDA(i) ((i) & 0xfffffffc) /* Channel x Next Descriptor Address */
99 #define AT_XDMAC_CNDC 0x1C /* Channel Next Descriptor Control Register */
100 #define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */
101 #define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */
102 #define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */
103 #define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */
104 #define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */
105 #define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */
106 #define AT_XDMAC_CNDC_NDVIEW_NDV3 (0x3 << 3) /* Channel x Next Descriptor View 3 */
107 #define AT_XDMAC_CUBC 0x20 /* Channel Microblock Control Register */
108 #define AT_XDMAC_CBC 0x24 /* Channel Block Control Register */
109 #define AT_XDMAC_CC 0x28 /* Channel Configuration Register */
110 #define AT_XDMAC_CC_TYPE (0x1 << 0) /* Channel Transfer Type */
111 #define AT_XDMAC_CC_TYPE_MEM_TRAN (0x0 << 0) /* Memory to Memory Transfer */
112 #define AT_XDMAC_CC_TYPE_PER_TRAN (0x1 << 0) /* Peripheral to Memory or Memory to Peripheral Transfer */
113 #define AT_XDMAC_CC_MBSIZE_MASK (0x3 << 1)
114 #define AT_XDMAC_CC_MBSIZE_SINGLE (0x0 << 1)
115 #define AT_XDMAC_CC_MBSIZE_FOUR (0x1 << 1)
116 #define AT_XDMAC_CC_MBSIZE_EIGHT (0x2 << 1)
117 #define AT_XDMAC_CC_MBSIZE_SIXTEEN (0x3 << 1)
118 #define AT_XDMAC_CC_DSYNC (0x1 << 4) /* Channel Synchronization */
119 #define AT_XDMAC_CC_DSYNC_PER2MEM (0x0 << 4)
120 #define AT_XDMAC_CC_DSYNC_MEM2PER (0x1 << 4)
121 #define AT_XDMAC_CC_PROT (0x1 << 5) /* Channel Protection */
122 #define AT_XDMAC_CC_PROT_SEC (0x0 << 5)
123 #define AT_XDMAC_CC_PROT_UNSEC (0x1 << 5)
124 #define AT_XDMAC_CC_SWREQ (0x1 << 6) /* Channel Software Request Trigger */
125 #define AT_XDMAC_CC_SWREQ_HWR_CONNECTED (0x0 << 6)
126 #define AT_XDMAC_CC_SWREQ_SWR_CONNECTED (0x1 << 6)
127 #define AT_XDMAC_CC_MEMSET (0x1 << 7) /* Channel Fill Block of memory */
128 #define AT_XDMAC_CC_MEMSET_NORMAL_MODE (0x0 << 7)
129 #define AT_XDMAC_CC_MEMSET_HW_MODE (0x1 << 7)
130 #define AT_XDMAC_CC_CSIZE(i) ((0x7 & (i)) << 8) /* Channel Chunk Size */
131 #define AT_XDMAC_CC_DWIDTH_OFFSET 11
132 #define AT_XDMAC_CC_DWIDTH_MASK (0x3 << AT_XDMAC_CC_DWIDTH_OFFSET)
133 #define AT_XDMAC_CC_DWIDTH(i) ((0x3 & (i)) << AT_XDMAC_CC_DWIDTH_OFFSET) /* Channel Data Width */
134 #define AT_XDMAC_CC_DWIDTH_BYTE 0x0
135 #define AT_XDMAC_CC_DWIDTH_HALFWORD 0x1
136 #define AT_XDMAC_CC_DWIDTH_WORD 0x2
137 #define AT_XDMAC_CC_DWIDTH_DWORD 0x3
138 #define AT_XDMAC_CC_SIF(i) ((0x1 & (i)) << 13) /* Channel Source Interface Identifier */
139 #define AT_XDMAC_CC_DIF(i) ((0x1 & (i)) << 14) /* Channel Destination Interface Identifier */
140 #define AT_XDMAC_CC_SAM_MASK (0x3 << 16) /* Channel Source Addressing Mode */
141 #define AT_XDMAC_CC_SAM_FIXED_AM (0x0 << 16)
142 #define AT_XDMAC_CC_SAM_INCREMENTED_AM (0x1 << 16)
143 #define AT_XDMAC_CC_SAM_UBS_AM (0x2 << 16)
144 #define AT_XDMAC_CC_SAM_UBS_DS_AM (0x3 << 16)
145 #define AT_XDMAC_CC_DAM_MASK (0x3 << 18) /* Channel Source Addressing Mode */
146 #define AT_XDMAC_CC_DAM_FIXED_AM (0x0 << 18)
147 #define AT_XDMAC_CC_DAM_INCREMENTED_AM (0x1 << 18)
148 #define AT_XDMAC_CC_DAM_UBS_AM (0x2 << 18)
149 #define AT_XDMAC_CC_DAM_UBS_DS_AM (0x3 << 18)
150 #define AT_XDMAC_CC_INITD (0x1 << 21) /* Channel Initialization Terminated (read only) */
151 #define AT_XDMAC_CC_INITD_TERMINATED (0x0 << 21)
152 #define AT_XDMAC_CC_INITD_IN_PROGRESS (0x1 << 21)
153 #define AT_XDMAC_CC_RDIP (0x1 << 22) /* Read in Progress (read only) */
154 #define AT_XDMAC_CC_RDIP_DONE (0x0 << 22)
155 #define AT_XDMAC_CC_RDIP_IN_PROGRESS (0x1 << 22)
156 #define AT_XDMAC_CC_WRIP (0x1 << 23) /* Write in Progress (read only) */
157 #define AT_XDMAC_CC_WRIP_DONE (0x0 << 23)
158 #define AT_XDMAC_CC_WRIP_IN_PROGRESS (0x1 << 23)
159 #define AT_XDMAC_CC_PERID(i) (0x7f & (i) << 24) /* Channel Peripheral Identifier */
160 #define AT_XDMAC_CDS_MSP 0x2C /* Channel Data Stride Memory Set Pattern */
161 #define AT_XDMAC_CSUS 0x30 /* Channel Source Microblock Stride */
162 #define AT_XDMAC_CDUS 0x34 /* Channel Destination Microblock Stride */
164 #define AT_XDMAC_CHAN_REG_BASE 0x50 /* Channel registers base address */
166 /* Microblock control members */
167 #define AT_XDMAC_MBR_UBC_UBLEN_MAX 0xFFFFFFUL /* Maximum Microblock Length */
168 #define AT_XDMAC_MBR_UBC_NDE (0x1 << 24) /* Next Descriptor Enable */
169 #define AT_XDMAC_MBR_UBC_NSEN (0x1 << 25) /* Next Descriptor Source Update */
170 #define AT_XDMAC_MBR_UBC_NDEN (0x1 << 26) /* Next Descriptor Destination Update */
171 #define AT_XDMAC_MBR_UBC_NDV0 (0x0 << 27) /* Next Descriptor View 0 */
172 #define AT_XDMAC_MBR_UBC_NDV1 (0x1 << 27) /* Next Descriptor View 1 */
173 #define AT_XDMAC_MBR_UBC_NDV2 (0x2 << 27) /* Next Descriptor View 2 */
174 #define AT_XDMAC_MBR_UBC_NDV3 (0x3 << 27) /* Next Descriptor View 3 */
176 #define AT_XDMAC_MAX_CHAN 0x20
177 #define AT_XDMAC_MAX_CSIZE 16 /* 16 data */
178 #define AT_XDMAC_MAX_DWIDTH 8 /* 64 bits */
180 #define AT_XDMAC_DMA_BUSWIDTHS\
181 (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\
182 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\
183 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
184 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |\
185 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES))
188 AT_XDMAC_CHAN_IS_CYCLIC
= 0,
189 AT_XDMAC_CHAN_IS_PAUSED
,
192 /* ----- Channels ----- */
193 struct at_xdmac_chan
{
194 struct dma_chan chan
;
195 void __iomem
*ch_regs
;
196 u32 mask
; /* Channel Mask */
197 u32 cfg
; /* Channel Configuration Register */
198 u8 perid
; /* Peripheral ID */
199 u8 perif
; /* Peripheral Interface */
200 u8 memif
; /* Memory Interface */
205 unsigned long status
;
206 struct tasklet_struct tasklet
;
207 struct dma_slave_config sconfig
;
211 struct list_head xfers_list
;
212 struct list_head free_descs_list
;
216 /* ----- Controller ----- */
218 struct dma_device dma
;
224 struct dma_pool
*at_xdmac_desc_pool
;
225 struct at_xdmac_chan chan
[0];
229 /* ----- Descriptors ----- */
231 /* Linked List Descriptor */
232 struct at_xdmac_lld
{
233 dma_addr_t mbr_nda
; /* Next Descriptor Member */
234 u32 mbr_ubc
; /* Microblock Control Member */
235 dma_addr_t mbr_sa
; /* Source Address Member */
236 dma_addr_t mbr_da
; /* Destination Address Member */
237 u32 mbr_cfg
; /* Configuration Register */
238 u32 mbr_bc
; /* Block Control Register */
239 u32 mbr_ds
; /* Data Stride Register */
240 u32 mbr_sus
; /* Source Microblock Stride Register */
241 u32 mbr_dus
; /* Destination Microblock Stride Register */
245 struct at_xdmac_desc
{
246 struct at_xdmac_lld lld
;
247 enum dma_transfer_direction direction
;
248 struct dma_async_tx_descriptor tx_dma_desc
;
249 struct list_head desc_node
;
250 /* Following members are only used by the first descriptor */
252 unsigned int xfer_size
;
253 struct list_head descs_list
;
254 struct list_head xfer_node
;
257 static inline void __iomem
*at_xdmac_chan_reg_base(struct at_xdmac
*atxdmac
, unsigned int chan_nb
)
259 return atxdmac
->regs
+ (AT_XDMAC_CHAN_REG_BASE
+ chan_nb
* 0x40);
262 #define at_xdmac_read(atxdmac, reg) readl_relaxed((atxdmac)->regs + (reg))
263 #define at_xdmac_write(atxdmac, reg, value) \
264 writel_relaxed((value), (atxdmac)->regs + (reg))
266 #define at_xdmac_chan_read(atchan, reg) readl_relaxed((atchan)->ch_regs + (reg))
267 #define at_xdmac_chan_write(atchan, reg, value) writel_relaxed((value), (atchan)->ch_regs + (reg))
269 static inline struct at_xdmac_chan
*to_at_xdmac_chan(struct dma_chan
*dchan
)
271 return container_of(dchan
, struct at_xdmac_chan
, chan
);
274 static struct device
*chan2dev(struct dma_chan
*chan
)
276 return &chan
->dev
->device
;
279 static inline struct at_xdmac
*to_at_xdmac(struct dma_device
*ddev
)
281 return container_of(ddev
, struct at_xdmac
, dma
);
284 static inline struct at_xdmac_desc
*txd_to_at_desc(struct dma_async_tx_descriptor
*txd
)
286 return container_of(txd
, struct at_xdmac_desc
, tx_dma_desc
);
289 static inline int at_xdmac_chan_is_cyclic(struct at_xdmac_chan
*atchan
)
291 return test_bit(AT_XDMAC_CHAN_IS_CYCLIC
, &atchan
->status
);
294 static inline int at_xdmac_chan_is_paused(struct at_xdmac_chan
*atchan
)
296 return test_bit(AT_XDMAC_CHAN_IS_PAUSED
, &atchan
->status
);
299 static inline int at_xdmac_csize(u32 maxburst
)
303 csize
= ffs(maxburst
) - 1;
310 static inline u8
at_xdmac_get_dwidth(u32 cfg
)
312 return (cfg
& AT_XDMAC_CC_DWIDTH_MASK
) >> AT_XDMAC_CC_DWIDTH_OFFSET
;
315 static unsigned int init_nr_desc_per_channel
= 64;
316 module_param(init_nr_desc_per_channel
, uint
, 0644);
317 MODULE_PARM_DESC(init_nr_desc_per_channel
,
318 "initial descriptors per channel (default: 64)");
321 static bool at_xdmac_chan_is_enabled(struct at_xdmac_chan
*atchan
)
323 return at_xdmac_chan_read(atchan
, AT_XDMAC_GS
) & atchan
->mask
;
326 static void at_xdmac_off(struct at_xdmac
*atxdmac
)
328 at_xdmac_write(atxdmac
, AT_XDMAC_GD
, -1L);
330 /* Wait that all chans are disabled. */
331 while (at_xdmac_read(atxdmac
, AT_XDMAC_GS
))
334 at_xdmac_write(atxdmac
, AT_XDMAC_GID
, -1L);
337 /* Call with lock hold. */
338 static void at_xdmac_start_xfer(struct at_xdmac_chan
*atchan
,
339 struct at_xdmac_desc
*first
)
341 struct at_xdmac
*atxdmac
= to_at_xdmac(atchan
->chan
.device
);
344 dev_vdbg(chan2dev(&atchan
->chan
), "%s: desc 0x%p\n", __func__
, first
);
346 if (at_xdmac_chan_is_enabled(atchan
))
349 /* Set transfer as active to not try to start it again. */
350 first
->active_xfer
= true;
352 /* Tell xdmac where to get the first descriptor. */
353 reg
= AT_XDMAC_CNDA_NDA(first
->tx_dma_desc
.phys
)
354 | AT_XDMAC_CNDA_NDAIF(atchan
->memif
);
355 at_xdmac_chan_write(atchan
, AT_XDMAC_CNDA
, reg
);
358 * When doing non cyclic transfer we need to use the next
359 * descriptor view 2 since some fields of the configuration register
360 * depend on transfer size and src/dest addresses.
362 if (at_xdmac_chan_is_cyclic(atchan
))
363 reg
= AT_XDMAC_CNDC_NDVIEW_NDV1
;
364 else if (first
->lld
.mbr_ubc
& AT_XDMAC_MBR_UBC_NDV3
)
365 reg
= AT_XDMAC_CNDC_NDVIEW_NDV3
;
367 reg
= AT_XDMAC_CNDC_NDVIEW_NDV2
;
369 * Even if the register will be updated from the configuration in the
370 * descriptor when using view 2 or higher, the PROT bit won't be set
371 * properly. This bit can be modified only by using the channel
372 * configuration register.
374 at_xdmac_chan_write(atchan
, AT_XDMAC_CC
, first
->lld
.mbr_cfg
);
376 reg
|= AT_XDMAC_CNDC_NDDUP
377 | AT_XDMAC_CNDC_NDSUP
379 at_xdmac_chan_write(atchan
, AT_XDMAC_CNDC
, reg
);
381 dev_vdbg(chan2dev(&atchan
->chan
),
382 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
383 __func__
, at_xdmac_chan_read(atchan
, AT_XDMAC_CC
),
384 at_xdmac_chan_read(atchan
, AT_XDMAC_CNDA
),
385 at_xdmac_chan_read(atchan
, AT_XDMAC_CNDC
),
386 at_xdmac_chan_read(atchan
, AT_XDMAC_CSA
),
387 at_xdmac_chan_read(atchan
, AT_XDMAC_CDA
),
388 at_xdmac_chan_read(atchan
, AT_XDMAC_CUBC
));
390 at_xdmac_chan_write(atchan
, AT_XDMAC_CID
, 0xffffffff);
391 reg
= AT_XDMAC_CIE_RBEIE
| AT_XDMAC_CIE_WBEIE
| AT_XDMAC_CIE_ROIE
;
393 * There is no end of list when doing cyclic dma, we need to get
394 * an interrupt after each periods.
396 if (at_xdmac_chan_is_cyclic(atchan
))
397 at_xdmac_chan_write(atchan
, AT_XDMAC_CIE
,
398 reg
| AT_XDMAC_CIE_BIE
);
400 at_xdmac_chan_write(atchan
, AT_XDMAC_CIE
,
401 reg
| AT_XDMAC_CIE_LIE
);
402 at_xdmac_write(atxdmac
, AT_XDMAC_GIE
, atchan
->mask
);
403 dev_vdbg(chan2dev(&atchan
->chan
),
404 "%s: enable channel (0x%08x)\n", __func__
, atchan
->mask
);
406 at_xdmac_write(atxdmac
, AT_XDMAC_GE
, atchan
->mask
);
408 dev_vdbg(chan2dev(&atchan
->chan
),
409 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
410 __func__
, at_xdmac_chan_read(atchan
, AT_XDMAC_CC
),
411 at_xdmac_chan_read(atchan
, AT_XDMAC_CNDA
),
412 at_xdmac_chan_read(atchan
, AT_XDMAC_CNDC
),
413 at_xdmac_chan_read(atchan
, AT_XDMAC_CSA
),
414 at_xdmac_chan_read(atchan
, AT_XDMAC_CDA
),
415 at_xdmac_chan_read(atchan
, AT_XDMAC_CUBC
));
419 static dma_cookie_t
at_xdmac_tx_submit(struct dma_async_tx_descriptor
*tx
)
421 struct at_xdmac_desc
*desc
= txd_to_at_desc(tx
);
422 struct at_xdmac_chan
*atchan
= to_at_xdmac_chan(tx
->chan
);
424 unsigned long irqflags
;
426 spin_lock_irqsave(&atchan
->lock
, irqflags
);
427 cookie
= dma_cookie_assign(tx
);
429 dev_vdbg(chan2dev(tx
->chan
), "%s: atchan 0x%p, add desc 0x%p to xfers_list\n",
430 __func__
, atchan
, desc
);
431 list_add_tail(&desc
->xfer_node
, &atchan
->xfers_list
);
432 if (list_is_singular(&atchan
->xfers_list
))
433 at_xdmac_start_xfer(atchan
, desc
);
435 spin_unlock_irqrestore(&atchan
->lock
, irqflags
);
439 static struct at_xdmac_desc
*at_xdmac_alloc_desc(struct dma_chan
*chan
,
442 struct at_xdmac_desc
*desc
;
443 struct at_xdmac
*atxdmac
= to_at_xdmac(chan
->device
);
446 desc
= dma_pool_alloc(atxdmac
->at_xdmac_desc_pool
, gfp_flags
, &phys
);
448 memset(desc
, 0, sizeof(*desc
));
449 INIT_LIST_HEAD(&desc
->descs_list
);
450 dma_async_tx_descriptor_init(&desc
->tx_dma_desc
, chan
);
451 desc
->tx_dma_desc
.tx_submit
= at_xdmac_tx_submit
;
452 desc
->tx_dma_desc
.phys
= phys
;
458 void at_xdmac_init_used_desc(struct at_xdmac_desc
*desc
)
460 memset(&desc
->lld
, 0, sizeof(desc
->lld
));
461 INIT_LIST_HEAD(&desc
->descs_list
);
462 desc
->direction
= DMA_TRANS_NONE
;
464 desc
->active_xfer
= false;
467 /* Call must be protected by lock. */
468 static struct at_xdmac_desc
*at_xdmac_get_desc(struct at_xdmac_chan
*atchan
)
470 struct at_xdmac_desc
*desc
;
472 if (list_empty(&atchan
->free_descs_list
)) {
473 desc
= at_xdmac_alloc_desc(&atchan
->chan
, GFP_NOWAIT
);
475 desc
= list_first_entry(&atchan
->free_descs_list
,
476 struct at_xdmac_desc
, desc_node
);
477 list_del(&desc
->desc_node
);
478 at_xdmac_init_used_desc(desc
);
484 static void at_xdmac_queue_desc(struct dma_chan
*chan
,
485 struct at_xdmac_desc
*prev
,
486 struct at_xdmac_desc
*desc
)
491 prev
->lld
.mbr_nda
= desc
->tx_dma_desc
.phys
;
492 prev
->lld
.mbr_ubc
|= AT_XDMAC_MBR_UBC_NDE
;
494 dev_dbg(chan2dev(chan
), "%s: chain lld: prev=0x%p, mbr_nda=%pad\n",
495 __func__
, prev
, &prev
->lld
.mbr_nda
);
498 static inline void at_xdmac_increment_block_count(struct dma_chan
*chan
,
499 struct at_xdmac_desc
*desc
)
506 dev_dbg(chan2dev(chan
),
507 "%s: incrementing the block count of the desc 0x%p\n",
511 static struct dma_chan
*at_xdmac_xlate(struct of_phandle_args
*dma_spec
,
512 struct of_dma
*of_dma
)
514 struct at_xdmac
*atxdmac
= of_dma
->of_dma_data
;
515 struct at_xdmac_chan
*atchan
;
516 struct dma_chan
*chan
;
517 struct device
*dev
= atxdmac
->dma
.dev
;
519 if (dma_spec
->args_count
!= 1) {
520 dev_err(dev
, "dma phandler args: bad number of args\n");
524 chan
= dma_get_any_slave_channel(&atxdmac
->dma
);
526 dev_err(dev
, "can't get a dma channel\n");
530 atchan
= to_at_xdmac_chan(chan
);
531 atchan
->memif
= AT91_XDMAC_DT_GET_MEM_IF(dma_spec
->args
[0]);
532 atchan
->perif
= AT91_XDMAC_DT_GET_PER_IF(dma_spec
->args
[0]);
533 atchan
->perid
= AT91_XDMAC_DT_GET_PERID(dma_spec
->args
[0]);
534 dev_dbg(dev
, "chan dt cfg: memif=%u perif=%u perid=%u\n",
535 atchan
->memif
, atchan
->perif
, atchan
->perid
);
540 static int at_xdmac_compute_chan_conf(struct dma_chan
*chan
,
541 enum dma_transfer_direction direction
)
543 struct at_xdmac_chan
*atchan
= to_at_xdmac_chan(chan
);
546 if (direction
== DMA_DEV_TO_MEM
) {
548 AT91_XDMAC_DT_PERID(atchan
->perid
)
549 | AT_XDMAC_CC_DAM_INCREMENTED_AM
550 | AT_XDMAC_CC_SAM_FIXED_AM
551 | AT_XDMAC_CC_DIF(atchan
->memif
)
552 | AT_XDMAC_CC_SIF(atchan
->perif
)
553 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
554 | AT_XDMAC_CC_DSYNC_PER2MEM
555 | AT_XDMAC_CC_MBSIZE_SIXTEEN
556 | AT_XDMAC_CC_TYPE_PER_TRAN
;
557 csize
= ffs(atchan
->sconfig
.src_maxburst
) - 1;
559 dev_err(chan2dev(chan
), "invalid src maxburst value\n");
562 atchan
->cfg
|= AT_XDMAC_CC_CSIZE(csize
);
563 dwidth
= ffs(atchan
->sconfig
.src_addr_width
) - 1;
565 dev_err(chan2dev(chan
), "invalid src addr width value\n");
568 atchan
->cfg
|= AT_XDMAC_CC_DWIDTH(dwidth
);
569 } else if (direction
== DMA_MEM_TO_DEV
) {
571 AT91_XDMAC_DT_PERID(atchan
->perid
)
572 | AT_XDMAC_CC_DAM_FIXED_AM
573 | AT_XDMAC_CC_SAM_INCREMENTED_AM
574 | AT_XDMAC_CC_DIF(atchan
->perif
)
575 | AT_XDMAC_CC_SIF(atchan
->memif
)
576 | AT_XDMAC_CC_SWREQ_HWR_CONNECTED
577 | AT_XDMAC_CC_DSYNC_MEM2PER
578 | AT_XDMAC_CC_MBSIZE_SIXTEEN
579 | AT_XDMAC_CC_TYPE_PER_TRAN
;
580 csize
= ffs(atchan
->sconfig
.dst_maxburst
) - 1;
582 dev_err(chan2dev(chan
), "invalid src maxburst value\n");
585 atchan
->cfg
|= AT_XDMAC_CC_CSIZE(csize
);
586 dwidth
= ffs(atchan
->sconfig
.dst_addr_width
) - 1;
588 dev_err(chan2dev(chan
), "invalid dst addr width value\n");
591 atchan
->cfg
|= AT_XDMAC_CC_DWIDTH(dwidth
);
594 dev_dbg(chan2dev(chan
), "%s: cfg=0x%08x\n", __func__
, atchan
->cfg
);
600 * Only check that maxburst and addr width values are supported by the
601 * the controller but not that the configuration is good to perform the
602 * transfer since we don't know the direction at this stage.
604 static int at_xdmac_check_slave_config(struct dma_slave_config
*sconfig
)
606 if ((sconfig
->src_maxburst
> AT_XDMAC_MAX_CSIZE
)
607 || (sconfig
->dst_maxburst
> AT_XDMAC_MAX_CSIZE
))
610 if ((sconfig
->src_addr_width
> AT_XDMAC_MAX_DWIDTH
)
611 || (sconfig
->dst_addr_width
> AT_XDMAC_MAX_DWIDTH
))
617 static int at_xdmac_set_slave_config(struct dma_chan
*chan
,
618 struct dma_slave_config
*sconfig
)
620 struct at_xdmac_chan
*atchan
= to_at_xdmac_chan(chan
);
622 if (at_xdmac_check_slave_config(sconfig
)) {
623 dev_err(chan2dev(chan
), "invalid slave configuration\n");
627 memcpy(&atchan
->sconfig
, sconfig
, sizeof(atchan
->sconfig
));
632 static struct dma_async_tx_descriptor
*
633 at_xdmac_prep_slave_sg(struct dma_chan
*chan
, struct scatterlist
*sgl
,
634 unsigned int sg_len
, enum dma_transfer_direction direction
,
635 unsigned long flags
, void *context
)
637 struct at_xdmac_chan
*atchan
= to_at_xdmac_chan(chan
);
638 struct at_xdmac_desc
*first
= NULL
, *prev
= NULL
;
639 struct scatterlist
*sg
;
641 unsigned int xfer_size
= 0;
642 unsigned long irqflags
;
643 struct dma_async_tx_descriptor
*ret
= NULL
;
648 if (!is_slave_direction(direction
)) {
649 dev_err(chan2dev(chan
), "invalid DMA direction\n");
653 dev_dbg(chan2dev(chan
), "%s: sg_len=%d, dir=%s, flags=0x%lx\n",
655 direction
== DMA_MEM_TO_DEV
? "to device" : "from device",
658 /* Protect dma_sconfig field that can be modified by set_slave_conf. */
659 spin_lock_irqsave(&atchan
->lock
, irqflags
);
661 if (at_xdmac_compute_chan_conf(chan
, direction
))
664 /* Prepare descriptors. */
665 for_each_sg(sgl
, sg
, sg_len
, i
) {
666 struct at_xdmac_desc
*desc
= NULL
;
667 u32 len
, mem
, dwidth
, fixed_dwidth
;
669 len
= sg_dma_len(sg
);
670 mem
= sg_dma_address(sg
);
671 if (unlikely(!len
)) {
672 dev_err(chan2dev(chan
), "sg data length is zero\n");
675 dev_dbg(chan2dev(chan
), "%s: * sg%d len=%u, mem=0x%08x\n",
676 __func__
, i
, len
, mem
);
678 desc
= at_xdmac_get_desc(atchan
);
680 dev_err(chan2dev(chan
), "can't get descriptor\n");
682 list_splice_init(&first
->descs_list
, &atchan
->free_descs_list
);
686 /* Linked list descriptor setup. */
687 if (direction
== DMA_DEV_TO_MEM
) {
688 desc
->lld
.mbr_sa
= atchan
->sconfig
.src_addr
;
689 desc
->lld
.mbr_da
= mem
;
691 desc
->lld
.mbr_sa
= mem
;
692 desc
->lld
.mbr_da
= atchan
->sconfig
.dst_addr
;
694 dwidth
= at_xdmac_get_dwidth(atchan
->cfg
);
695 fixed_dwidth
= IS_ALIGNED(len
, 1 << dwidth
)
697 : AT_XDMAC_CC_DWIDTH_BYTE
;
698 desc
->lld
.mbr_ubc
= AT_XDMAC_MBR_UBC_NDV2
/* next descriptor view */
699 | AT_XDMAC_MBR_UBC_NDEN
/* next descriptor dst parameter update */
700 | AT_XDMAC_MBR_UBC_NSEN
/* next descriptor src parameter update */
701 | (len
>> fixed_dwidth
); /* microblock length */
702 desc
->lld
.mbr_cfg
= (atchan
->cfg
& ~AT_XDMAC_CC_DWIDTH_MASK
) |
703 AT_XDMAC_CC_DWIDTH(fixed_dwidth
);
704 dev_dbg(chan2dev(chan
),
705 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
706 __func__
, &desc
->lld
.mbr_sa
, &desc
->lld
.mbr_da
, desc
->lld
.mbr_ubc
);
710 at_xdmac_queue_desc(chan
, prev
, desc
);
716 dev_dbg(chan2dev(chan
), "%s: add desc 0x%p to descs_list 0x%p\n",
717 __func__
, desc
, first
);
718 list_add_tail(&desc
->desc_node
, &first
->descs_list
);
723 first
->tx_dma_desc
.flags
= flags
;
724 first
->xfer_size
= xfer_size
;
725 first
->direction
= direction
;
726 ret
= &first
->tx_dma_desc
;
729 spin_unlock_irqrestore(&atchan
->lock
, irqflags
);
733 static struct dma_async_tx_descriptor
*
734 at_xdmac_prep_dma_cyclic(struct dma_chan
*chan
, dma_addr_t buf_addr
,
735 size_t buf_len
, size_t period_len
,
736 enum dma_transfer_direction direction
,
739 struct at_xdmac_chan
*atchan
= to_at_xdmac_chan(chan
);
740 struct at_xdmac_desc
*first
= NULL
, *prev
= NULL
;
741 unsigned int periods
= buf_len
/ period_len
;
743 unsigned long irqflags
;
745 dev_dbg(chan2dev(chan
), "%s: buf_addr=%pad, buf_len=%zd, period_len=%zd, dir=%s, flags=0x%lx\n",
746 __func__
, &buf_addr
, buf_len
, period_len
,
747 direction
== DMA_MEM_TO_DEV
? "mem2per" : "per2mem", flags
);
749 if (!is_slave_direction(direction
)) {
750 dev_err(chan2dev(chan
), "invalid DMA direction\n");
754 if (test_and_set_bit(AT_XDMAC_CHAN_IS_CYCLIC
, &atchan
->status
)) {
755 dev_err(chan2dev(chan
), "channel currently used\n");
759 if (at_xdmac_compute_chan_conf(chan
, direction
))
762 for (i
= 0; i
< periods
; i
++) {
763 struct at_xdmac_desc
*desc
= NULL
;
765 spin_lock_irqsave(&atchan
->lock
, irqflags
);
766 desc
= at_xdmac_get_desc(atchan
);
768 dev_err(chan2dev(chan
), "can't get descriptor\n");
770 list_splice_init(&first
->descs_list
, &atchan
->free_descs_list
);
771 spin_unlock_irqrestore(&atchan
->lock
, irqflags
);
774 spin_unlock_irqrestore(&atchan
->lock
, irqflags
);
775 dev_dbg(chan2dev(chan
),
776 "%s: desc=0x%p, tx_dma_desc.phys=%pad\n",
777 __func__
, desc
, &desc
->tx_dma_desc
.phys
);
779 if (direction
== DMA_DEV_TO_MEM
) {
780 desc
->lld
.mbr_sa
= atchan
->sconfig
.src_addr
;
781 desc
->lld
.mbr_da
= buf_addr
+ i
* period_len
;
783 desc
->lld
.mbr_sa
= buf_addr
+ i
* period_len
;
784 desc
->lld
.mbr_da
= atchan
->sconfig
.dst_addr
;
786 desc
->lld
.mbr_cfg
= atchan
->cfg
;
787 desc
->lld
.mbr_ubc
= AT_XDMAC_MBR_UBC_NDV1
788 | AT_XDMAC_MBR_UBC_NDEN
789 | AT_XDMAC_MBR_UBC_NSEN
790 | period_len
>> at_xdmac_get_dwidth(desc
->lld
.mbr_cfg
);
792 dev_dbg(chan2dev(chan
),
793 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x\n",
794 __func__
, &desc
->lld
.mbr_sa
, &desc
->lld
.mbr_da
, desc
->lld
.mbr_ubc
);
798 at_xdmac_queue_desc(chan
, prev
, desc
);
804 dev_dbg(chan2dev(chan
), "%s: add desc 0x%p to descs_list 0x%p\n",
805 __func__
, desc
, first
);
806 list_add_tail(&desc
->desc_node
, &first
->descs_list
);
809 at_xdmac_queue_desc(chan
, prev
, first
);
810 first
->tx_dma_desc
.flags
= flags
;
811 first
->xfer_size
= buf_len
;
812 first
->direction
= direction
;
814 return &first
->tx_dma_desc
;
817 static inline u32
at_xdmac_align_width(struct dma_chan
*chan
, dma_addr_t addr
)
822 * Check address alignment to select the greater data width we
825 * Some XDMAC implementations don't provide dword transfer, in
826 * this case selecting dword has the same behavior as
827 * selecting word transfers.
830 width
= AT_XDMAC_CC_DWIDTH_DWORD
;
831 dev_dbg(chan2dev(chan
), "%s: dwidth: double word\n", __func__
);
832 } else if (!(addr
& 3)) {
833 width
= AT_XDMAC_CC_DWIDTH_WORD
;
834 dev_dbg(chan2dev(chan
), "%s: dwidth: word\n", __func__
);
835 } else if (!(addr
& 1)) {
836 width
= AT_XDMAC_CC_DWIDTH_HALFWORD
;
837 dev_dbg(chan2dev(chan
), "%s: dwidth: half word\n", __func__
);
839 width
= AT_XDMAC_CC_DWIDTH_BYTE
;
840 dev_dbg(chan2dev(chan
), "%s: dwidth: byte\n", __func__
);
846 static struct at_xdmac_desc
*
847 at_xdmac_interleaved_queue_desc(struct dma_chan
*chan
,
848 struct at_xdmac_chan
*atchan
,
849 struct at_xdmac_desc
*prev
,
850 dma_addr_t src
, dma_addr_t dst
,
851 struct dma_interleaved_template
*xt
,
852 struct data_chunk
*chunk
)
854 struct at_xdmac_desc
*desc
;
859 * WARNING: The channel configuration is set here since there is no
860 * dmaengine_slave_config call in this case. Moreover we don't know the
861 * direction, it involves we can't dynamically set the source and dest
862 * interface so we have to use the same one. Only interface 0 allows EBI
863 * access. Hopefully we can access DDR through both ports (at least on
864 * SAMA5D4x), so we can use the same interface for source and dest,
865 * that solves the fact we don't know the direction.
866 * ERRATA: Even if useless for memory transfers, the PERID has to not
867 * match the one of another channel. If not, it could lead to spurious
870 u32 chan_cc
= AT_XDMAC_CC_PERID(0x3f)
873 | AT_XDMAC_CC_MBSIZE_SIXTEEN
874 | AT_XDMAC_CC_TYPE_MEM_TRAN
;
876 dwidth
= at_xdmac_align_width(chan
, src
| dst
| chunk
->size
);
877 if (chunk
->size
>= (AT_XDMAC_MBR_UBC_UBLEN_MAX
<< dwidth
)) {
878 dev_dbg(chan2dev(chan
),
879 "%s: chunk too big (%d, max size %lu)...\n",
880 __func__
, chunk
->size
,
881 AT_XDMAC_MBR_UBC_UBLEN_MAX
<< dwidth
);
886 dev_dbg(chan2dev(chan
),
887 "Adding items at the end of desc 0x%p\n", prev
);
891 chan_cc
|= AT_XDMAC_CC_SAM_UBS_AM
;
893 chan_cc
|= AT_XDMAC_CC_SAM_INCREMENTED_AM
;
898 chan_cc
|= AT_XDMAC_CC_DAM_UBS_AM
;
900 chan_cc
|= AT_XDMAC_CC_DAM_INCREMENTED_AM
;
903 spin_lock_irqsave(&atchan
->lock
, flags
);
904 desc
= at_xdmac_get_desc(atchan
);
905 spin_unlock_irqrestore(&atchan
->lock
, flags
);
907 dev_err(chan2dev(chan
), "can't get descriptor\n");
911 chan_cc
|= AT_XDMAC_CC_DWIDTH(dwidth
);
913 ublen
= chunk
->size
>> dwidth
;
915 desc
->lld
.mbr_sa
= src
;
916 desc
->lld
.mbr_da
= dst
;
917 desc
->lld
.mbr_sus
= dmaengine_get_src_icg(xt
, chunk
);
918 desc
->lld
.mbr_dus
= dmaengine_get_dst_icg(xt
, chunk
);
920 desc
->lld
.mbr_ubc
= AT_XDMAC_MBR_UBC_NDV3
921 | AT_XDMAC_MBR_UBC_NDEN
922 | AT_XDMAC_MBR_UBC_NSEN
924 desc
->lld
.mbr_cfg
= chan_cc
;
926 dev_dbg(chan2dev(chan
),
927 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
928 __func__
, &desc
->lld
.mbr_sa
, &desc
->lld
.mbr_da
,
929 desc
->lld
.mbr_ubc
, desc
->lld
.mbr_cfg
);
933 at_xdmac_queue_desc(chan
, prev
, desc
);
938 static struct dma_async_tx_descriptor
*
939 at_xdmac_prep_interleaved(struct dma_chan
*chan
,
940 struct dma_interleaved_template
*xt
,
943 struct at_xdmac_chan
*atchan
= to_at_xdmac_chan(chan
);
944 struct at_xdmac_desc
*prev
= NULL
, *first
= NULL
;
945 dma_addr_t dst_addr
, src_addr
;
946 size_t src_skip
= 0, dst_skip
= 0, len
= 0;
947 struct data_chunk
*chunk
;
950 if (!xt
|| !xt
->numf
|| (xt
->dir
!= DMA_MEM_TO_MEM
))
954 * TODO: Handle the case where we have to repeat a chain of
957 if ((xt
->numf
> 1) && (xt
->frame_size
> 1))
960 dev_dbg(chan2dev(chan
), "%s: src=%pad, dest=%pad, numf=%d, frame_size=%d, flags=0x%lx\n",
961 __func__
, &xt
->src_start
, &xt
->dst_start
, xt
->numf
,
962 xt
->frame_size
, flags
);
964 src_addr
= xt
->src_start
;
965 dst_addr
= xt
->dst_start
;
968 first
= at_xdmac_interleaved_queue_desc(chan
, atchan
,
973 /* Length of the block is (BLEN+1) microblocks. */
974 for (i
= 0; i
< xt
->numf
- 1; i
++)
975 at_xdmac_increment_block_count(chan
, first
);
977 dev_dbg(chan2dev(chan
), "%s: add desc 0x%p to descs_list 0x%p\n",
978 __func__
, first
, first
);
979 list_add_tail(&first
->desc_node
, &first
->descs_list
);
981 for (i
= 0; i
< xt
->frame_size
; i
++) {
982 size_t src_icg
= 0, dst_icg
= 0;
983 struct at_xdmac_desc
*desc
;
987 dst_icg
= dmaengine_get_dst_icg(xt
, chunk
);
988 src_icg
= dmaengine_get_src_icg(xt
, chunk
);
990 src_skip
= chunk
->size
+ src_icg
;
991 dst_skip
= chunk
->size
+ dst_icg
;
993 dev_dbg(chan2dev(chan
),
994 "%s: chunk size=%d, src icg=%d, dst icg=%d\n",
995 __func__
, chunk
->size
, src_icg
, dst_icg
);
997 desc
= at_xdmac_interleaved_queue_desc(chan
, atchan
,
1002 list_splice_init(&first
->descs_list
,
1003 &atchan
->free_descs_list
);
1010 dev_dbg(chan2dev(chan
), "%s: add desc 0x%p to descs_list 0x%p\n",
1011 __func__
, desc
, first
);
1012 list_add_tail(&desc
->desc_node
, &first
->descs_list
);
1015 src_addr
+= src_skip
;
1018 dst_addr
+= dst_skip
;
1025 first
->tx_dma_desc
.cookie
= -EBUSY
;
1026 first
->tx_dma_desc
.flags
= flags
;
1027 first
->xfer_size
= len
;
1029 return &first
->tx_dma_desc
;
1032 static struct dma_async_tx_descriptor
*
1033 at_xdmac_prep_dma_memcpy(struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t src
,
1034 size_t len
, unsigned long flags
)
1036 struct at_xdmac_chan
*atchan
= to_at_xdmac_chan(chan
);
1037 struct at_xdmac_desc
*first
= NULL
, *prev
= NULL
;
1038 size_t remaining_size
= len
, xfer_size
= 0, ublen
;
1039 dma_addr_t src_addr
= src
, dst_addr
= dest
;
1042 * WARNING: We don't know the direction, it involves we can't
1043 * dynamically set the source and dest interface so we have to use the
1044 * same one. Only interface 0 allows EBI access. Hopefully we can
1045 * access DDR through both ports (at least on SAMA5D4x), so we can use
1046 * the same interface for source and dest, that solves the fact we
1047 * don't know the direction.
1048 * ERRATA: Even if useless for memory transfers, the PERID has to not
1049 * match the one of another channel. If not, it could lead to spurious
1052 u32 chan_cc
= AT_XDMAC_CC_PERID(0x3f)
1053 | AT_XDMAC_CC_DAM_INCREMENTED_AM
1054 | AT_XDMAC_CC_SAM_INCREMENTED_AM
1055 | AT_XDMAC_CC_DIF(0)
1056 | AT_XDMAC_CC_SIF(0)
1057 | AT_XDMAC_CC_MBSIZE_SIXTEEN
1058 | AT_XDMAC_CC_TYPE_MEM_TRAN
;
1059 unsigned long irqflags
;
1061 dev_dbg(chan2dev(chan
), "%s: src=%pad, dest=%pad, len=%zd, flags=0x%lx\n",
1062 __func__
, &src
, &dest
, len
, flags
);
1067 dwidth
= at_xdmac_align_width(chan
, src_addr
| dst_addr
);
1069 /* Prepare descriptors. */
1070 while (remaining_size
) {
1071 struct at_xdmac_desc
*desc
= NULL
;
1073 dev_dbg(chan2dev(chan
), "%s: remaining_size=%zu\n", __func__
, remaining_size
);
1075 spin_lock_irqsave(&atchan
->lock
, irqflags
);
1076 desc
= at_xdmac_get_desc(atchan
);
1077 spin_unlock_irqrestore(&atchan
->lock
, irqflags
);
1079 dev_err(chan2dev(chan
), "can't get descriptor\n");
1081 list_splice_init(&first
->descs_list
, &atchan
->free_descs_list
);
1085 /* Update src and dest addresses. */
1086 src_addr
+= xfer_size
;
1087 dst_addr
+= xfer_size
;
1089 if (remaining_size
>= AT_XDMAC_MBR_UBC_UBLEN_MAX
<< dwidth
)
1090 xfer_size
= AT_XDMAC_MBR_UBC_UBLEN_MAX
<< dwidth
;
1092 xfer_size
= remaining_size
;
1094 dev_dbg(chan2dev(chan
), "%s: xfer_size=%zu\n", __func__
, xfer_size
);
1096 /* Check remaining length and change data width if needed. */
1097 dwidth
= at_xdmac_align_width(chan
,
1098 src_addr
| dst_addr
| xfer_size
);
1099 chan_cc
&= ~AT_XDMAC_CC_DWIDTH_MASK
;
1100 chan_cc
|= AT_XDMAC_CC_DWIDTH(dwidth
);
1102 ublen
= xfer_size
>> dwidth
;
1103 remaining_size
-= xfer_size
;
1105 desc
->lld
.mbr_sa
= src_addr
;
1106 desc
->lld
.mbr_da
= dst_addr
;
1107 desc
->lld
.mbr_ubc
= AT_XDMAC_MBR_UBC_NDV2
1108 | AT_XDMAC_MBR_UBC_NDEN
1109 | AT_XDMAC_MBR_UBC_NSEN
1111 desc
->lld
.mbr_cfg
= chan_cc
;
1113 dev_dbg(chan2dev(chan
),
1114 "%s: lld: mbr_sa=%pad, mbr_da=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
1115 __func__
, &desc
->lld
.mbr_sa
, &desc
->lld
.mbr_da
, desc
->lld
.mbr_ubc
, desc
->lld
.mbr_cfg
);
1119 at_xdmac_queue_desc(chan
, prev
, desc
);
1125 dev_dbg(chan2dev(chan
), "%s: add desc 0x%p to descs_list 0x%p\n",
1126 __func__
, desc
, first
);
1127 list_add_tail(&desc
->desc_node
, &first
->descs_list
);
1130 first
->tx_dma_desc
.flags
= flags
;
1131 first
->xfer_size
= len
;
1133 return &first
->tx_dma_desc
;
1136 static struct at_xdmac_desc
*at_xdmac_memset_create_desc(struct dma_chan
*chan
,
1137 struct at_xdmac_chan
*atchan
,
1138 dma_addr_t dst_addr
,
1142 struct at_xdmac_desc
*desc
;
1143 unsigned long flags
;
1147 * WARNING: The channel configuration is set here since there is no
1148 * dmaengine_slave_config call in this case. Moreover we don't know the
1149 * direction, it involves we can't dynamically set the source and dest
1150 * interface so we have to use the same one. Only interface 0 allows EBI
1151 * access. Hopefully we can access DDR through both ports (at least on
1152 * SAMA5D4x), so we can use the same interface for source and dest,
1153 * that solves the fact we don't know the direction.
1154 * ERRATA: Even if useless for memory transfers, the PERID has to not
1155 * match the one of another channel. If not, it could lead to spurious
1158 u32 chan_cc
= AT_XDMAC_CC_PERID(0x3f)
1159 | AT_XDMAC_CC_DAM_UBS_AM
1160 | AT_XDMAC_CC_SAM_INCREMENTED_AM
1161 | AT_XDMAC_CC_DIF(0)
1162 | AT_XDMAC_CC_SIF(0)
1163 | AT_XDMAC_CC_MBSIZE_SIXTEEN
1164 | AT_XDMAC_CC_MEMSET_HW_MODE
1165 | AT_XDMAC_CC_TYPE_MEM_TRAN
;
1167 dwidth
= at_xdmac_align_width(chan
, dst_addr
);
1169 if (len
>= (AT_XDMAC_MBR_UBC_UBLEN_MAX
<< dwidth
)) {
1170 dev_err(chan2dev(chan
),
1171 "%s: Transfer too large, aborting...\n",
1176 spin_lock_irqsave(&atchan
->lock
, flags
);
1177 desc
= at_xdmac_get_desc(atchan
);
1178 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1180 dev_err(chan2dev(chan
), "can't get descriptor\n");
1184 chan_cc
|= AT_XDMAC_CC_DWIDTH(dwidth
);
1186 ublen
= len
>> dwidth
;
1188 desc
->lld
.mbr_da
= dst_addr
;
1189 desc
->lld
.mbr_ds
= value
;
1190 desc
->lld
.mbr_ubc
= AT_XDMAC_MBR_UBC_NDV3
1191 | AT_XDMAC_MBR_UBC_NDEN
1192 | AT_XDMAC_MBR_UBC_NSEN
1194 desc
->lld
.mbr_cfg
= chan_cc
;
1196 dev_dbg(chan2dev(chan
),
1197 "%s: lld: mbr_da=%pad, mbr_ds=%pad, mbr_ubc=0x%08x, mbr_cfg=0x%08x\n",
1198 __func__
, &desc
->lld
.mbr_da
, &desc
->lld
.mbr_ds
, desc
->lld
.mbr_ubc
,
1204 struct dma_async_tx_descriptor
*
1205 at_xdmac_prep_dma_memset(struct dma_chan
*chan
, dma_addr_t dest
, int value
,
1206 size_t len
, unsigned long flags
)
1208 struct at_xdmac_chan
*atchan
= to_at_xdmac_chan(chan
);
1209 struct at_xdmac_desc
*desc
;
1211 dev_dbg(chan2dev(chan
), "%s: dest=%pad, len=%d, pattern=0x%x, flags=0x%lx\n",
1212 __func__
, &dest
, len
, value
, flags
);
1217 desc
= at_xdmac_memset_create_desc(chan
, atchan
, dest
, len
, value
);
1218 list_add_tail(&desc
->desc_node
, &desc
->descs_list
);
1220 desc
->tx_dma_desc
.cookie
= -EBUSY
;
1221 desc
->tx_dma_desc
.flags
= flags
;
1222 desc
->xfer_size
= len
;
1224 return &desc
->tx_dma_desc
;
1227 static struct dma_async_tx_descriptor
*
1228 at_xdmac_prep_dma_memset_sg(struct dma_chan
*chan
, struct scatterlist
*sgl
,
1229 unsigned int sg_len
, int value
,
1230 unsigned long flags
)
1232 struct at_xdmac_chan
*atchan
= to_at_xdmac_chan(chan
);
1233 struct at_xdmac_desc
*desc
, *pdesc
= NULL
,
1234 *ppdesc
= NULL
, *first
= NULL
;
1235 struct scatterlist
*sg
, *psg
= NULL
, *ppsg
= NULL
;
1236 size_t stride
= 0, pstride
= 0, len
= 0;
1242 dev_dbg(chan2dev(chan
), "%s: sg_len=%d, value=0x%x, flags=0x%lx\n",
1243 __func__
, sg_len
, value
, flags
);
1245 /* Prepare descriptors. */
1246 for_each_sg(sgl
, sg
, sg_len
, i
) {
1247 dev_dbg(chan2dev(chan
), "%s: dest=%pad, len=%d, pattern=0x%x, flags=0x%lx\n",
1248 __func__
, &sg_dma_address(sg
), sg_dma_len(sg
),
1250 desc
= at_xdmac_memset_create_desc(chan
, atchan
,
1255 list_splice_init(&first
->descs_list
,
1256 &atchan
->free_descs_list
);
1261 /* Update our strides */
1264 stride
= sg_dma_address(sg
) -
1265 (sg_dma_address(psg
) + sg_dma_len(psg
));
1268 * The scatterlist API gives us only the address and
1269 * length of each elements.
1271 * Unfortunately, we don't have the stride, which we
1272 * will need to compute.
1274 * That make us end up in a situation like this one:
1275 * len stride len stride len
1276 * +-------+ +-------+ +-------+
1277 * | N-2 | | N-1 | | N |
1278 * +-------+ +-------+ +-------+
1280 * We need all these three elements (N-2, N-1 and N)
1281 * to actually take the decision on whether we need to
1282 * queue N-1 or reuse N-2.
1284 * We will only consider N if it is the last element.
1286 if (ppdesc
&& pdesc
) {
1287 if ((stride
== pstride
) &&
1288 (sg_dma_len(ppsg
) == sg_dma_len(psg
))) {
1289 dev_dbg(chan2dev(chan
),
1290 "%s: desc 0x%p can be merged with desc 0x%p\n",
1291 __func__
, pdesc
, ppdesc
);
1294 * Increment the block count of the
1297 at_xdmac_increment_block_count(chan
, ppdesc
);
1298 ppdesc
->lld
.mbr_dus
= stride
;
1301 * Put back the N-1 descriptor in the
1302 * free descriptor list
1304 list_add_tail(&pdesc
->desc_node
,
1305 &atchan
->free_descs_list
);
1308 * Make our N-1 descriptor pointer
1309 * point to the N-2 since they were
1315 * Rule out the case where we don't have
1316 * pstride computed yet (our second sg
1319 * We also want to catch the case where there
1320 * would be a negative stride,
1322 } else if (pstride
||
1323 sg_dma_address(sg
) < sg_dma_address(psg
)) {
1325 * Queue the N-1 descriptor after the
1328 at_xdmac_queue_desc(chan
, ppdesc
, pdesc
);
1331 * Add the N-1 descriptor to the list
1332 * of the descriptors used for this
1335 list_add_tail(&desc
->desc_node
,
1336 &first
->descs_list
);
1337 dev_dbg(chan2dev(chan
),
1338 "%s: add desc 0x%p to descs_list 0x%p\n",
1339 __func__
, desc
, first
);
1344 * If we are the last element, just see if we have the
1345 * same size than the previous element.
1347 * If so, we can merge it with the previous descriptor
1348 * since we don't care about the stride anymore.
1350 if ((i
== (sg_len
- 1)) &&
1351 sg_dma_len(psg
) == sg_dma_len(sg
)) {
1352 dev_dbg(chan2dev(chan
),
1353 "%s: desc 0x%p can be merged with desc 0x%p\n",
1354 __func__
, desc
, pdesc
);
1357 * Increment the block count of the N-1
1360 at_xdmac_increment_block_count(chan
, pdesc
);
1361 pdesc
->lld
.mbr_dus
= stride
;
1364 * Put back the N descriptor in the free
1367 list_add_tail(&desc
->desc_node
,
1368 &atchan
->free_descs_list
);
1371 /* Update our descriptors */
1375 /* Update our scatter pointers */
1379 len
+= sg_dma_len(sg
);
1382 first
->tx_dma_desc
.cookie
= -EBUSY
;
1383 first
->tx_dma_desc
.flags
= flags
;
1384 first
->xfer_size
= len
;
1386 return &first
->tx_dma_desc
;
1389 static enum dma_status
1390 at_xdmac_tx_status(struct dma_chan
*chan
, dma_cookie_t cookie
,
1391 struct dma_tx_state
*txstate
)
1393 struct at_xdmac_chan
*atchan
= to_at_xdmac_chan(chan
);
1394 struct at_xdmac
*atxdmac
= to_at_xdmac(atchan
->chan
.device
);
1395 struct at_xdmac_desc
*desc
, *_desc
;
1396 struct list_head
*descs_list
;
1397 enum dma_status ret
;
1399 u32 cur_nda
, mask
, value
;
1401 unsigned long flags
;
1403 ret
= dma_cookie_status(chan
, cookie
, txstate
);
1404 if (ret
== DMA_COMPLETE
)
1410 spin_lock_irqsave(&atchan
->lock
, flags
);
1412 desc
= list_first_entry(&atchan
->xfers_list
, struct at_xdmac_desc
, xfer_node
);
1415 * If the transfer has not been started yet, don't need to compute the
1416 * residue, it's the transfer length.
1418 if (!desc
->active_xfer
) {
1419 dma_set_residue(txstate
, desc
->xfer_size
);
1423 residue
= desc
->xfer_size
;
1425 * Flush FIFO: only relevant when the transfer is source peripheral
1428 mask
= AT_XDMAC_CC_TYPE
| AT_XDMAC_CC_DSYNC
;
1429 value
= AT_XDMAC_CC_TYPE_PER_TRAN
| AT_XDMAC_CC_DSYNC_PER2MEM
;
1430 if ((desc
->lld
.mbr_cfg
& mask
) == value
) {
1431 at_xdmac_write(atxdmac
, AT_XDMAC_GSWF
, atchan
->mask
);
1432 while (!(at_xdmac_chan_read(atchan
, AT_XDMAC_CIS
) & AT_XDMAC_CIS_FIS
))
1436 cur_nda
= at_xdmac_chan_read(atchan
, AT_XDMAC_CNDA
) & 0xfffffffc;
1438 * Remove size of all microblocks already transferred and the current
1439 * one. Then add the remaining size to transfer of the current
1442 descs_list
= &desc
->descs_list
;
1443 list_for_each_entry_safe(desc
, _desc
, descs_list
, desc_node
) {
1444 dwidth
= at_xdmac_get_dwidth(desc
->lld
.mbr_cfg
);
1445 residue
-= (desc
->lld
.mbr_ubc
& 0xffffff) << dwidth
;
1446 if ((desc
->lld
.mbr_nda
& 0xfffffffc) == cur_nda
)
1449 residue
+= at_xdmac_chan_read(atchan
, AT_XDMAC_CUBC
) << dwidth
;
1451 dma_set_residue(txstate
, residue
);
1453 dev_dbg(chan2dev(chan
),
1454 "%s: desc=0x%p, tx_dma_desc.phys=%pad, tx_status=%d, cookie=%d, residue=%d\n",
1455 __func__
, desc
, &desc
->tx_dma_desc
.phys
, ret
, cookie
, residue
);
1458 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1462 /* Call must be protected by lock. */
1463 static void at_xdmac_remove_xfer(struct at_xdmac_chan
*atchan
,
1464 struct at_xdmac_desc
*desc
)
1466 dev_dbg(chan2dev(&atchan
->chan
), "%s: desc 0x%p\n", __func__
, desc
);
1469 * Remove the transfer from the transfer list then move the transfer
1470 * descriptors into the free descriptors list.
1472 list_del(&desc
->xfer_node
);
1473 list_splice_init(&desc
->descs_list
, &atchan
->free_descs_list
);
1476 static void at_xdmac_advance_work(struct at_xdmac_chan
*atchan
)
1478 struct at_xdmac_desc
*desc
;
1479 unsigned long flags
;
1481 spin_lock_irqsave(&atchan
->lock
, flags
);
1484 * If channel is enabled, do nothing, advance_work will be triggered
1485 * after the interruption.
1487 if (!at_xdmac_chan_is_enabled(atchan
) && !list_empty(&atchan
->xfers_list
)) {
1488 desc
= list_first_entry(&atchan
->xfers_list
,
1489 struct at_xdmac_desc
,
1491 dev_vdbg(chan2dev(&atchan
->chan
), "%s: desc 0x%p\n", __func__
, desc
);
1492 if (!desc
->active_xfer
)
1493 at_xdmac_start_xfer(atchan
, desc
);
1496 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1499 static void at_xdmac_handle_cyclic(struct at_xdmac_chan
*atchan
)
1501 struct at_xdmac_desc
*desc
;
1502 struct dma_async_tx_descriptor
*txd
;
1504 desc
= list_first_entry(&atchan
->xfers_list
, struct at_xdmac_desc
, xfer_node
);
1505 txd
= &desc
->tx_dma_desc
;
1507 if (txd
->callback
&& (txd
->flags
& DMA_PREP_INTERRUPT
))
1508 txd
->callback(txd
->callback_param
);
1511 static void at_xdmac_tasklet(unsigned long data
)
1513 struct at_xdmac_chan
*atchan
= (struct at_xdmac_chan
*)data
;
1514 struct at_xdmac_desc
*desc
;
1517 dev_dbg(chan2dev(&atchan
->chan
), "%s: status=0x%08lx\n",
1518 __func__
, atchan
->status
);
1520 error_mask
= AT_XDMAC_CIS_RBEIS
1521 | AT_XDMAC_CIS_WBEIS
1522 | AT_XDMAC_CIS_ROIS
;
1524 if (at_xdmac_chan_is_cyclic(atchan
)) {
1525 at_xdmac_handle_cyclic(atchan
);
1526 } else if ((atchan
->status
& AT_XDMAC_CIS_LIS
)
1527 || (atchan
->status
& error_mask
)) {
1528 struct dma_async_tx_descriptor
*txd
;
1530 if (atchan
->status
& AT_XDMAC_CIS_RBEIS
)
1531 dev_err(chan2dev(&atchan
->chan
), "read bus error!!!");
1532 if (atchan
->status
& AT_XDMAC_CIS_WBEIS
)
1533 dev_err(chan2dev(&atchan
->chan
), "write bus error!!!");
1534 if (atchan
->status
& AT_XDMAC_CIS_ROIS
)
1535 dev_err(chan2dev(&atchan
->chan
), "request overflow error!!!");
1537 spin_lock_bh(&atchan
->lock
);
1538 desc
= list_first_entry(&atchan
->xfers_list
,
1539 struct at_xdmac_desc
,
1541 dev_vdbg(chan2dev(&atchan
->chan
), "%s: desc 0x%p\n", __func__
, desc
);
1542 BUG_ON(!desc
->active_xfer
);
1544 txd
= &desc
->tx_dma_desc
;
1546 at_xdmac_remove_xfer(atchan
, desc
);
1547 spin_unlock_bh(&atchan
->lock
);
1549 if (!at_xdmac_chan_is_cyclic(atchan
)) {
1550 dma_cookie_complete(txd
);
1551 if (txd
->callback
&& (txd
->flags
& DMA_PREP_INTERRUPT
))
1552 txd
->callback(txd
->callback_param
);
1555 dma_run_dependencies(txd
);
1557 at_xdmac_advance_work(atchan
);
1561 static irqreturn_t
at_xdmac_interrupt(int irq
, void *dev_id
)
1563 struct at_xdmac
*atxdmac
= (struct at_xdmac
*)dev_id
;
1564 struct at_xdmac_chan
*atchan
;
1565 u32 imr
, status
, pending
;
1566 u32 chan_imr
, chan_status
;
1567 int i
, ret
= IRQ_NONE
;
1570 imr
= at_xdmac_read(atxdmac
, AT_XDMAC_GIM
);
1571 status
= at_xdmac_read(atxdmac
, AT_XDMAC_GIS
);
1572 pending
= status
& imr
;
1574 dev_vdbg(atxdmac
->dma
.dev
,
1575 "%s: status=0x%08x, imr=0x%08x, pending=0x%08x\n",
1576 __func__
, status
, imr
, pending
);
1581 /* We have to find which channel has generated the interrupt. */
1582 for (i
= 0; i
< atxdmac
->dma
.chancnt
; i
++) {
1583 if (!((1 << i
) & pending
))
1586 atchan
= &atxdmac
->chan
[i
];
1587 chan_imr
= at_xdmac_chan_read(atchan
, AT_XDMAC_CIM
);
1588 chan_status
= at_xdmac_chan_read(atchan
, AT_XDMAC_CIS
);
1589 atchan
->status
= chan_status
& chan_imr
;
1590 dev_vdbg(atxdmac
->dma
.dev
,
1591 "%s: chan%d: imr=0x%x, status=0x%x\n",
1592 __func__
, i
, chan_imr
, chan_status
);
1593 dev_vdbg(chan2dev(&atchan
->chan
),
1594 "%s: CC=0x%08x CNDA=0x%08x, CNDC=0x%08x, CSA=0x%08x, CDA=0x%08x, CUBC=0x%08x\n",
1596 at_xdmac_chan_read(atchan
, AT_XDMAC_CC
),
1597 at_xdmac_chan_read(atchan
, AT_XDMAC_CNDA
),
1598 at_xdmac_chan_read(atchan
, AT_XDMAC_CNDC
),
1599 at_xdmac_chan_read(atchan
, AT_XDMAC_CSA
),
1600 at_xdmac_chan_read(atchan
, AT_XDMAC_CDA
),
1601 at_xdmac_chan_read(atchan
, AT_XDMAC_CUBC
));
1603 if (atchan
->status
& (AT_XDMAC_CIS_RBEIS
| AT_XDMAC_CIS_WBEIS
))
1604 at_xdmac_write(atxdmac
, AT_XDMAC_GD
, atchan
->mask
);
1606 tasklet_schedule(&atchan
->tasklet
);
1615 static void at_xdmac_issue_pending(struct dma_chan
*chan
)
1617 struct at_xdmac_chan
*atchan
= to_at_xdmac_chan(chan
);
1619 dev_dbg(chan2dev(&atchan
->chan
), "%s\n", __func__
);
1621 if (!at_xdmac_chan_is_cyclic(atchan
))
1622 at_xdmac_advance_work(atchan
);
1627 static int at_xdmac_device_config(struct dma_chan
*chan
,
1628 struct dma_slave_config
*config
)
1630 struct at_xdmac_chan
*atchan
= to_at_xdmac_chan(chan
);
1632 unsigned long flags
;
1634 dev_dbg(chan2dev(chan
), "%s\n", __func__
);
1636 spin_lock_irqsave(&atchan
->lock
, flags
);
1637 ret
= at_xdmac_set_slave_config(chan
, config
);
1638 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1643 static int at_xdmac_device_pause(struct dma_chan
*chan
)
1645 struct at_xdmac_chan
*atchan
= to_at_xdmac_chan(chan
);
1646 struct at_xdmac
*atxdmac
= to_at_xdmac(atchan
->chan
.device
);
1647 unsigned long flags
;
1649 dev_dbg(chan2dev(chan
), "%s\n", __func__
);
1651 if (test_and_set_bit(AT_XDMAC_CHAN_IS_PAUSED
, &atchan
->status
))
1654 spin_lock_irqsave(&atchan
->lock
, flags
);
1655 at_xdmac_write(atxdmac
, AT_XDMAC_GRWS
, atchan
->mask
);
1656 while (at_xdmac_chan_read(atchan
, AT_XDMAC_CC
)
1657 & (AT_XDMAC_CC_WRIP
| AT_XDMAC_CC_RDIP
))
1659 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1664 static int at_xdmac_device_resume(struct dma_chan
*chan
)
1666 struct at_xdmac_chan
*atchan
= to_at_xdmac_chan(chan
);
1667 struct at_xdmac
*atxdmac
= to_at_xdmac(atchan
->chan
.device
);
1668 unsigned long flags
;
1670 dev_dbg(chan2dev(chan
), "%s\n", __func__
);
1672 spin_lock_irqsave(&atchan
->lock
, flags
);
1673 if (!at_xdmac_chan_is_paused(atchan
)) {
1674 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1678 at_xdmac_write(atxdmac
, AT_XDMAC_GRWR
, atchan
->mask
);
1679 clear_bit(AT_XDMAC_CHAN_IS_PAUSED
, &atchan
->status
);
1680 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1685 static int at_xdmac_device_terminate_all(struct dma_chan
*chan
)
1687 struct at_xdmac_desc
*desc
, *_desc
;
1688 struct at_xdmac_chan
*atchan
= to_at_xdmac_chan(chan
);
1689 struct at_xdmac
*atxdmac
= to_at_xdmac(atchan
->chan
.device
);
1690 unsigned long flags
;
1692 dev_dbg(chan2dev(chan
), "%s\n", __func__
);
1694 spin_lock_irqsave(&atchan
->lock
, flags
);
1695 at_xdmac_write(atxdmac
, AT_XDMAC_GD
, atchan
->mask
);
1696 while (at_xdmac_read(atxdmac
, AT_XDMAC_GS
) & atchan
->mask
)
1699 /* Cancel all pending transfers. */
1700 list_for_each_entry_safe(desc
, _desc
, &atchan
->xfers_list
, xfer_node
)
1701 at_xdmac_remove_xfer(atchan
, desc
);
1703 clear_bit(AT_XDMAC_CHAN_IS_PAUSED
, &atchan
->status
);
1704 clear_bit(AT_XDMAC_CHAN_IS_CYCLIC
, &atchan
->status
);
1705 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1710 static int at_xdmac_alloc_chan_resources(struct dma_chan
*chan
)
1712 struct at_xdmac_chan
*atchan
= to_at_xdmac_chan(chan
);
1713 struct at_xdmac_desc
*desc
;
1715 unsigned long flags
;
1717 spin_lock_irqsave(&atchan
->lock
, flags
);
1719 if (at_xdmac_chan_is_enabled(atchan
)) {
1720 dev_err(chan2dev(chan
),
1721 "can't allocate channel resources (channel enabled)\n");
1726 if (!list_empty(&atchan
->free_descs_list
)) {
1727 dev_err(chan2dev(chan
),
1728 "can't allocate channel resources (channel not free from a previous use)\n");
1733 for (i
= 0; i
< init_nr_desc_per_channel
; i
++) {
1734 desc
= at_xdmac_alloc_desc(chan
, GFP_ATOMIC
);
1736 dev_warn(chan2dev(chan
),
1737 "only %d descriptors have been allocated\n", i
);
1740 list_add_tail(&desc
->desc_node
, &atchan
->free_descs_list
);
1743 dma_cookie_init(chan
);
1745 dev_dbg(chan2dev(chan
), "%s: allocated %d descriptors\n", __func__
, i
);
1748 spin_unlock_irqrestore(&atchan
->lock
, flags
);
1752 static void at_xdmac_free_chan_resources(struct dma_chan
*chan
)
1754 struct at_xdmac_chan
*atchan
= to_at_xdmac_chan(chan
);
1755 struct at_xdmac
*atxdmac
= to_at_xdmac(chan
->device
);
1756 struct at_xdmac_desc
*desc
, *_desc
;
1758 list_for_each_entry_safe(desc
, _desc
, &atchan
->free_descs_list
, desc_node
) {
1759 dev_dbg(chan2dev(chan
), "%s: freeing descriptor %p\n", __func__
, desc
);
1760 list_del(&desc
->desc_node
);
1761 dma_pool_free(atxdmac
->at_xdmac_desc_pool
, desc
, desc
->tx_dma_desc
.phys
);
1768 static int atmel_xdmac_prepare(struct device
*dev
)
1770 struct platform_device
*pdev
= to_platform_device(dev
);
1771 struct at_xdmac
*atxdmac
= platform_get_drvdata(pdev
);
1772 struct dma_chan
*chan
, *_chan
;
1774 list_for_each_entry_safe(chan
, _chan
, &atxdmac
->dma
.channels
, device_node
) {
1775 struct at_xdmac_chan
*atchan
= to_at_xdmac_chan(chan
);
1777 /* Wait for transfer completion, except in cyclic case. */
1778 if (at_xdmac_chan_is_enabled(atchan
) && !at_xdmac_chan_is_cyclic(atchan
))
1784 # define atmel_xdmac_prepare NULL
1787 #ifdef CONFIG_PM_SLEEP
1788 static int atmel_xdmac_suspend(struct device
*dev
)
1790 struct platform_device
*pdev
= to_platform_device(dev
);
1791 struct at_xdmac
*atxdmac
= platform_get_drvdata(pdev
);
1792 struct dma_chan
*chan
, *_chan
;
1794 list_for_each_entry_safe(chan
, _chan
, &atxdmac
->dma
.channels
, device_node
) {
1795 struct at_xdmac_chan
*atchan
= to_at_xdmac_chan(chan
);
1797 atchan
->save_cc
= at_xdmac_chan_read(atchan
, AT_XDMAC_CC
);
1798 if (at_xdmac_chan_is_cyclic(atchan
)) {
1799 if (!at_xdmac_chan_is_paused(atchan
))
1800 at_xdmac_device_pause(chan
);
1801 atchan
->save_cim
= at_xdmac_chan_read(atchan
, AT_XDMAC_CIM
);
1802 atchan
->save_cnda
= at_xdmac_chan_read(atchan
, AT_XDMAC_CNDA
);
1803 atchan
->save_cndc
= at_xdmac_chan_read(atchan
, AT_XDMAC_CNDC
);
1806 atxdmac
->save_gim
= at_xdmac_read(atxdmac
, AT_XDMAC_GIM
);
1808 at_xdmac_off(atxdmac
);
1809 clk_disable_unprepare(atxdmac
->clk
);
1813 static int atmel_xdmac_resume(struct device
*dev
)
1815 struct platform_device
*pdev
= to_platform_device(dev
);
1816 struct at_xdmac
*atxdmac
= platform_get_drvdata(pdev
);
1817 struct at_xdmac_chan
*atchan
;
1818 struct dma_chan
*chan
, *_chan
;
1821 clk_prepare_enable(atxdmac
->clk
);
1823 /* Clear pending interrupts. */
1824 for (i
= 0; i
< atxdmac
->dma
.chancnt
; i
++) {
1825 atchan
= &atxdmac
->chan
[i
];
1826 while (at_xdmac_chan_read(atchan
, AT_XDMAC_CIS
))
1830 at_xdmac_write(atxdmac
, AT_XDMAC_GIE
, atxdmac
->save_gim
);
1831 at_xdmac_write(atxdmac
, AT_XDMAC_GE
, atxdmac
->save_gs
);
1832 list_for_each_entry_safe(chan
, _chan
, &atxdmac
->dma
.channels
, device_node
) {
1833 atchan
= to_at_xdmac_chan(chan
);
1834 at_xdmac_chan_write(atchan
, AT_XDMAC_CC
, atchan
->save_cc
);
1835 if (at_xdmac_chan_is_cyclic(atchan
)) {
1836 if (at_xdmac_chan_is_paused(atchan
))
1837 at_xdmac_device_resume(chan
);
1838 at_xdmac_chan_write(atchan
, AT_XDMAC_CNDA
, atchan
->save_cnda
);
1839 at_xdmac_chan_write(atchan
, AT_XDMAC_CNDC
, atchan
->save_cndc
);
1840 at_xdmac_chan_write(atchan
, AT_XDMAC_CIE
, atchan
->save_cim
);
1842 at_xdmac_write(atxdmac
, AT_XDMAC_GE
, atchan
->mask
);
1847 #endif /* CONFIG_PM_SLEEP */
1849 static int at_xdmac_probe(struct platform_device
*pdev
)
1851 struct resource
*res
;
1852 struct at_xdmac
*atxdmac
;
1853 int irq
, size
, nr_channels
, i
, ret
;
1857 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1861 irq
= platform_get_irq(pdev
, 0);
1865 base
= devm_ioremap_resource(&pdev
->dev
, res
);
1867 return PTR_ERR(base
);
1870 * Read number of xdmac channels, read helper function can't be used
1871 * since atxdmac is not yet allocated and we need to know the number
1872 * of channels to do the allocation.
1874 reg
= readl_relaxed(base
+ AT_XDMAC_GTYPE
);
1875 nr_channels
= AT_XDMAC_NB_CH(reg
);
1876 if (nr_channels
> AT_XDMAC_MAX_CHAN
) {
1877 dev_err(&pdev
->dev
, "invalid number of channels (%u)\n",
1882 size
= sizeof(*atxdmac
);
1883 size
+= nr_channels
* sizeof(struct at_xdmac_chan
);
1884 atxdmac
= devm_kzalloc(&pdev
->dev
, size
, GFP_KERNEL
);
1886 dev_err(&pdev
->dev
, "can't allocate at_xdmac structure\n");
1890 atxdmac
->regs
= base
;
1893 atxdmac
->clk
= devm_clk_get(&pdev
->dev
, "dma_clk");
1894 if (IS_ERR(atxdmac
->clk
)) {
1895 dev_err(&pdev
->dev
, "can't get dma_clk\n");
1896 return PTR_ERR(atxdmac
->clk
);
1899 /* Do not use dev res to prevent races with tasklet */
1900 ret
= request_irq(atxdmac
->irq
, at_xdmac_interrupt
, 0, "at_xdmac", atxdmac
);
1902 dev_err(&pdev
->dev
, "can't request irq\n");
1906 ret
= clk_prepare_enable(atxdmac
->clk
);
1908 dev_err(&pdev
->dev
, "can't prepare or enable clock\n");
1912 atxdmac
->at_xdmac_desc_pool
=
1913 dmam_pool_create(dev_name(&pdev
->dev
), &pdev
->dev
,
1914 sizeof(struct at_xdmac_desc
), 4, 0);
1915 if (!atxdmac
->at_xdmac_desc_pool
) {
1916 dev_err(&pdev
->dev
, "no memory for descriptors dma pool\n");
1918 goto err_clk_disable
;
1921 dma_cap_set(DMA_CYCLIC
, atxdmac
->dma
.cap_mask
);
1922 dma_cap_set(DMA_INTERLEAVE
, atxdmac
->dma
.cap_mask
);
1923 dma_cap_set(DMA_MEMCPY
, atxdmac
->dma
.cap_mask
);
1924 dma_cap_set(DMA_MEMSET
, atxdmac
->dma
.cap_mask
);
1925 dma_cap_set(DMA_MEMSET_SG
, atxdmac
->dma
.cap_mask
);
1926 dma_cap_set(DMA_SLAVE
, atxdmac
->dma
.cap_mask
);
1928 * Without DMA_PRIVATE the driver is not able to allocate more than
1929 * one channel, second allocation fails in private_candidate.
1931 dma_cap_set(DMA_PRIVATE
, atxdmac
->dma
.cap_mask
);
1932 atxdmac
->dma
.dev
= &pdev
->dev
;
1933 atxdmac
->dma
.device_alloc_chan_resources
= at_xdmac_alloc_chan_resources
;
1934 atxdmac
->dma
.device_free_chan_resources
= at_xdmac_free_chan_resources
;
1935 atxdmac
->dma
.device_tx_status
= at_xdmac_tx_status
;
1936 atxdmac
->dma
.device_issue_pending
= at_xdmac_issue_pending
;
1937 atxdmac
->dma
.device_prep_dma_cyclic
= at_xdmac_prep_dma_cyclic
;
1938 atxdmac
->dma
.device_prep_interleaved_dma
= at_xdmac_prep_interleaved
;
1939 atxdmac
->dma
.device_prep_dma_memcpy
= at_xdmac_prep_dma_memcpy
;
1940 atxdmac
->dma
.device_prep_dma_memset
= at_xdmac_prep_dma_memset
;
1941 atxdmac
->dma
.device_prep_dma_memset_sg
= at_xdmac_prep_dma_memset_sg
;
1942 atxdmac
->dma
.device_prep_slave_sg
= at_xdmac_prep_slave_sg
;
1943 atxdmac
->dma
.device_config
= at_xdmac_device_config
;
1944 atxdmac
->dma
.device_pause
= at_xdmac_device_pause
;
1945 atxdmac
->dma
.device_resume
= at_xdmac_device_resume
;
1946 atxdmac
->dma
.device_terminate_all
= at_xdmac_device_terminate_all
;
1947 atxdmac
->dma
.src_addr_widths
= AT_XDMAC_DMA_BUSWIDTHS
;
1948 atxdmac
->dma
.dst_addr_widths
= AT_XDMAC_DMA_BUSWIDTHS
;
1949 atxdmac
->dma
.directions
= BIT(DMA_DEV_TO_MEM
) | BIT(DMA_MEM_TO_DEV
);
1950 atxdmac
->dma
.residue_granularity
= DMA_RESIDUE_GRANULARITY_BURST
;
1952 /* Disable all chans and interrupts. */
1953 at_xdmac_off(atxdmac
);
1955 /* Init channels. */
1956 INIT_LIST_HEAD(&atxdmac
->dma
.channels
);
1957 for (i
= 0; i
< nr_channels
; i
++) {
1958 struct at_xdmac_chan
*atchan
= &atxdmac
->chan
[i
];
1960 atchan
->chan
.device
= &atxdmac
->dma
;
1961 list_add_tail(&atchan
->chan
.device_node
,
1962 &atxdmac
->dma
.channels
);
1964 atchan
->ch_regs
= at_xdmac_chan_reg_base(atxdmac
, i
);
1965 atchan
->mask
= 1 << i
;
1967 spin_lock_init(&atchan
->lock
);
1968 INIT_LIST_HEAD(&atchan
->xfers_list
);
1969 INIT_LIST_HEAD(&atchan
->free_descs_list
);
1970 tasklet_init(&atchan
->tasklet
, at_xdmac_tasklet
,
1971 (unsigned long)atchan
);
1973 /* Clear pending interrupts. */
1974 while (at_xdmac_chan_read(atchan
, AT_XDMAC_CIS
))
1977 platform_set_drvdata(pdev
, atxdmac
);
1979 ret
= dma_async_device_register(&atxdmac
->dma
);
1981 dev_err(&pdev
->dev
, "fail to register DMA engine device\n");
1982 goto err_clk_disable
;
1985 ret
= of_dma_controller_register(pdev
->dev
.of_node
,
1986 at_xdmac_xlate
, atxdmac
);
1988 dev_err(&pdev
->dev
, "could not register of dma controller\n");
1989 goto err_dma_unregister
;
1992 dev_info(&pdev
->dev
, "%d channels, mapped at 0x%p\n",
1993 nr_channels
, atxdmac
->regs
);
1998 dma_async_device_unregister(&atxdmac
->dma
);
2000 clk_disable_unprepare(atxdmac
->clk
);
2002 free_irq(atxdmac
->irq
, atxdmac
->dma
.dev
);
2006 static int at_xdmac_remove(struct platform_device
*pdev
)
2008 struct at_xdmac
*atxdmac
= (struct at_xdmac
*)platform_get_drvdata(pdev
);
2011 at_xdmac_off(atxdmac
);
2012 of_dma_controller_free(pdev
->dev
.of_node
);
2013 dma_async_device_unregister(&atxdmac
->dma
);
2014 clk_disable_unprepare(atxdmac
->clk
);
2016 free_irq(atxdmac
->irq
, atxdmac
->dma
.dev
);
2018 for (i
= 0; i
< atxdmac
->dma
.chancnt
; i
++) {
2019 struct at_xdmac_chan
*atchan
= &atxdmac
->chan
[i
];
2021 tasklet_kill(&atchan
->tasklet
);
2022 at_xdmac_free_chan_resources(&atchan
->chan
);
2028 static const struct dev_pm_ops atmel_xdmac_dev_pm_ops
= {
2029 .prepare
= atmel_xdmac_prepare
,
2030 SET_LATE_SYSTEM_SLEEP_PM_OPS(atmel_xdmac_suspend
, atmel_xdmac_resume
)
2033 static const struct of_device_id atmel_xdmac_dt_ids
[] = {
2035 .compatible
= "atmel,sama5d4-dma",
2040 MODULE_DEVICE_TABLE(of
, atmel_xdmac_dt_ids
);
2042 static struct platform_driver at_xdmac_driver
= {
2043 .probe
= at_xdmac_probe
,
2044 .remove
= at_xdmac_remove
,
2047 .of_match_table
= of_match_ptr(atmel_xdmac_dt_ids
),
2048 .pm
= &atmel_xdmac_dev_pm_ops
,
2052 static int __init
at_xdmac_init(void)
2054 return platform_driver_probe(&at_xdmac_driver
, at_xdmac_probe
);
2056 subsys_initcall(at_xdmac_init
);
2058 MODULE_DESCRIPTION("Atmel Extended DMA Controller driver");
2059 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
2060 MODULE_LICENSE("GPL");