drivers/dma/dw_dmac_regs.h

   1 /*
   2  * Driver for the Synopsys DesignWare AHB DMA Controller
   3  *
   4  * Copyright (C) 2005-2007 Atmel Corporation
   5  * Copyright (C) 2010-2011 ST Microelectronics
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/dmaengine.h>
  13 #include <linux/dw_dmac.h>
  14
  15 #define DW_DMA_MAX_NR_CHANNELS  8
  16
  17 /* flow controller */
  18 enum dw_dma_fc {
  19         DW_DMA_FC_D_M2M,
  20         DW_DMA_FC_D_M2P,
  21         DW_DMA_FC_D_P2M,
  22         DW_DMA_FC_D_P2P,
  23         DW_DMA_FC_P_P2M,
  24         DW_DMA_FC_SP_P2P,
  25         DW_DMA_FC_P_M2P,
  26         DW_DMA_FC_DP_P2P,
  27 };
  28
  29 /*
  30  * Redefine this macro to handle differences between 32- and 64-bit
  31  * addressing, big vs. little endian, etc.
  32  */
  33 #define DW_REG(name)            u32 name; u32 __pad_##name
  34
  35 /* Hardware register definitions. */
  36 struct dw_dma_chan_regs {
  37         DW_REG(SAR);            /* Source Address Register */
  38         DW_REG(DAR);            /* Destination Address Register */
  39         DW_REG(LLP);            /* Linked List Pointer */
  40         u32     CTL_LO;         /* Control Register Low */
  41         u32     CTL_HI;         /* Control Register High */
  42         DW_REG(SSTAT);
  43         DW_REG(DSTAT);
  44         DW_REG(SSTATAR);
  45         DW_REG(DSTATAR);
  46         u32     CFG_LO;         /* Configuration Register Low */
  47         u32     CFG_HI;         /* Configuration Register High */
  48         DW_REG(SGR);
  49         DW_REG(DSR);
  50 };
  51
  52 struct dw_dma_irq_regs {
  53         DW_REG(XFER);
  54         DW_REG(BLOCK);
  55         DW_REG(SRC_TRAN);
  56         DW_REG(DST_TRAN);
  57         DW_REG(ERROR);
  58 };
  59
  60 struct dw_dma_regs {
  61         /* per-channel registers */
  62         struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS];
  63
  64         /* irq handling */
  65         struct dw_dma_irq_regs  RAW;            /* r */
  66         struct dw_dma_irq_regs  STATUS;         /* r (raw & mask) */
  67         struct dw_dma_irq_regs  MASK;           /* rw (set = irq enabled) */
  68         struct dw_dma_irq_regs  CLEAR;          /* w (ack, affects "raw") */
  69
  70         DW_REG(STATUS_INT);                     /* r */
  71
  72         /* software handshaking */
  73         DW_REG(REQ_SRC);
  74         DW_REG(REQ_DST);
  75         DW_REG(SGL_REQ_SRC);
  76         DW_REG(SGL_REQ_DST);
  77         DW_REG(LAST_SRC);
  78         DW_REG(LAST_DST);
  79
  80         /* miscellaneous */
  81         DW_REG(CFG);
  82         DW_REG(CH_EN);
  83         DW_REG(ID);
  84         DW_REG(TEST);
  85
  86         /* reserved */
  87         DW_REG(__reserved0);
  88         DW_REG(__reserved1);
  89
  90         /* optional encoded params, 0x3c8..0x3f7 */
  91         u32     __reserved;
  92
  93         /* per-channel configuration registers */
  94         u32     DWC_PARAMS[DW_DMA_MAX_NR_CHANNELS];
  95         u32     MULTI_BLK_TYPE;
  96         u32     MAX_BLK_SIZE;
  97
  98         /* top-level parameters */
  99         u32     DW_PARAMS;
 100 };
 101
 102 #ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
 103 #define dma_readl_native ioread32be
 104 #define dma_writel_native iowrite32be
 105 #else
 106 #define dma_readl_native readl
 107 #define dma_writel_native writel
 108 #endif
 109
 110 /* To access the registers in early stage of probe */
 111 #define dma_read_byaddr(addr, name) \
 112         dma_readl_native((addr) + offsetof(struct dw_dma_regs, name))
 113
 114 /* Bitfields in DW_PARAMS */
 115 #define DW_PARAMS_NR_CHAN       8               /* number of channels */
 116 #define DW_PARAMS_NR_MASTER     11              /* number of AHB masters */
 117 #define DW_PARAMS_DATA_WIDTH(n) (15 + 2 * (n))
 118 #define DW_PARAMS_DATA_WIDTH1   15              /* master 1 data width */
 119 #define DW_PARAMS_DATA_WIDTH2   17              /* master 2 data width */
 120 #define DW_PARAMS_DATA_WIDTH3   19              /* master 3 data width */
 121 #define DW_PARAMS_DATA_WIDTH4   21              /* master 4 data width */
 122 #define DW_PARAMS_EN            28              /* encoded parameters */
 123
 124 /* Bitfields in DWC_PARAMS */
 125 #define DWC_PARAMS_MBLK_EN      11              /* multi block transfer */
 126
 127 /* Bitfields in CTL_LO */
 128 #define DWC_CTLL_INT_EN         (1 << 0)        /* irqs enabled? */
 129 #define DWC_CTLL_DST_WIDTH(n)   ((n)<<1)        /* bytes per element */
 130 #define DWC_CTLL_SRC_WIDTH(n)   ((n)<<4)
 131 #define DWC_CTLL_DST_INC        (0<<7)          /* DAR update/not */
 132 #define DWC_CTLL_DST_DEC        (1<<7)
 133 #define DWC_CTLL_DST_FIX        (2<<7)
 134 #define DWC_CTLL_SRC_INC        (0<<7)          /* SAR update/not */
 135 #define DWC_CTLL_SRC_DEC        (1<<9)
 136 #define DWC_CTLL_SRC_FIX        (2<<9)
 137 #define DWC_CTLL_DST_MSIZE(n)   ((n)<<11)       /* burst, #elements */
 138 #define DWC_CTLL_SRC_MSIZE(n)   ((n)<<14)
 139 #define DWC_CTLL_S_GATH_EN      (1 << 17)       /* src gather, !FIX */
 140 #define DWC_CTLL_D_SCAT_EN      (1 << 18)       /* dst scatter, !FIX */
 141 #define DWC_CTLL_FC(n)          ((n) << 20)
 142 #define DWC_CTLL_FC_M2M         (0 << 20)       /* mem-to-mem */
 143 #define DWC_CTLL_FC_M2P         (1 << 20)       /* mem-to-periph */
 144 #define DWC_CTLL_FC_P2M         (2 << 20)       /* periph-to-mem */
 145 #define DWC_CTLL_FC_P2P         (3 << 20)       /* periph-to-periph */
 146 /* plus 4 transfer types for peripheral-as-flow-controller */
 147 #define DWC_CTLL_DMS(n)         ((n)<<23)       /* dst master select */
 148 #define DWC_CTLL_SMS(n)         ((n)<<25)       /* src master select */
 149 #define DWC_CTLL_LLP_D_EN       (1 << 27)       /* dest block chain */
 150 #define DWC_CTLL_LLP_S_EN       (1 << 28)       /* src block chain */
 151
 152 /* Bitfields in CTL_HI */
 153 #define DWC_CTLH_DONE           0x00001000
 154 #define DWC_CTLH_BLOCK_TS_MASK  0x00000fff
 155
 156 /* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */
 157 #define DWC_CFGL_CH_PRIOR_MASK  (0x7 << 5)      /* priority mask */
 158 #define DWC_CFGL_CH_PRIOR(x)    ((x) << 5)      /* priority */
 159 #define DWC_CFGL_CH_SUSP        (1 << 8)        /* pause xfer */
 160 #define DWC_CFGL_FIFO_EMPTY     (1 << 9)        /* pause xfer */
 161 #define DWC_CFGL_HS_DST         (1 << 10)       /* handshake w/dst */
 162 #define DWC_CFGL_HS_SRC         (1 << 11)       /* handshake w/src */
 163 #define DWC_CFGL_MAX_BURST(x)   ((x) << 20)
 164 #define DWC_CFGL_RELOAD_SAR     (1 << 30)
 165 #define DWC_CFGL_RELOAD_DAR     (1 << 31)
 166
 167 /* Bitfields in CFG_HI. Platform-configurable bits are in <linux/dw_dmac.h> */
 168 #define DWC_CFGH_DS_UPD_EN      (1 << 5)
 169 #define DWC_CFGH_SS_UPD_EN      (1 << 6)
 170
 171 /* Bitfields in SGR */
 172 #define DWC_SGR_SGI(x)          ((x) << 0)
 173 #define DWC_SGR_SGC(x)          ((x) << 20)
 174
 175 /* Bitfields in DSR */
 176 #define DWC_DSR_DSI(x)          ((x) << 0)
 177 #define DWC_DSR_DSC(x)          ((x) << 20)
 178
 179 /* Bitfields in CFG */
 180 #define DW_CFG_DMA_EN           (1 << 0)
 181
 182 enum dw_dmac_flags {
 183         DW_DMA_IS_CYCLIC = 0,
 184         DW_DMA_IS_SOFT_LLP = 1,
 185 };
 186
 187 struct dw_dma_chan {
 188         struct dma_chan                 chan;
 189         void __iomem                    *ch_regs;
 190         u8                              mask;
 191         u8                              priority;
 192         enum dma_transfer_direction     direction;
 193         bool                            paused;
 194         bool                            initialized;
 195
 196         /* software emulation of the LLP transfers */
 197         struct list_head        *tx_node_active;
 198
 199         spinlock_t              lock;
 200
 201         /* these other elements are all protected by lock */
 202         unsigned long           flags;
 203         struct list_head        active_list;
 204         struct list_head        queue;
 205         struct list_head        free_list;
 206         u32                     residue;
 207         struct dw_cyclic_desc   *cdesc;
 208
 209         unsigned int            descs_allocated;
 210
 211         /* hardware configuration */
 212         unsigned int            block_size;
 213         bool                    nollp;
 214
 215         /* configuration passed via DMA_SLAVE_CONFIG */
 216         struct dma_slave_config dma_sconfig;
 217 };
 218
 219 static inline struct dw_dma_chan_regs __iomem *
 220 __dwc_regs(struct dw_dma_chan *dwc)
 221 {
 222         return dwc->ch_regs;
 223 }
 224
 225 #define channel_readl(dwc, name) \
 226         dma_readl_native(&(__dwc_regs(dwc)->name))
 227 #define channel_writel(dwc, name, val) \
 228         dma_writel_native((val), &(__dwc_regs(dwc)->name))
 229
 230 static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
 231 {
 232         return container_of(chan, struct dw_dma_chan, chan);
 233 }
 234
 235 struct dw_dma {
 236         struct dma_device       dma;
 237         void __iomem            *regs;
 238         struct dma_pool         *desc_pool;
 239         struct tasklet_struct   tasklet;
 240         struct clk              *clk;
 241
 242         /* slave information */
 243         struct dw_dma_slave     *sd;
 244         unsigned int            sd_count;
 245
 246         u8                      all_chan_mask;
 247
 248         /* hardware configuration */
 249         unsigned char           nr_masters;
 250         unsigned char           data_width[4];
 251
 252         struct dw_dma_chan      chan[0];
 253 };
 254
 255 static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
 256 {
 257         return dw->regs;
 258 }
 259
 260 #define dma_readl(dw, name) \
 261         dma_readl_native(&(__dw_regs(dw)->name))
 262 #define dma_writel(dw, name, val) \
 263         dma_writel_native((val), &(__dw_regs(dw)->name))
 264
 265 #define channel_set_bit(dw, reg, mask) \
 266         dma_writel(dw, reg, ((mask) << 8) | (mask))
 267 #define channel_clear_bit(dw, reg, mask) \
 268         dma_writel(dw, reg, ((mask) << 8) | 0)
 269
 270 static inline struct dw_dma *to_dw_dma(struct dma_device *ddev)
 271 {
 272         return container_of(ddev, struct dw_dma, dma);
 273 }
 274
 275 /* LLI == Linked List Item; a.k.a. DMA block descriptor */
 276 struct dw_lli {
 277         /* values that are not changed by hardware */
 278         u32             sar;
 279         u32             dar;
 280         u32             llp;            /* chain to next lli */
 281         u32             ctllo;
 282         /* values that may get written back: */
 283         u32             ctlhi;
 284         /* sstat and dstat can snapshot peripheral register state.
 285          * silicon config may discard either or both...
 286          */
 287         u32             sstat;
 288         u32             dstat;
 289 };
 290
 291 struct dw_desc {
 292         /* FIRST values the hardware uses */
 293         struct dw_lli                   lli;
 294
 295         /* THEN values for driver housekeeping */
 296         struct list_head                desc_node;
 297         struct list_head                tx_list;
 298         struct dma_async_tx_descriptor  txd;
 299         size_t                          len;
 300         size_t                          total_len;
 301 };
 302
 303 #define to_dw_desc(h)   list_entry(h, struct dw_desc, desc_node)
 304
 305 static inline struct dw_desc *
 306 txd_to_dw_desc(struct dma_async_tx_descriptor *txd)
 307 {
 308         return container_of(txd, struct dw_desc, txd);
 309 }