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dmaengine: imx-sdma: convert callback to helper function
[deliverable/linux.git] / drivers / dma / imx-sdma.c
1 /*
2 * drivers/dma/imx-sdma.c
3 *
4 * This file contains a driver for the Freescale Smart DMA engine
5 *
6 * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
7 *
8 * Based on code from Freescale:
9 *
10 * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
11 *
12 * The code contained herein is licensed under the GNU General Public
13 * License. You may obtain a copy of the GNU General Public License
14 * Version 2 or later at the following locations:
15 *
16 * http://www.opensource.org/licenses/gpl-license.html
17 * http://www.gnu.org/copyleft/gpl.html
18 */
19
20 #include <linux/init.h>
21 #include <linux/iopoll.h>
22 #include <linux/module.h>
23 #include <linux/types.h>
24 #include <linux/bitops.h>
25 #include <linux/mm.h>
26 #include <linux/interrupt.h>
27 #include <linux/clk.h>
28 #include <linux/delay.h>
29 #include <linux/sched.h>
30 #include <linux/semaphore.h>
31 #include <linux/spinlock.h>
32 #include <linux/device.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/firmware.h>
35 #include <linux/slab.h>
36 #include <linux/platform_device.h>
37 #include <linux/dmaengine.h>
38 #include <linux/of.h>
39 #include <linux/of_address.h>
40 #include <linux/of_device.h>
41 #include <linux/of_dma.h>
42
43 #include <asm/irq.h>
44 #include <linux/platform_data/dma-imx-sdma.h>
45 #include <linux/platform_data/dma-imx.h>
46 #include <linux/regmap.h>
47 #include <linux/mfd/syscon.h>
48 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
49
50 #include "dmaengine.h"
51
52 /* SDMA registers */
53 #define SDMA_H_C0PTR 0x000
54 #define SDMA_H_INTR 0x004
55 #define SDMA_H_STATSTOP 0x008
56 #define SDMA_H_START 0x00c
57 #define SDMA_H_EVTOVR 0x010
58 #define SDMA_H_DSPOVR 0x014
59 #define SDMA_H_HOSTOVR 0x018
60 #define SDMA_H_EVTPEND 0x01c
61 #define SDMA_H_DSPENBL 0x020
62 #define SDMA_H_RESET 0x024
63 #define SDMA_H_EVTERR 0x028
64 #define SDMA_H_INTRMSK 0x02c
65 #define SDMA_H_PSW 0x030
66 #define SDMA_H_EVTERRDBG 0x034
67 #define SDMA_H_CONFIG 0x038
68 #define SDMA_ONCE_ENB 0x040
69 #define SDMA_ONCE_DATA 0x044
70 #define SDMA_ONCE_INSTR 0x048
71 #define SDMA_ONCE_STAT 0x04c
72 #define SDMA_ONCE_CMD 0x050
73 #define SDMA_EVT_MIRROR 0x054
74 #define SDMA_ILLINSTADDR 0x058
75 #define SDMA_CHN0ADDR 0x05c
76 #define SDMA_ONCE_RTB 0x060
77 #define SDMA_XTRIG_CONF1 0x070
78 #define SDMA_XTRIG_CONF2 0x074
79 #define SDMA_CHNENBL0_IMX35 0x200
80 #define SDMA_CHNENBL0_IMX31 0x080
81 #define SDMA_CHNPRI_0 0x100
82
83 /*
84 * Buffer descriptor status values.
85 */
86 #define BD_DONE 0x01
87 #define BD_WRAP 0x02
88 #define BD_CONT 0x04
89 #define BD_INTR 0x08
90 #define BD_RROR 0x10
91 #define BD_LAST 0x20
92 #define BD_EXTD 0x80
93
94 /*
95 * Data Node descriptor status values.
96 */
97 #define DND_END_OF_FRAME 0x80
98 #define DND_END_OF_XFER 0x40
99 #define DND_DONE 0x20
100 #define DND_UNUSED 0x01
101
102 /*
103 * IPCV2 descriptor status values.
104 */
105 #define BD_IPCV2_END_OF_FRAME 0x40
106
107 #define IPCV2_MAX_NODES 50
108 /*
109 * Error bit set in the CCB status field by the SDMA,
110 * in setbd routine, in case of a transfer error
111 */
112 #define DATA_ERROR 0x10000000
113
114 /*
115 * Buffer descriptor commands.
116 */
117 #define C0_ADDR 0x01
118 #define C0_LOAD 0x02
119 #define C0_DUMP 0x03
120 #define C0_SETCTX 0x07
121 #define C0_GETCTX 0x03
122 #define C0_SETDM 0x01
123 #define C0_SETPM 0x04
124 #define C0_GETDM 0x02
125 #define C0_GETPM 0x08
126 /*
127 * Change endianness indicator in the BD command field
128 */
129 #define CHANGE_ENDIANNESS 0x80
130
131 /*
132 * p_2_p watermark_level description
133 * Bits Name Description
134 * 0-7 Lower WML Lower watermark level
135 * 8 PS 1: Pad Swallowing
136 * 0: No Pad Swallowing
137 * 9 PA 1: Pad Adding
138 * 0: No Pad Adding
139 * 10 SPDIF If this bit is set both source
140 * and destination are on SPBA
141 * 11 Source Bit(SP) 1: Source on SPBA
142 * 0: Source on AIPS
143 * 12 Destination Bit(DP) 1: Destination on SPBA
144 * 0: Destination on AIPS
145 * 13-15 --------- MUST BE 0
146 * 16-23 Higher WML HWML
147 * 24-27 N Total number of samples after
148 * which Pad adding/Swallowing
149 * must be done. It must be odd.
150 * 28 Lower WML Event(LWE) SDMA events reg to check for
151 * LWML event mask
152 * 0: LWE in EVENTS register
153 * 1: LWE in EVENTS2 register
154 * 29 Higher WML Event(HWE) SDMA events reg to check for
155 * HWML event mask
156 * 0: HWE in EVENTS register
157 * 1: HWE in EVENTS2 register
158 * 30 --------- MUST BE 0
159 * 31 CONT 1: Amount of samples to be
160 * transferred is unknown and
161 * script will keep on
162 * transferring samples as long as
163 * both events are detected and
164 * script must be manually stopped
165 * by the application
166 * 0: The amount of samples to be
167 * transferred is equal to the
168 * count field of mode word
169 */
170 #define SDMA_WATERMARK_LEVEL_LWML 0xFF
171 #define SDMA_WATERMARK_LEVEL_PS BIT(8)
172 #define SDMA_WATERMARK_LEVEL_PA BIT(9)
173 #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10)
174 #define SDMA_WATERMARK_LEVEL_SP BIT(11)
175 #define SDMA_WATERMARK_LEVEL_DP BIT(12)
176 #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16)
177 #define SDMA_WATERMARK_LEVEL_LWE BIT(28)
178 #define SDMA_WATERMARK_LEVEL_HWE BIT(29)
179 #define SDMA_WATERMARK_LEVEL_CONT BIT(31)
180
181 /*
182 * Mode/Count of data node descriptors - IPCv2
183 */
184 struct sdma_mode_count {
185 u32 count : 16; /* size of the buffer pointed by this BD */
186 u32 status : 8; /* E,R,I,C,W,D status bits stored here */
187 u32 command : 8; /* command mostlky used for channel 0 */
188 };
189
190 /*
191 * Buffer descriptor
192 */
193 struct sdma_buffer_descriptor {
194 struct sdma_mode_count mode;
195 u32 buffer_addr; /* address of the buffer described */
196 u32 ext_buffer_addr; /* extended buffer address */
197 } __attribute__ ((packed));
198
199 /**
200 * struct sdma_channel_control - Channel control Block
201 *
202 * @current_bd_ptr current buffer descriptor processed
203 * @base_bd_ptr first element of buffer descriptor array
204 * @unused padding. The SDMA engine expects an array of 128 byte
205 * control blocks
206 */
207 struct sdma_channel_control {
208 u32 current_bd_ptr;
209 u32 base_bd_ptr;
210 u32 unused[2];
211 } __attribute__ ((packed));
212
213 /**
214 * struct sdma_state_registers - SDMA context for a channel
215 *
216 * @pc: program counter
217 * @t: test bit: status of arithmetic & test instruction
218 * @rpc: return program counter
219 * @sf: source fault while loading data
220 * @spc: loop start program counter
221 * @df: destination fault while storing data
222 * @epc: loop end program counter
223 * @lm: loop mode
224 */
225 struct sdma_state_registers {
226 u32 pc :14;
227 u32 unused1: 1;
228 u32 t : 1;
229 u32 rpc :14;
230 u32 unused0: 1;
231 u32 sf : 1;
232 u32 spc :14;
233 u32 unused2: 1;
234 u32 df : 1;
235 u32 epc :14;
236 u32 lm : 2;
237 } __attribute__ ((packed));
238
239 /**
240 * struct sdma_context_data - sdma context specific to a channel
241 *
242 * @channel_state: channel state bits
243 * @gReg: general registers
244 * @mda: burst dma destination address register
245 * @msa: burst dma source address register
246 * @ms: burst dma status register
247 * @md: burst dma data register
248 * @pda: peripheral dma destination address register
249 * @psa: peripheral dma source address register
250 * @ps: peripheral dma status register
251 * @pd: peripheral dma data register
252 * @ca: CRC polynomial register
253 * @cs: CRC accumulator register
254 * @dda: dedicated core destination address register
255 * @dsa: dedicated core source address register
256 * @ds: dedicated core status register
257 * @dd: dedicated core data register
258 */
259 struct sdma_context_data {
260 struct sdma_state_registers channel_state;
261 u32 gReg[8];
262 u32 mda;
263 u32 msa;
264 u32 ms;
265 u32 md;
266 u32 pda;
267 u32 psa;
268 u32 ps;
269 u32 pd;
270 u32 ca;
271 u32 cs;
272 u32 dda;
273 u32 dsa;
274 u32 ds;
275 u32 dd;
276 u32 scratch0;
277 u32 scratch1;
278 u32 scratch2;
279 u32 scratch3;
280 u32 scratch4;
281 u32 scratch5;
282 u32 scratch6;
283 u32 scratch7;
284 } __attribute__ ((packed));
285
286 #define NUM_BD (int)(PAGE_SIZE / sizeof(struct sdma_buffer_descriptor))
287
288 struct sdma_engine;
289
290 /**
291 * struct sdma_channel - housekeeping for a SDMA channel
292 *
293 * @sdma pointer to the SDMA engine for this channel
294 * @channel the channel number, matches dmaengine chan_id + 1
295 * @direction transfer type. Needed for setting SDMA script
296 * @peripheral_type Peripheral type. Needed for setting SDMA script
297 * @event_id0 aka dma request line
298 * @event_id1 for channels that use 2 events
299 * @word_size peripheral access size
300 * @buf_tail ID of the buffer that was processed
301 * @num_bd max NUM_BD. number of descriptors currently handling
302 */
303 struct sdma_channel {
304 struct sdma_engine *sdma;
305 unsigned int channel;
306 enum dma_transfer_direction direction;
307 enum sdma_peripheral_type peripheral_type;
308 unsigned int event_id0;
309 unsigned int event_id1;
310 enum dma_slave_buswidth word_size;
311 unsigned int buf_tail;
312 unsigned int num_bd;
313 unsigned int period_len;
314 struct sdma_buffer_descriptor *bd;
315 dma_addr_t bd_phys;
316 unsigned int pc_from_device, pc_to_device;
317 unsigned int device_to_device;
318 unsigned long flags;
319 dma_addr_t per_address, per_address2;
320 unsigned long event_mask[2];
321 unsigned long watermark_level;
322 u32 shp_addr, per_addr;
323 struct dma_chan chan;
324 spinlock_t lock;
325 struct dma_async_tx_descriptor desc;
326 enum dma_status status;
327 unsigned int chn_count;
328 unsigned int chn_real_count;
329 struct tasklet_struct tasklet;
330 struct imx_dma_data data;
331 };
332
333 #define IMX_DMA_SG_LOOP BIT(0)
334
335 #define MAX_DMA_CHANNELS 32
336 #define MXC_SDMA_DEFAULT_PRIORITY 1
337 #define MXC_SDMA_MIN_PRIORITY 1
338 #define MXC_SDMA_MAX_PRIORITY 7
339
340 #define SDMA_FIRMWARE_MAGIC 0x414d4453
341
342 /**
343 * struct sdma_firmware_header - Layout of the firmware image
344 *
345 * @magic "SDMA"
346 * @version_major increased whenever layout of struct sdma_script_start_addrs
347 * changes.
348 * @version_minor firmware minor version (for binary compatible changes)
349 * @script_addrs_start offset of struct sdma_script_start_addrs in this image
350 * @num_script_addrs Number of script addresses in this image
351 * @ram_code_start offset of SDMA ram image in this firmware image
352 * @ram_code_size size of SDMA ram image
353 * @script_addrs Stores the start address of the SDMA scripts
354 * (in SDMA memory space)
355 */
356 struct sdma_firmware_header {
357 u32 magic;
358 u32 version_major;
359 u32 version_minor;
360 u32 script_addrs_start;
361 u32 num_script_addrs;
362 u32 ram_code_start;
363 u32 ram_code_size;
364 };
365
366 struct sdma_driver_data {
367 int chnenbl0;
368 int num_events;
369 struct sdma_script_start_addrs *script_addrs;
370 };
371
372 struct sdma_engine {
373 struct device *dev;
374 struct device_dma_parameters dma_parms;
375 struct sdma_channel channel[MAX_DMA_CHANNELS];
376 struct sdma_channel_control *channel_control;
377 void __iomem *regs;
378 struct sdma_context_data *context;
379 dma_addr_t context_phys;
380 struct dma_device dma_device;
381 struct clk *clk_ipg;
382 struct clk *clk_ahb;
383 spinlock_t channel_0_lock;
384 u32 script_number;
385 struct sdma_script_start_addrs *script_addrs;
386 const struct sdma_driver_data *drvdata;
387 u32 spba_start_addr;
388 u32 spba_end_addr;
389 unsigned int irq;
390 };
391
392 static struct sdma_driver_data sdma_imx31 = {
393 .chnenbl0 = SDMA_CHNENBL0_IMX31,
394 .num_events = 32,
395 };
396
397 static struct sdma_script_start_addrs sdma_script_imx25 = {
398 .ap_2_ap_addr = 729,
399 .uart_2_mcu_addr = 904,
400 .per_2_app_addr = 1255,
401 .mcu_2_app_addr = 834,
402 .uartsh_2_mcu_addr = 1120,
403 .per_2_shp_addr = 1329,
404 .mcu_2_shp_addr = 1048,
405 .ata_2_mcu_addr = 1560,
406 .mcu_2_ata_addr = 1479,
407 .app_2_per_addr = 1189,
408 .app_2_mcu_addr = 770,
409 .shp_2_per_addr = 1407,
410 .shp_2_mcu_addr = 979,
411 };
412
413 static struct sdma_driver_data sdma_imx25 = {
414 .chnenbl0 = SDMA_CHNENBL0_IMX35,
415 .num_events = 48,
416 .script_addrs = &sdma_script_imx25,
417 };
418
419 static struct sdma_driver_data sdma_imx35 = {
420 .chnenbl0 = SDMA_CHNENBL0_IMX35,
421 .num_events = 48,
422 };
423
424 static struct sdma_script_start_addrs sdma_script_imx51 = {
425 .ap_2_ap_addr = 642,
426 .uart_2_mcu_addr = 817,
427 .mcu_2_app_addr = 747,
428 .mcu_2_shp_addr = 961,
429 .ata_2_mcu_addr = 1473,
430 .mcu_2_ata_addr = 1392,
431 .app_2_per_addr = 1033,
432 .app_2_mcu_addr = 683,
433 .shp_2_per_addr = 1251,
434 .shp_2_mcu_addr = 892,
435 };
436
437 static struct sdma_driver_data sdma_imx51 = {
438 .chnenbl0 = SDMA_CHNENBL0_IMX35,
439 .num_events = 48,
440 .script_addrs = &sdma_script_imx51,
441 };
442
443 static struct sdma_script_start_addrs sdma_script_imx53 = {
444 .ap_2_ap_addr = 642,
445 .app_2_mcu_addr = 683,
446 .mcu_2_app_addr = 747,
447 .uart_2_mcu_addr = 817,
448 .shp_2_mcu_addr = 891,
449 .mcu_2_shp_addr = 960,
450 .uartsh_2_mcu_addr = 1032,
451 .spdif_2_mcu_addr = 1100,
452 .mcu_2_spdif_addr = 1134,
453 .firi_2_mcu_addr = 1193,
454 .mcu_2_firi_addr = 1290,
455 };
456
457 static struct sdma_driver_data sdma_imx53 = {
458 .chnenbl0 = SDMA_CHNENBL0_IMX35,
459 .num_events = 48,
460 .script_addrs = &sdma_script_imx53,
461 };
462
463 static struct sdma_script_start_addrs sdma_script_imx6q = {
464 .ap_2_ap_addr = 642,
465 .uart_2_mcu_addr = 817,
466 .mcu_2_app_addr = 747,
467 .per_2_per_addr = 6331,
468 .uartsh_2_mcu_addr = 1032,
469 .mcu_2_shp_addr = 960,
470 .app_2_mcu_addr = 683,
471 .shp_2_mcu_addr = 891,
472 .spdif_2_mcu_addr = 1100,
473 .mcu_2_spdif_addr = 1134,
474 };
475
476 static struct sdma_driver_data sdma_imx6q = {
477 .chnenbl0 = SDMA_CHNENBL0_IMX35,
478 .num_events = 48,
479 .script_addrs = &sdma_script_imx6q,
480 };
481
482 static const struct platform_device_id sdma_devtypes[] = {
483 {
484 .name = "imx25-sdma",
485 .driver_data = (unsigned long)&sdma_imx25,
486 }, {
487 .name = "imx31-sdma",
488 .driver_data = (unsigned long)&sdma_imx31,
489 }, {
490 .name = "imx35-sdma",
491 .driver_data = (unsigned long)&sdma_imx35,
492 }, {
493 .name = "imx51-sdma",
494 .driver_data = (unsigned long)&sdma_imx51,
495 }, {
496 .name = "imx53-sdma",
497 .driver_data = (unsigned long)&sdma_imx53,
498 }, {
499 .name = "imx6q-sdma",
500 .driver_data = (unsigned long)&sdma_imx6q,
501 }, {
502 /* sentinel */
503 }
504 };
505 MODULE_DEVICE_TABLE(platform, sdma_devtypes);
506
507 static const struct of_device_id sdma_dt_ids[] = {
508 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
509 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
510 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
511 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
512 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
513 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
514 { /* sentinel */ }
515 };
516 MODULE_DEVICE_TABLE(of, sdma_dt_ids);
517
518 #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */
519 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
520 #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */
521 #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
522
523 static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
524 {
525 u32 chnenbl0 = sdma->drvdata->chnenbl0;
526 return chnenbl0 + event * 4;
527 }
528
529 static int sdma_config_ownership(struct sdma_channel *sdmac,
530 bool event_override, bool mcu_override, bool dsp_override)
531 {
532 struct sdma_engine *sdma = sdmac->sdma;
533 int channel = sdmac->channel;
534 unsigned long evt, mcu, dsp;
535
536 if (event_override && mcu_override && dsp_override)
537 return -EINVAL;
538
539 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
540 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
541 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
542
543 if (dsp_override)
544 __clear_bit(channel, &dsp);
545 else
546 __set_bit(channel, &dsp);
547
548 if (event_override)
549 __clear_bit(channel, &evt);
550 else
551 __set_bit(channel, &evt);
552
553 if (mcu_override)
554 __clear_bit(channel, &mcu);
555 else
556 __set_bit(channel, &mcu);
557
558 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
559 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
560 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
561
562 return 0;
563 }
564
565 static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
566 {
567 writel(BIT(channel), sdma->regs + SDMA_H_START);
568 }
569
570 /*
571 * sdma_run_channel0 - run a channel and wait till it's done
572 */
573 static int sdma_run_channel0(struct sdma_engine *sdma)
574 {
575 int ret;
576 u32 reg;
577
578 sdma_enable_channel(sdma, 0);
579
580 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
581 reg, !(reg & 1), 1, 500);
582 if (ret)
583 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
584
585 /* Set bits of CONFIG register with dynamic context switching */
586 if (readl(sdma->regs + SDMA_H_CONFIG) == 0)
587 writel_relaxed(SDMA_H_CONFIG_CSM, sdma->regs + SDMA_H_CONFIG);
588
589 return ret;
590 }
591
592 static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
593 u32 address)
594 {
595 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
596 void *buf_virt;
597 dma_addr_t buf_phys;
598 int ret;
599 unsigned long flags;
600
601 buf_virt = dma_alloc_coherent(NULL,
602 size,
603 &buf_phys, GFP_KERNEL);
604 if (!buf_virt) {
605 return -ENOMEM;
606 }
607
608 spin_lock_irqsave(&sdma->channel_0_lock, flags);
609
610 bd0->mode.command = C0_SETPM;
611 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
612 bd0->mode.count = size / 2;
613 bd0->buffer_addr = buf_phys;
614 bd0->ext_buffer_addr = address;
615
616 memcpy(buf_virt, buf, size);
617
618 ret = sdma_run_channel0(sdma);
619
620 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
621
622 dma_free_coherent(NULL, size, buf_virt, buf_phys);
623
624 return ret;
625 }
626
627 static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
628 {
629 struct sdma_engine *sdma = sdmac->sdma;
630 int channel = sdmac->channel;
631 unsigned long val;
632 u32 chnenbl = chnenbl_ofs(sdma, event);
633
634 val = readl_relaxed(sdma->regs + chnenbl);
635 __set_bit(channel, &val);
636 writel_relaxed(val, sdma->regs + chnenbl);
637 }
638
639 static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
640 {
641 struct sdma_engine *sdma = sdmac->sdma;
642 int channel = sdmac->channel;
643 u32 chnenbl = chnenbl_ofs(sdma, event);
644 unsigned long val;
645
646 val = readl_relaxed(sdma->regs + chnenbl);
647 __clear_bit(channel, &val);
648 writel_relaxed(val, sdma->regs + chnenbl);
649 }
650
651 static void sdma_handle_channel_loop(struct sdma_channel *sdmac)
652 {
653 dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL);
654 }
655
656 static void sdma_update_channel_loop(struct sdma_channel *sdmac)
657 {
658 struct sdma_buffer_descriptor *bd;
659
660 /*
661 * loop mode. Iterate over descriptors, re-setup them and
662 * call callback function.
663 */
664 while (1) {
665 bd = &sdmac->bd[sdmac->buf_tail];
666
667 if (bd->mode.status & BD_DONE)
668 break;
669
670 if (bd->mode.status & BD_RROR)
671 sdmac->status = DMA_ERROR;
672
673 bd->mode.status |= BD_DONE;
674 sdmac->buf_tail++;
675 sdmac->buf_tail %= sdmac->num_bd;
676 }
677 }
678
679 static void mxc_sdma_handle_channel_normal(struct sdma_channel *sdmac)
680 {
681 struct sdma_buffer_descriptor *bd;
682 int i, error = 0;
683
684 sdmac->chn_real_count = 0;
685 /*
686 * non loop mode. Iterate over all descriptors, collect
687 * errors and call callback function
688 */
689 for (i = 0; i < sdmac->num_bd; i++) {
690 bd = &sdmac->bd[i];
691
692 if (bd->mode.status & (BD_DONE | BD_RROR))
693 error = -EIO;
694 sdmac->chn_real_count += bd->mode.count;
695 }
696
697 if (error)
698 sdmac->status = DMA_ERROR;
699 else
700 sdmac->status = DMA_COMPLETE;
701
702 dma_cookie_complete(&sdmac->desc);
703
704 dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL);
705 }
706
707 static void sdma_tasklet(unsigned long data)
708 {
709 struct sdma_channel *sdmac = (struct sdma_channel *) data;
710
711 if (sdmac->flags & IMX_DMA_SG_LOOP)
712 sdma_handle_channel_loop(sdmac);
713 else
714 mxc_sdma_handle_channel_normal(sdmac);
715 }
716
717 static irqreturn_t sdma_int_handler(int irq, void *dev_id)
718 {
719 struct sdma_engine *sdma = dev_id;
720 unsigned long stat;
721
722 stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
723 writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
724 /* channel 0 is special and not handled here, see run_channel0() */
725 stat &= ~1;
726
727 while (stat) {
728 int channel = fls(stat) - 1;
729 struct sdma_channel *sdmac = &sdma->channel[channel];
730
731 if (sdmac->flags & IMX_DMA_SG_LOOP)
732 sdma_update_channel_loop(sdmac);
733
734 tasklet_schedule(&sdmac->tasklet);
735
736 __clear_bit(channel, &stat);
737 }
738
739 return IRQ_HANDLED;
740 }
741
742 /*
743 * sets the pc of SDMA script according to the peripheral type
744 */
745 static void sdma_get_pc(struct sdma_channel *sdmac,
746 enum sdma_peripheral_type peripheral_type)
747 {
748 struct sdma_engine *sdma = sdmac->sdma;
749 int per_2_emi = 0, emi_2_per = 0;
750 /*
751 * These are needed once we start to support transfers between
752 * two peripherals or memory-to-memory transfers
753 */
754 int per_2_per = 0;
755
756 sdmac->pc_from_device = 0;
757 sdmac->pc_to_device = 0;
758 sdmac->device_to_device = 0;
759
760 switch (peripheral_type) {
761 case IMX_DMATYPE_MEMORY:
762 break;
763 case IMX_DMATYPE_DSP:
764 emi_2_per = sdma->script_addrs->bp_2_ap_addr;
765 per_2_emi = sdma->script_addrs->ap_2_bp_addr;
766 break;
767 case IMX_DMATYPE_FIRI:
768 per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
769 emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
770 break;
771 case IMX_DMATYPE_UART:
772 per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
773 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
774 break;
775 case IMX_DMATYPE_UART_SP:
776 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
777 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
778 break;
779 case IMX_DMATYPE_ATA:
780 per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
781 emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
782 break;
783 case IMX_DMATYPE_CSPI:
784 case IMX_DMATYPE_EXT:
785 case IMX_DMATYPE_SSI:
786 case IMX_DMATYPE_SAI:
787 per_2_emi = sdma->script_addrs->app_2_mcu_addr;
788 emi_2_per = sdma->script_addrs->mcu_2_app_addr;
789 break;
790 case IMX_DMATYPE_SSI_DUAL:
791 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
792 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
793 break;
794 case IMX_DMATYPE_SSI_SP:
795 case IMX_DMATYPE_MMC:
796 case IMX_DMATYPE_SDHC:
797 case IMX_DMATYPE_CSPI_SP:
798 case IMX_DMATYPE_ESAI:
799 case IMX_DMATYPE_MSHC_SP:
800 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
801 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
802 break;
803 case IMX_DMATYPE_ASRC:
804 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
805 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
806 per_2_per = sdma->script_addrs->per_2_per_addr;
807 break;
808 case IMX_DMATYPE_ASRC_SP:
809 per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
810 emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
811 per_2_per = sdma->script_addrs->per_2_per_addr;
812 break;
813 case IMX_DMATYPE_MSHC:
814 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
815 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
816 break;
817 case IMX_DMATYPE_CCM:
818 per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
819 break;
820 case IMX_DMATYPE_SPDIF:
821 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
822 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
823 break;
824 case IMX_DMATYPE_IPU_MEMORY:
825 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
826 break;
827 default:
828 break;
829 }
830
831 sdmac->pc_from_device = per_2_emi;
832 sdmac->pc_to_device = emi_2_per;
833 sdmac->device_to_device = per_2_per;
834 }
835
836 static int sdma_load_context(struct sdma_channel *sdmac)
837 {
838 struct sdma_engine *sdma = sdmac->sdma;
839 int channel = sdmac->channel;
840 int load_address;
841 struct sdma_context_data *context = sdma->context;
842 struct sdma_buffer_descriptor *bd0 = sdma->channel[0].bd;
843 int ret;
844 unsigned long flags;
845
846 if (sdmac->direction == DMA_DEV_TO_MEM)
847 load_address = sdmac->pc_from_device;
848 else if (sdmac->direction == DMA_DEV_TO_DEV)
849 load_address = sdmac->device_to_device;
850 else
851 load_address = sdmac->pc_to_device;
852
853 if (load_address < 0)
854 return load_address;
855
856 dev_dbg(sdma->dev, "load_address = %d\n", load_address);
857 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
858 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
859 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
860 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
861 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
862
863 spin_lock_irqsave(&sdma->channel_0_lock, flags);
864
865 memset(context, 0, sizeof(*context));
866 context->channel_state.pc = load_address;
867
868 /* Send by context the event mask,base address for peripheral
869 * and watermark level
870 */
871 context->gReg[0] = sdmac->event_mask[1];
872 context->gReg[1] = sdmac->event_mask[0];
873 context->gReg[2] = sdmac->per_addr;
874 context->gReg[6] = sdmac->shp_addr;
875 context->gReg[7] = sdmac->watermark_level;
876
877 bd0->mode.command = C0_SETDM;
878 bd0->mode.status = BD_DONE | BD_INTR | BD_WRAP | BD_EXTD;
879 bd0->mode.count = sizeof(*context) / 4;
880 bd0->buffer_addr = sdma->context_phys;
881 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
882 ret = sdma_run_channel0(sdma);
883
884 spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
885
886 return ret;
887 }
888
889 static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
890 {
891 return container_of(chan, struct sdma_channel, chan);
892 }
893
894 static int sdma_disable_channel(struct dma_chan *chan)
895 {
896 struct sdma_channel *sdmac = to_sdma_chan(chan);
897 struct sdma_engine *sdma = sdmac->sdma;
898 int channel = sdmac->channel;
899
900 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
901 sdmac->status = DMA_ERROR;
902
903 return 0;
904 }
905
906 static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
907 {
908 struct sdma_engine *sdma = sdmac->sdma;
909
910 int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
911 int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;
912
913 set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
914 set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);
915
916 if (sdmac->event_id0 > 31)
917 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;
918
919 if (sdmac->event_id1 > 31)
920 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;
921
922 /*
923 * If LWML(src_maxburst) > HWML(dst_maxburst), we need
924 * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
925 * r0(event_mask[1]) and r1(event_mask[0]).
926 */
927 if (lwml > hwml) {
928 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
929 SDMA_WATERMARK_LEVEL_HWML);
930 sdmac->watermark_level |= hwml;
931 sdmac->watermark_level |= lwml << 16;
932 swap(sdmac->event_mask[0], sdmac->event_mask[1]);
933 }
934
935 if (sdmac->per_address2 >= sdma->spba_start_addr &&
936 sdmac->per_address2 <= sdma->spba_end_addr)
937 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;
938
939 if (sdmac->per_address >= sdma->spba_start_addr &&
940 sdmac->per_address <= sdma->spba_end_addr)
941 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
942
943 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
944 }
945
946 static int sdma_config_channel(struct dma_chan *chan)
947 {
948 struct sdma_channel *sdmac = to_sdma_chan(chan);
949 int ret;
950
951 sdma_disable_channel(chan);
952
953 sdmac->event_mask[0] = 0;
954 sdmac->event_mask[1] = 0;
955 sdmac->shp_addr = 0;
956 sdmac->per_addr = 0;
957
958 if (sdmac->event_id0) {
959 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
960 return -EINVAL;
961 sdma_event_enable(sdmac, sdmac->event_id0);
962 }
963
964 if (sdmac->event_id1) {
965 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
966 return -EINVAL;
967 sdma_event_enable(sdmac, sdmac->event_id1);
968 }
969
970 switch (sdmac->peripheral_type) {
971 case IMX_DMATYPE_DSP:
972 sdma_config_ownership(sdmac, false, true, true);
973 break;
974 case IMX_DMATYPE_MEMORY:
975 sdma_config_ownership(sdmac, false, true, false);
976 break;
977 default:
978 sdma_config_ownership(sdmac, true, true, false);
979 break;
980 }
981
982 sdma_get_pc(sdmac, sdmac->peripheral_type);
983
984 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
985 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
986 /* Handle multiple event channels differently */
987 if (sdmac->event_id1) {
988 if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
989 sdmac->peripheral_type == IMX_DMATYPE_ASRC)
990 sdma_set_watermarklevel_for_p2p(sdmac);
991 } else
992 __set_bit(sdmac->event_id0, sdmac->event_mask);
993
994 /* Address */
995 sdmac->shp_addr = sdmac->per_address;
996 sdmac->per_addr = sdmac->per_address2;
997 } else {
998 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
999 }
1000
1001 ret = sdma_load_context(sdmac);
1002
1003 return ret;
1004 }
1005
1006 static int sdma_set_channel_priority(struct sdma_channel *sdmac,
1007 unsigned int priority)
1008 {
1009 struct sdma_engine *sdma = sdmac->sdma;
1010 int channel = sdmac->channel;
1011
1012 if (priority < MXC_SDMA_MIN_PRIORITY
1013 || priority > MXC_SDMA_MAX_PRIORITY) {
1014 return -EINVAL;
1015 }
1016
1017 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
1018
1019 return 0;
1020 }
1021
1022 static int sdma_request_channel(struct sdma_channel *sdmac)
1023 {
1024 struct sdma_engine *sdma = sdmac->sdma;
1025 int channel = sdmac->channel;
1026 int ret = -EBUSY;
1027
1028 sdmac->bd = dma_zalloc_coherent(NULL, PAGE_SIZE, &sdmac->bd_phys,
1029 GFP_KERNEL);
1030 if (!sdmac->bd) {
1031 ret = -ENOMEM;
1032 goto out;
1033 }
1034
1035 sdma->channel_control[channel].base_bd_ptr = sdmac->bd_phys;
1036 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1037
1038 sdma_set_channel_priority(sdmac, MXC_SDMA_DEFAULT_PRIORITY);
1039 return 0;
1040 out:
1041
1042 return ret;
1043 }
1044
1045 static dma_cookie_t sdma_tx_submit(struct dma_async_tx_descriptor *tx)
1046 {
1047 unsigned long flags;
1048 struct sdma_channel *sdmac = to_sdma_chan(tx->chan);
1049 dma_cookie_t cookie;
1050
1051 spin_lock_irqsave(&sdmac->lock, flags);
1052
1053 cookie = dma_cookie_assign(tx);
1054
1055 spin_unlock_irqrestore(&sdmac->lock, flags);
1056
1057 return cookie;
1058 }
1059
1060 static int sdma_alloc_chan_resources(struct dma_chan *chan)
1061 {
1062 struct sdma_channel *sdmac = to_sdma_chan(chan);
1063 struct imx_dma_data *data = chan->private;
1064 int prio, ret;
1065
1066 if (!data)
1067 return -EINVAL;
1068
1069 switch (data->priority) {
1070 case DMA_PRIO_HIGH:
1071 prio = 3;
1072 break;
1073 case DMA_PRIO_MEDIUM:
1074 prio = 2;
1075 break;
1076 case DMA_PRIO_LOW:
1077 default:
1078 prio = 1;
1079 break;
1080 }
1081
1082 sdmac->peripheral_type = data->peripheral_type;
1083 sdmac->event_id0 = data->dma_request;
1084 sdmac->event_id1 = data->dma_request2;
1085
1086 ret = clk_enable(sdmac->sdma->clk_ipg);
1087 if (ret)
1088 return ret;
1089 ret = clk_enable(sdmac->sdma->clk_ahb);
1090 if (ret)
1091 goto disable_clk_ipg;
1092
1093 ret = sdma_request_channel(sdmac);
1094 if (ret)
1095 goto disable_clk_ahb;
1096
1097 ret = sdma_set_channel_priority(sdmac, prio);
1098 if (ret)
1099 goto disable_clk_ahb;
1100
1101 dma_async_tx_descriptor_init(&sdmac->desc, chan);
1102 sdmac->desc.tx_submit = sdma_tx_submit;
1103 /* txd.flags will be overwritten in prep funcs */
1104 sdmac->desc.flags = DMA_CTRL_ACK;
1105
1106 return 0;
1107
1108 disable_clk_ahb:
1109 clk_disable(sdmac->sdma->clk_ahb);
1110 disable_clk_ipg:
1111 clk_disable(sdmac->sdma->clk_ipg);
1112 return ret;
1113 }
1114
1115 static void sdma_free_chan_resources(struct dma_chan *chan)
1116 {
1117 struct sdma_channel *sdmac = to_sdma_chan(chan);
1118 struct sdma_engine *sdma = sdmac->sdma;
1119
1120 sdma_disable_channel(chan);
1121
1122 if (sdmac->event_id0)
1123 sdma_event_disable(sdmac, sdmac->event_id0);
1124 if (sdmac->event_id1)
1125 sdma_event_disable(sdmac, sdmac->event_id1);
1126
1127 sdmac->event_id0 = 0;
1128 sdmac->event_id1 = 0;
1129
1130 sdma_set_channel_priority(sdmac, 0);
1131
1132 dma_free_coherent(NULL, PAGE_SIZE, sdmac->bd, sdmac->bd_phys);
1133
1134 clk_disable(sdma->clk_ipg);
1135 clk_disable(sdma->clk_ahb);
1136 }
1137
1138 static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
1139 struct dma_chan *chan, struct scatterlist *sgl,
1140 unsigned int sg_len, enum dma_transfer_direction direction,
1141 unsigned long flags, void *context)
1142 {
1143 struct sdma_channel *sdmac = to_sdma_chan(chan);
1144 struct sdma_engine *sdma = sdmac->sdma;
1145 int ret, i, count;
1146 int channel = sdmac->channel;
1147 struct scatterlist *sg;
1148
1149 if (sdmac->status == DMA_IN_PROGRESS)
1150 return NULL;
1151 sdmac->status = DMA_IN_PROGRESS;
1152
1153 sdmac->flags = 0;
1154
1155 sdmac->buf_tail = 0;
1156
1157 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
1158 sg_len, channel);
1159
1160 sdmac->direction = direction;
1161 ret = sdma_load_context(sdmac);
1162 if (ret)
1163 goto err_out;
1164
1165 if (sg_len > NUM_BD) {
1166 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1167 channel, sg_len, NUM_BD);
1168 ret = -EINVAL;
1169 goto err_out;
1170 }
1171
1172 sdmac->chn_count = 0;
1173 for_each_sg(sgl, sg, sg_len, i) {
1174 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1175 int param;
1176
1177 bd->buffer_addr = sg->dma_address;
1178
1179 count = sg_dma_len(sg);
1180
1181 if (count > 0xffff) {
1182 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
1183 channel, count, 0xffff);
1184 ret = -EINVAL;
1185 goto err_out;
1186 }
1187
1188 bd->mode.count = count;
1189 sdmac->chn_count += count;
1190
1191 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) {
1192 ret = -EINVAL;
1193 goto err_out;
1194 }
1195
1196 switch (sdmac->word_size) {
1197 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1198 bd->mode.command = 0;
1199 if (count & 3 || sg->dma_address & 3)
1200 return NULL;
1201 break;
1202 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1203 bd->mode.command = 2;
1204 if (count & 1 || sg->dma_address & 1)
1205 return NULL;
1206 break;
1207 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1208 bd->mode.command = 1;
1209 break;
1210 default:
1211 return NULL;
1212 }
1213
1214 param = BD_DONE | BD_EXTD | BD_CONT;
1215
1216 if (i + 1 == sg_len) {
1217 param |= BD_INTR;
1218 param |= BD_LAST;
1219 param &= ~BD_CONT;
1220 }
1221
1222 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1223 i, count, (u64)sg->dma_address,
1224 param & BD_WRAP ? "wrap" : "",
1225 param & BD_INTR ? " intr" : "");
1226
1227 bd->mode.status = param;
1228 }
1229
1230 sdmac->num_bd = sg_len;
1231 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1232
1233 return &sdmac->desc;
1234 err_out:
1235 sdmac->status = DMA_ERROR;
1236 return NULL;
1237 }
1238
1239 static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
1240 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
1241 size_t period_len, enum dma_transfer_direction direction,
1242 unsigned long flags)
1243 {
1244 struct sdma_channel *sdmac = to_sdma_chan(chan);
1245 struct sdma_engine *sdma = sdmac->sdma;
1246 int num_periods = buf_len / period_len;
1247 int channel = sdmac->channel;
1248 int ret, i = 0, buf = 0;
1249
1250 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
1251
1252 if (sdmac->status == DMA_IN_PROGRESS)
1253 return NULL;
1254
1255 sdmac->status = DMA_IN_PROGRESS;
1256
1257 sdmac->buf_tail = 0;
1258 sdmac->period_len = period_len;
1259
1260 sdmac->flags |= IMX_DMA_SG_LOOP;
1261 sdmac->direction = direction;
1262 ret = sdma_load_context(sdmac);
1263 if (ret)
1264 goto err_out;
1265
1266 if (num_periods > NUM_BD) {
1267 dev_err(sdma->dev, "SDMA channel %d: maximum number of sg exceeded: %d > %d\n",
1268 channel, num_periods, NUM_BD);
1269 goto err_out;
1270 }
1271
1272 if (period_len > 0xffff) {
1273 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %d > %d\n",
1274 channel, period_len, 0xffff);
1275 goto err_out;
1276 }
1277
1278 while (buf < buf_len) {
1279 struct sdma_buffer_descriptor *bd = &sdmac->bd[i];
1280 int param;
1281
1282 bd->buffer_addr = dma_addr;
1283
1284 bd->mode.count = period_len;
1285
1286 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
1287 goto err_out;
1288 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
1289 bd->mode.command = 0;
1290 else
1291 bd->mode.command = sdmac->word_size;
1292
1293 param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
1294 if (i + 1 == num_periods)
1295 param |= BD_WRAP;
1296
1297 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
1298 i, period_len, (u64)dma_addr,
1299 param & BD_WRAP ? "wrap" : "",
1300 param & BD_INTR ? " intr" : "");
1301
1302 bd->mode.status = param;
1303
1304 dma_addr += period_len;
1305 buf += period_len;
1306
1307 i++;
1308 }
1309
1310 sdmac->num_bd = num_periods;
1311 sdma->channel_control[channel].current_bd_ptr = sdmac->bd_phys;
1312
1313 return &sdmac->desc;
1314 err_out:
1315 sdmac->status = DMA_ERROR;
1316 return NULL;
1317 }
1318
1319 static int sdma_config(struct dma_chan *chan,
1320 struct dma_slave_config *dmaengine_cfg)
1321 {
1322 struct sdma_channel *sdmac = to_sdma_chan(chan);
1323
1324 if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
1325 sdmac->per_address = dmaengine_cfg->src_addr;
1326 sdmac->watermark_level = dmaengine_cfg->src_maxburst *
1327 dmaengine_cfg->src_addr_width;
1328 sdmac->word_size = dmaengine_cfg->src_addr_width;
1329 } else if (dmaengine_cfg->direction == DMA_DEV_TO_DEV) {
1330 sdmac->per_address2 = dmaengine_cfg->src_addr;
1331 sdmac->per_address = dmaengine_cfg->dst_addr;
1332 sdmac->watermark_level = dmaengine_cfg->src_maxburst &
1333 SDMA_WATERMARK_LEVEL_LWML;
1334 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
1335 SDMA_WATERMARK_LEVEL_HWML;
1336 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1337 } else {
1338 sdmac->per_address = dmaengine_cfg->dst_addr;
1339 sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
1340 dmaengine_cfg->dst_addr_width;
1341 sdmac->word_size = dmaengine_cfg->dst_addr_width;
1342 }
1343 sdmac->direction = dmaengine_cfg->direction;
1344 return sdma_config_channel(chan);
1345 }
1346
1347 static enum dma_status sdma_tx_status(struct dma_chan *chan,
1348 dma_cookie_t cookie,
1349 struct dma_tx_state *txstate)
1350 {
1351 struct sdma_channel *sdmac = to_sdma_chan(chan);
1352 u32 residue;
1353
1354 if (sdmac->flags & IMX_DMA_SG_LOOP)
1355 residue = (sdmac->num_bd - sdmac->buf_tail) * sdmac->period_len;
1356 else
1357 residue = sdmac->chn_count - sdmac->chn_real_count;
1358
1359 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
1360 residue);
1361
1362 return sdmac->status;
1363 }
1364
1365 static void sdma_issue_pending(struct dma_chan *chan)
1366 {
1367 struct sdma_channel *sdmac = to_sdma_chan(chan);
1368 struct sdma_engine *sdma = sdmac->sdma;
1369
1370 if (sdmac->status == DMA_IN_PROGRESS)
1371 sdma_enable_channel(sdma, sdmac->channel);
1372 }
1373
1374 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
1375 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
1376 #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
1377
1378 static void sdma_add_scripts(struct sdma_engine *sdma,
1379 const struct sdma_script_start_addrs *addr)
1380 {
1381 s32 *addr_arr = (u32 *)addr;
1382 s32 *saddr_arr = (u32 *)sdma->script_addrs;
1383 int i;
1384
1385 /* use the default firmware in ROM if missing external firmware */
1386 if (!sdma->script_number)
1387 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1388
1389 for (i = 0; i < sdma->script_number; i++)
1390 if (addr_arr[i] > 0)
1391 saddr_arr[i] = addr_arr[i];
1392 }
1393
1394 static void sdma_load_firmware(const struct firmware *fw, void *context)
1395 {
1396 struct sdma_engine *sdma = context;
1397 const struct sdma_firmware_header *header;
1398 const struct sdma_script_start_addrs *addr;
1399 unsigned short *ram_code;
1400
1401 if (!fw) {
1402 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
1403 /* In this case we just use the ROM firmware. */
1404 return;
1405 }
1406
1407 if (fw->size < sizeof(*header))
1408 goto err_firmware;
1409
1410 header = (struct sdma_firmware_header *)fw->data;
1411
1412 if (header->magic != SDMA_FIRMWARE_MAGIC)
1413 goto err_firmware;
1414 if (header->ram_code_start + header->ram_code_size > fw->size)
1415 goto err_firmware;
1416 switch (header->version_major) {
1417 case 1:
1418 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
1419 break;
1420 case 2:
1421 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
1422 break;
1423 case 3:
1424 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
1425 break;
1426 default:
1427 dev_err(sdma->dev, "unknown firmware version\n");
1428 goto err_firmware;
1429 }
1430
1431 addr = (void *)header + header->script_addrs_start;
1432 ram_code = (void *)header + header->ram_code_start;
1433
1434 clk_enable(sdma->clk_ipg);
1435 clk_enable(sdma->clk_ahb);
1436 /* download the RAM image for SDMA */
1437 sdma_load_script(sdma, ram_code,
1438 header->ram_code_size,
1439 addr->ram_code_start_addr);
1440 clk_disable(sdma->clk_ipg);
1441 clk_disable(sdma->clk_ahb);
1442
1443 sdma_add_scripts(sdma, addr);
1444
1445 dev_info(sdma->dev, "loaded firmware %d.%d\n",
1446 header->version_major,
1447 header->version_minor);
1448
1449 err_firmware:
1450 release_firmware(fw);
1451 }
1452
1453 #define EVENT_REMAP_CELLS 3
1454
1455 static int sdma_event_remap(struct sdma_engine *sdma)
1456 {
1457 struct device_node *np = sdma->dev->of_node;
1458 struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
1459 struct property *event_remap;
1460 struct regmap *gpr;
1461 char propname[] = "fsl,sdma-event-remap";
1462 u32 reg, val, shift, num_map, i;
1463 int ret = 0;
1464
1465 if (IS_ERR(np) || IS_ERR(gpr_np))
1466 goto out;
1467
1468 event_remap = of_find_property(np, propname, NULL);
1469 num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
1470 if (!num_map) {
1471 dev_dbg(sdma->dev, "no event needs to be remapped\n");
1472 goto out;
1473 } else if (num_map % EVENT_REMAP_CELLS) {
1474 dev_err(sdma->dev, "the property %s must modulo %d\n",
1475 propname, EVENT_REMAP_CELLS);
1476 ret = -EINVAL;
1477 goto out;
1478 }
1479
1480 gpr = syscon_node_to_regmap(gpr_np);
1481 if (IS_ERR(gpr)) {
1482 dev_err(sdma->dev, "failed to get gpr regmap\n");
1483 ret = PTR_ERR(gpr);
1484 goto out;
1485 }
1486
1487 for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
1488 ret = of_property_read_u32_index(np, propname, i, &reg);
1489 if (ret) {
1490 dev_err(sdma->dev, "failed to read property %s index %d\n",
1491 propname, i);
1492 goto out;
1493 }
1494
1495 ret = of_property_read_u32_index(np, propname, i + 1, &shift);
1496 if (ret) {
1497 dev_err(sdma->dev, "failed to read property %s index %d\n",
1498 propname, i + 1);
1499 goto out;
1500 }
1501
1502 ret = of_property_read_u32_index(np, propname, i + 2, &val);
1503 if (ret) {
1504 dev_err(sdma->dev, "failed to read property %s index %d\n",
1505 propname, i + 2);
1506 goto out;
1507 }
1508
1509 regmap_update_bits(gpr, reg, BIT(shift), val << shift);
1510 }
1511
1512 out:
1513 if (!IS_ERR(gpr_np))
1514 of_node_put(gpr_np);
1515
1516 return ret;
1517 }
1518
1519 static int sdma_get_firmware(struct sdma_engine *sdma,
1520 const char *fw_name)
1521 {
1522 int ret;
1523
1524 ret = request_firmware_nowait(THIS_MODULE,
1525 FW_ACTION_HOTPLUG, fw_name, sdma->dev,
1526 GFP_KERNEL, sdma, sdma_load_firmware);
1527
1528 return ret;
1529 }
1530
1531 static int sdma_init(struct sdma_engine *sdma)
1532 {
1533 int i, ret;
1534 dma_addr_t ccb_phys;
1535
1536 ret = clk_enable(sdma->clk_ipg);
1537 if (ret)
1538 return ret;
1539 ret = clk_enable(sdma->clk_ahb);
1540 if (ret)
1541 goto disable_clk_ipg;
1542
1543 /* Be sure SDMA has not started yet */
1544 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
1545
1546 sdma->channel_control = dma_alloc_coherent(NULL,
1547 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
1548 sizeof(struct sdma_context_data),
1549 &ccb_phys, GFP_KERNEL);
1550
1551 if (!sdma->channel_control) {
1552 ret = -ENOMEM;
1553 goto err_dma_alloc;
1554 }
1555
1556 sdma->context = (void *)sdma->channel_control +
1557 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1558 sdma->context_phys = ccb_phys +
1559 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
1560
1561 /* Zero-out the CCB structures array just allocated */
1562 memset(sdma->channel_control, 0,
1563 MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control));
1564
1565 /* disable all channels */
1566 for (i = 0; i < sdma->drvdata->num_events; i++)
1567 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
1568
1569 /* All channels have priority 0 */
1570 for (i = 0; i < MAX_DMA_CHANNELS; i++)
1571 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
1572
1573 ret = sdma_request_channel(&sdma->channel[0]);
1574 if (ret)
1575 goto err_dma_alloc;
1576
1577 sdma_config_ownership(&sdma->channel[0], false, true, false);
1578
1579 /* Set Command Channel (Channel Zero) */
1580 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
1581
1582 /* Set bits of CONFIG register but with static context switching */
1583 /* FIXME: Check whether to set ACR bit depending on clock ratios */
1584 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
1585
1586 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
1587
1588 /* Initializes channel's priorities */
1589 sdma_set_channel_priority(&sdma->channel[0], 7);
1590
1591 clk_disable(sdma->clk_ipg);
1592 clk_disable(sdma->clk_ahb);
1593
1594 return 0;
1595
1596 err_dma_alloc:
1597 clk_disable(sdma->clk_ahb);
1598 disable_clk_ipg:
1599 clk_disable(sdma->clk_ipg);
1600 dev_err(sdma->dev, "initialisation failed with %d\n", ret);
1601 return ret;
1602 }
1603
1604 static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
1605 {
1606 struct sdma_channel *sdmac = to_sdma_chan(chan);
1607 struct imx_dma_data *data = fn_param;
1608
1609 if (!imx_dma_is_general_purpose(chan))
1610 return false;
1611
1612 sdmac->data = *data;
1613 chan->private = &sdmac->data;
1614
1615 return true;
1616 }
1617
1618 static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
1619 struct of_dma *ofdma)
1620 {
1621 struct sdma_engine *sdma = ofdma->of_dma_data;
1622 dma_cap_mask_t mask = sdma->dma_device.cap_mask;
1623 struct imx_dma_data data;
1624
1625 if (dma_spec->args_count != 3)
1626 return NULL;
1627
1628 data.dma_request = dma_spec->args[0];
1629 data.peripheral_type = dma_spec->args[1];
1630 data.priority = dma_spec->args[2];
1631 /*
1632 * init dma_request2 to zero, which is not used by the dts.
1633 * For P2P, dma_request2 is init from dma_request_channel(),
1634 * chan->private will point to the imx_dma_data, and in
1635 * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
1636 * be set to sdmac->event_id1.
1637 */
1638 data.dma_request2 = 0;
1639
1640 return dma_request_channel(mask, sdma_filter_fn, &data);
1641 }
1642
1643 static int sdma_probe(struct platform_device *pdev)
1644 {
1645 const struct of_device_id *of_id =
1646 of_match_device(sdma_dt_ids, &pdev->dev);
1647 struct device_node *np = pdev->dev.of_node;
1648 struct device_node *spba_bus;
1649 const char *fw_name;
1650 int ret;
1651 int irq;
1652 struct resource *iores;
1653 struct resource spba_res;
1654 struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
1655 int i;
1656 struct sdma_engine *sdma;
1657 s32 *saddr_arr;
1658 const struct sdma_driver_data *drvdata = NULL;
1659
1660 if (of_id)
1661 drvdata = of_id->data;
1662 else if (pdev->id_entry)
1663 drvdata = (void *)pdev->id_entry->driver_data;
1664
1665 if (!drvdata) {
1666 dev_err(&pdev->dev, "unable to find driver data\n");
1667 return -EINVAL;
1668 }
1669
1670 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1671 if (ret)
1672 return ret;
1673
1674 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
1675 if (!sdma)
1676 return -ENOMEM;
1677
1678 spin_lock_init(&sdma->channel_0_lock);
1679
1680 sdma->dev = &pdev->dev;
1681 sdma->drvdata = drvdata;
1682
1683 irq = platform_get_irq(pdev, 0);
1684 if (irq < 0)
1685 return irq;
1686
1687 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1688 sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
1689 if (IS_ERR(sdma->regs))
1690 return PTR_ERR(sdma->regs);
1691
1692 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1693 if (IS_ERR(sdma->clk_ipg))
1694 return PTR_ERR(sdma->clk_ipg);
1695
1696 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1697 if (IS_ERR(sdma->clk_ahb))
1698 return PTR_ERR(sdma->clk_ahb);
1699
1700 clk_prepare(sdma->clk_ipg);
1701 clk_prepare(sdma->clk_ahb);
1702
1703 ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
1704 sdma);
1705 if (ret)
1706 return ret;
1707
1708 sdma->irq = irq;
1709
1710 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
1711 if (!sdma->script_addrs)
1712 return -ENOMEM;
1713
1714 /* initially no scripts available */
1715 saddr_arr = (s32 *)sdma->script_addrs;
1716 for (i = 0; i < SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; i++)
1717 saddr_arr[i] = -EINVAL;
1718
1719 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
1720 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
1721
1722 INIT_LIST_HEAD(&sdma->dma_device.channels);
1723 /* Initialize channel parameters */
1724 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1725 struct sdma_channel *sdmac = &sdma->channel[i];
1726
1727 sdmac->sdma = sdma;
1728 spin_lock_init(&sdmac->lock);
1729
1730 sdmac->chan.device = &sdma->dma_device;
1731 dma_cookie_init(&sdmac->chan);
1732 sdmac->channel = i;
1733
1734 tasklet_init(&sdmac->tasklet, sdma_tasklet,
1735 (unsigned long) sdmac);
1736 /*
1737 * Add the channel to the DMAC list. Do not add channel 0 though
1738 * because we need it internally in the SDMA driver. This also means
1739 * that channel 0 in dmaengine counting matches sdma channel 1.
1740 */
1741 if (i)
1742 list_add_tail(&sdmac->chan.device_node,
1743 &sdma->dma_device.channels);
1744 }
1745
1746 ret = sdma_init(sdma);
1747 if (ret)
1748 goto err_init;
1749
1750 ret = sdma_event_remap(sdma);
1751 if (ret)
1752 goto err_init;
1753
1754 if (sdma->drvdata->script_addrs)
1755 sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
1756 if (pdata && pdata->script_addrs)
1757 sdma_add_scripts(sdma, pdata->script_addrs);
1758
1759 if (pdata) {
1760 ret = sdma_get_firmware(sdma, pdata->fw_name);
1761 if (ret)
1762 dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
1763 } else {
1764 /*
1765 * Because that device tree does not encode ROM script address,
1766 * the RAM script in firmware is mandatory for device tree
1767 * probe, otherwise it fails.
1768 */
1769 ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
1770 &fw_name);
1771 if (ret)
1772 dev_warn(&pdev->dev, "failed to get firmware name\n");
1773 else {
1774 ret = sdma_get_firmware(sdma, fw_name);
1775 if (ret)
1776 dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
1777 }
1778 }
1779
1780 sdma->dma_device.dev = &pdev->dev;
1781
1782 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
1783 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
1784 sdma->dma_device.device_tx_status = sdma_tx_status;
1785 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
1786 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
1787 sdma->dma_device.device_config = sdma_config;
1788 sdma->dma_device.device_terminate_all = sdma_disable_channel;
1789 sdma->dma_device.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1790 sdma->dma_device.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
1791 sdma->dma_device.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1792 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
1793 sdma->dma_device.device_issue_pending = sdma_issue_pending;
1794 sdma->dma_device.dev->dma_parms = &sdma->dma_parms;
1795 dma_set_max_seg_size(sdma->dma_device.dev, 65535);
1796
1797 platform_set_drvdata(pdev, sdma);
1798
1799 ret = dma_async_device_register(&sdma->dma_device);
1800 if (ret) {
1801 dev_err(&pdev->dev, "unable to register\n");
1802 goto err_init;
1803 }
1804
1805 if (np) {
1806 ret = of_dma_controller_register(np, sdma_xlate, sdma);
1807 if (ret) {
1808 dev_err(&pdev->dev, "failed to register controller\n");
1809 goto err_register;
1810 }
1811
1812 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
1813 ret = of_address_to_resource(spba_bus, 0, &spba_res);
1814 if (!ret) {
1815 sdma->spba_start_addr = spba_res.start;
1816 sdma->spba_end_addr = spba_res.end;
1817 }
1818 of_node_put(spba_bus);
1819 }
1820
1821 return 0;
1822
1823 err_register:
1824 dma_async_device_unregister(&sdma->dma_device);
1825 err_init:
1826 kfree(sdma->script_addrs);
1827 return ret;
1828 }
1829
1830 static int sdma_remove(struct platform_device *pdev)
1831 {
1832 struct sdma_engine *sdma = platform_get_drvdata(pdev);
1833 int i;
1834
1835 devm_free_irq(&pdev->dev, sdma->irq, sdma);
1836 dma_async_device_unregister(&sdma->dma_device);
1837 kfree(sdma->script_addrs);
1838 /* Kill the tasklet */
1839 for (i = 0; i < MAX_DMA_CHANNELS; i++) {
1840 struct sdma_channel *sdmac = &sdma->channel[i];
1841
1842 tasklet_kill(&sdmac->tasklet);
1843 }
1844
1845 platform_set_drvdata(pdev, NULL);
1846 return 0;
1847 }
1848
1849 static struct platform_driver sdma_driver = {
1850 .driver = {
1851 .name = "imx-sdma",
1852 .of_match_table = sdma_dt_ids,
1853 },
1854 .id_table = sdma_devtypes,
1855 .remove = sdma_remove,
1856 .probe = sdma_probe,
1857 };
1858
1859 module_platform_driver(sdma_driver);
1860
1861 MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
1862 MODULE_DESCRIPTION("i.MX SDMA driver");
1863 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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