drivers/dma/ioat/hw.h

   1 /*
   2  * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the Free
   6  * Software Foundation; either version 2 of the License, or (at your option)
   7  * any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called COPYING.
  16  */
  17 #ifndef _IOAT_HW_H_
  18 #define _IOAT_HW_H_
  19
  20 /* PCI Configuration Space Values */
  21 #define IOAT_MMIO_BAR           0
  22
  23 /* CB device ID's */
  24 #define PCI_DEVICE_ID_INTEL_IOAT_IVB0   0x0e20
  25 #define PCI_DEVICE_ID_INTEL_IOAT_IVB1   0x0e21
  26 #define PCI_DEVICE_ID_INTEL_IOAT_IVB2   0x0e22
  27 #define PCI_DEVICE_ID_INTEL_IOAT_IVB3   0x0e23
  28 #define PCI_DEVICE_ID_INTEL_IOAT_IVB4   0x0e24
  29 #define PCI_DEVICE_ID_INTEL_IOAT_IVB5   0x0e25
  30 #define PCI_DEVICE_ID_INTEL_IOAT_IVB6   0x0e26
  31 #define PCI_DEVICE_ID_INTEL_IOAT_IVB7   0x0e27
  32 #define PCI_DEVICE_ID_INTEL_IOAT_IVB8   0x0e2e
  33 #define PCI_DEVICE_ID_INTEL_IOAT_IVB9   0x0e2f
  34
  35 #define PCI_DEVICE_ID_INTEL_IOAT_HSW0   0x2f20
  36 #define PCI_DEVICE_ID_INTEL_IOAT_HSW1   0x2f21
  37 #define PCI_DEVICE_ID_INTEL_IOAT_HSW2   0x2f22
  38 #define PCI_DEVICE_ID_INTEL_IOAT_HSW3   0x2f23
  39 #define PCI_DEVICE_ID_INTEL_IOAT_HSW4   0x2f24
  40 #define PCI_DEVICE_ID_INTEL_IOAT_HSW5   0x2f25
  41 #define PCI_DEVICE_ID_INTEL_IOAT_HSW6   0x2f26
  42 #define PCI_DEVICE_ID_INTEL_IOAT_HSW7   0x2f27
  43 #define PCI_DEVICE_ID_INTEL_IOAT_HSW8   0x2f2e
  44 #define PCI_DEVICE_ID_INTEL_IOAT_HSW9   0x2f2f
  45
  46 #define PCI_DEVICE_ID_INTEL_IOAT_BWD0   0x0C50
  47 #define PCI_DEVICE_ID_INTEL_IOAT_BWD1   0x0C51
  48 #define PCI_DEVICE_ID_INTEL_IOAT_BWD2   0x0C52
  49 #define PCI_DEVICE_ID_INTEL_IOAT_BWD3   0x0C53
  50
  51 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE0 0x6f50
  52 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE1 0x6f51
  53 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE2 0x6f52
  54 #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE3 0x6f53
  55
  56 #define PCI_DEVICE_ID_INTEL_IOAT_BDX0   0x6f20
  57 #define PCI_DEVICE_ID_INTEL_IOAT_BDX1   0x6f21
  58 #define PCI_DEVICE_ID_INTEL_IOAT_BDX2   0x6f22
  59 #define PCI_DEVICE_ID_INTEL_IOAT_BDX3   0x6f23
  60 #define PCI_DEVICE_ID_INTEL_IOAT_BDX4   0x6f24
  61 #define PCI_DEVICE_ID_INTEL_IOAT_BDX5   0x6f25
  62 #define PCI_DEVICE_ID_INTEL_IOAT_BDX6   0x6f26
  63 #define PCI_DEVICE_ID_INTEL_IOAT_BDX7   0x6f27
  64 #define PCI_DEVICE_ID_INTEL_IOAT_BDX8   0x6f2e
  65 #define PCI_DEVICE_ID_INTEL_IOAT_BDX9   0x6f2f
  66
  67 #define IOAT_VER_1_2            0x12    /* Version 1.2 */
  68 #define IOAT_VER_2_0            0x20    /* Version 2.0 */
  69 #define IOAT_VER_3_0            0x30    /* Version 3.0 */
  70 #define IOAT_VER_3_2            0x32    /* Version 3.2 */
  71 #define IOAT_VER_3_3            0x33    /* Version 3.3 */
  72
  73
  74 int system_has_dca_enabled(struct pci_dev *pdev);
  75
  76 struct ioat_dma_descriptor {
  77         uint32_t        size;
  78         union {
  79                 uint32_t ctl;
  80                 struct {
  81                         unsigned int int_en:1;
  82                         unsigned int src_snoop_dis:1;
  83                         unsigned int dest_snoop_dis:1;
  84                         unsigned int compl_write:1;
  85                         unsigned int fence:1;
  86                         unsigned int null:1;
  87                         unsigned int src_brk:1;
  88                         unsigned int dest_brk:1;
  89                         unsigned int bundle:1;
  90                         unsigned int dest_dca:1;
  91                         unsigned int hint:1;
  92                         unsigned int rsvd2:13;
  93                         #define IOAT_OP_COPY 0x00
  94                         unsigned int op:8;
  95                 } ctl_f;
  96         };
  97         uint64_t        src_addr;
  98         uint64_t        dst_addr;
  99         uint64_t        next;
 100         uint64_t        rsv1;
 101         uint64_t        rsv2;
 102         /* store some driver data in an unused portion of the descriptor */
 103         union {
 104                 uint64_t        user1;
 105                 uint64_t        tx_cnt;
 106         };
 107         uint64_t        user2;
 108 };
 109
 110 struct ioat_xor_descriptor {
 111         uint32_t        size;
 112         union {
 113                 uint32_t ctl;
 114                 struct {
 115                         unsigned int int_en:1;
 116                         unsigned int src_snoop_dis:1;
 117                         unsigned int dest_snoop_dis:1;
 118                         unsigned int compl_write:1;
 119                         unsigned int fence:1;
 120                         unsigned int src_cnt:3;
 121                         unsigned int bundle:1;
 122                         unsigned int dest_dca:1;
 123                         unsigned int hint:1;
 124                         unsigned int rsvd:13;
 125                         #define IOAT_OP_XOR 0x87
 126                         #define IOAT_OP_XOR_VAL 0x88
 127                         unsigned int op:8;
 128                 } ctl_f;
 129         };
 130         uint64_t        src_addr;
 131         uint64_t        dst_addr;
 132         uint64_t        next;
 133         uint64_t        src_addr2;
 134         uint64_t        src_addr3;
 135         uint64_t        src_addr4;
 136         uint64_t        src_addr5;
 137 };
 138
 139 struct ioat_xor_ext_descriptor {
 140         uint64_t        src_addr6;
 141         uint64_t        src_addr7;
 142         uint64_t        src_addr8;
 143         uint64_t        next;
 144         uint64_t        rsvd[4];
 145 };
 146
 147 struct ioat_pq_descriptor {
 148         union {
 149                 uint32_t        size;
 150                 uint32_t        dwbes;
 151                 struct {
 152                         unsigned int rsvd:25;
 153                         unsigned int p_val_err:1;
 154                         unsigned int q_val_err:1;
 155                         unsigned int rsvd1:4;
 156                         unsigned int wbes:1;
 157                 } dwbes_f;
 158         };
 159         union {
 160                 uint32_t ctl;
 161                 struct {
 162                         unsigned int int_en:1;
 163                         unsigned int src_snoop_dis:1;
 164                         unsigned int dest_snoop_dis:1;
 165                         unsigned int compl_write:1;
 166                         unsigned int fence:1;
 167                         unsigned int src_cnt:3;
 168                         unsigned int bundle:1;
 169                         unsigned int dest_dca:1;
 170                         unsigned int hint:1;
 171                         unsigned int p_disable:1;
 172                         unsigned int q_disable:1;
 173                         unsigned int rsvd2:2;
 174                         unsigned int wb_en:1;
 175                         unsigned int prl_en:1;
 176                         unsigned int rsvd3:7;
 177                         #define IOAT_OP_PQ 0x89
 178                         #define IOAT_OP_PQ_VAL 0x8a
 179                         #define IOAT_OP_PQ_16S 0xa0
 180                         #define IOAT_OP_PQ_VAL_16S 0xa1
 181                         unsigned int op:8;
 182                 } ctl_f;
 183         };
 184         uint64_t        src_addr;
 185         uint64_t        p_addr;
 186         uint64_t        next;
 187         uint64_t        src_addr2;
 188         union {
 189                 uint64_t        src_addr3;
 190                 uint64_t        sed_addr;
 191         };
 192         uint8_t         coef[8];
 193         uint64_t        q_addr;
 194 };
 195
 196 struct ioat_pq_ext_descriptor {
 197         uint64_t        src_addr4;
 198         uint64_t        src_addr5;
 199         uint64_t        src_addr6;
 200         uint64_t        next;
 201         uint64_t        src_addr7;
 202         uint64_t        src_addr8;
 203         uint64_t        rsvd[2];
 204 };
 205
 206 struct ioat_pq_update_descriptor {
 207         uint32_t        size;
 208         union {
 209                 uint32_t ctl;
 210                 struct {
 211                         unsigned int int_en:1;
 212                         unsigned int src_snoop_dis:1;
 213                         unsigned int dest_snoop_dis:1;
 214                         unsigned int compl_write:1;
 215                         unsigned int fence:1;
 216                         unsigned int src_cnt:3;
 217                         unsigned int bundle:1;
 218                         unsigned int dest_dca:1;
 219                         unsigned int hint:1;
 220                         unsigned int p_disable:1;
 221                         unsigned int q_disable:1;
 222                         unsigned int rsvd:3;
 223                         unsigned int coef:8;
 224                         #define IOAT_OP_PQ_UP 0x8b
 225                         unsigned int op:8;
 226                 } ctl_f;
 227         };
 228         uint64_t        src_addr;
 229         uint64_t        p_addr;
 230         uint64_t        next;
 231         uint64_t        src_addr2;
 232         uint64_t        p_src;
 233         uint64_t        q_src;
 234         uint64_t        q_addr;
 235 };
 236
 237 struct ioat_raw_descriptor {
 238         uint64_t        field[8];
 239 };
 240
 241 struct ioat_pq16a_descriptor {
 242         uint8_t coef[8];
 243         uint64_t src_addr3;
 244         uint64_t src_addr4;
 245         uint64_t src_addr5;
 246         uint64_t src_addr6;
 247         uint64_t src_addr7;
 248         uint64_t src_addr8;
 249         uint64_t src_addr9;
 250 };
 251
 252 struct ioat_pq16b_descriptor {
 253         uint64_t src_addr10;
 254         uint64_t src_addr11;
 255         uint64_t src_addr12;
 256         uint64_t src_addr13;
 257         uint64_t src_addr14;
 258         uint64_t src_addr15;
 259         uint64_t src_addr16;
 260         uint64_t rsvd;
 261 };
 262
 263 union ioat_sed_pq_descriptor {
 264         struct ioat_pq16a_descriptor a;
 265         struct ioat_pq16b_descriptor b;
 266 };
 267
 268 #define SED_SIZE        64
 269
 270 struct ioat_sed_raw_descriptor {
 271         uint64_t        a[8];
 272         uint64_t        b[8];
 273         uint64_t        c[8];
 274 };
 275
 276 #endif