drivers/dma/mv_xor.h

   1 /*
   2  * Copyright (C) 2007, 2008, Marvell International Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  11  * for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software Foundation,
  15  * Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  16  */
  17
  18 #ifndef MV_XOR_H
  19 #define MV_XOR_H
  20
  21 #include <linux/types.h>
  22 #include <linux/io.h>
  23 #include <linux/dmaengine.h>
  24 #include <linux/interrupt.h>
  25
  26 #define USE_TIMER
  27 #define MV_XOR_SLOT_SIZE                64
  28 #define MV_XOR_THRESHOLD                1
  29
  30 #define XOR_OPERATION_MODE_XOR          0
  31 #define XOR_OPERATION_MODE_MEMCPY       2
  32 #define XOR_OPERATION_MODE_MEMSET       4
  33
  34 #define XOR_CURR_DESC(chan)     (chan->mmr_base + 0x210 + (chan->idx * 4))
  35 #define XOR_NEXT_DESC(chan)     (chan->mmr_base + 0x200 + (chan->idx * 4))
  36 #define XOR_BYTE_COUNT(chan)    (chan->mmr_base + 0x220 + (chan->idx * 4))
  37 #define XOR_DEST_POINTER(chan)  (chan->mmr_base + 0x2B0 + (chan->idx * 4))
  38 #define XOR_BLOCK_SIZE(chan)    (chan->mmr_base + 0x2C0 + (chan->idx * 4))
  39 #define XOR_INIT_VALUE_LOW(chan)        (chan->mmr_base + 0x2E0)
  40 #define XOR_INIT_VALUE_HIGH(chan)       (chan->mmr_base + 0x2E4)
  41
  42 #define XOR_CONFIG(chan)        (chan->mmr_base + 0x10 + (chan->idx * 4))
  43 #define XOR_ACTIVATION(chan)    (chan->mmr_base + 0x20 + (chan->idx * 4))
  44 #define XOR_INTR_CAUSE(chan)    (chan->mmr_base + 0x30)
  45 #define XOR_INTR_MASK(chan)     (chan->mmr_base + 0x40)
  46 #define XOR_ERROR_CAUSE(chan)   (chan->mmr_base + 0x50)
  47 #define XOR_ERROR_ADDR(chan)    (chan->mmr_base + 0x60)
  48 #define XOR_INTR_MASK_VALUE     0x3F5
  49
  50 #define WINDOW_BASE(w)          (0x250 + ((w) << 2))
  51 #define WINDOW_SIZE(w)          (0x270 + ((w) << 2))
  52 #define WINDOW_REMAP_HIGH(w)    (0x290 + ((w) << 2))
  53 #define WINDOW_BAR_ENABLE(chan) (0x240 + ((chan) << 2))
  54
  55 struct mv_xor_shared_private {
  56         void __iomem    *xor_base;
  57         void __iomem    *xor_high_base;
  58         struct clk      *clk;
  59 };
  60
  61
  62 /**
  63  * struct mv_xor_device - internal representation of a XOR device
  64  * @pdev: Platform device
  65  * @id: HW XOR Device selector
  66  * @dma_desc_pool: base of DMA descriptor region (DMA address)
  67  * @dma_desc_pool_virt: base of DMA descriptor region (CPU address)
  68  * @common: embedded struct dma_device
  69  */
  70 struct mv_xor_device {
  71         struct platform_device          *pdev;
  72         int                             id;
  73         dma_addr_t                      dma_desc_pool;
  74         void                            *dma_desc_pool_virt;
  75         struct dma_device               common;
  76         struct mv_xor_shared_private    *shared;
  77 };
  78
  79 /**
  80  * struct mv_xor_chan - internal representation of a XOR channel
  81  * @pending: allows batching of hardware operations
  82  * @lock: serializes enqueue/dequeue operations to the descriptors pool
  83  * @mmr_base: memory mapped register base
  84  * @idx: the index of the xor channel
  85  * @chain: device chain view of the descriptors
  86  * @completed_slots: slots completed by HW but still need to be acked
  87  * @device: parent device
  88  * @common: common dmaengine channel object members
  89  * @last_used: place holder for allocation to continue from where it left off
  90  * @all_slots: complete domain of slots usable by the channel
  91  * @slots_allocated: records the actual size of the descriptor slot pool
  92  * @irq_tasklet: bottom half where mv_xor_slot_cleanup runs
  93  */
  94 struct mv_xor_chan {
  95         int                     pending;
  96         spinlock_t              lock; /* protects the descriptor slot pool */
  97         void __iomem            *mmr_base;
  98         unsigned int            idx;
  99         enum dma_transaction_type       current_type;
 100         struct list_head        chain;
 101         struct list_head        completed_slots;
 102         struct mv_xor_device    *device;
 103         struct dma_chan         common;
 104         struct mv_xor_desc_slot *last_used;
 105         struct list_head        all_slots;
 106         int                     slots_allocated;
 107         struct tasklet_struct   irq_tasklet;
 108 #ifdef USE_TIMER
 109         unsigned long           cleanup_time;
 110         u32                     current_on_last_cleanup;
 111 #endif
 112 };
 113
 114 /**
 115  * struct mv_xor_desc_slot - software descriptor
 116  * @slot_node: node on the mv_xor_chan.all_slots list
 117  * @chain_node: node on the mv_xor_chan.chain list
 118  * @completed_node: node on the mv_xor_chan.completed_slots list
 119  * @hw_desc: virtual address of the hardware descriptor chain
 120  * @phys: hardware address of the hardware descriptor chain
 121  * @group_head: first operation in a transaction
 122  * @slot_cnt: total slots used in an transaction (group of operations)
 123  * @slots_per_op: number of slots per operation
 124  * @idx: pool index
 125  * @unmap_src_cnt: number of xor sources
 126  * @unmap_len: transaction bytecount
 127  * @tx_list: list of slots that make up a multi-descriptor transaction
 128  * @async_tx: support for the async_tx api
 129  * @xor_check_result: result of zero sum
 130  * @crc32_result: result crc calculation
 131  */
 132 struct mv_xor_desc_slot {
 133         struct list_head        slot_node;
 134         struct list_head        chain_node;
 135         struct list_head        completed_node;
 136         enum dma_transaction_type       type;
 137         void                    *hw_desc;
 138         struct mv_xor_desc_slot *group_head;
 139         u16                     slot_cnt;
 140         u16                     slots_per_op;
 141         u16                     idx;
 142         u16                     unmap_src_cnt;
 143         u32                     value;
 144         size_t                  unmap_len;
 145         struct list_head        tx_list;
 146         struct dma_async_tx_descriptor  async_tx;
 147         union {
 148                 u32             *xor_check_result;
 149                 u32             *crc32_result;
 150         };
 151 #ifdef USE_TIMER
 152         unsigned long           arrival_time;
 153         struct timer_list       timeout;
 154 #endif
 155 };
 156
 157 /* This structure describes XOR descriptor size 64bytes */
 158 struct mv_xor_desc {
 159         u32 status;             /* descriptor execution status */
 160         u32 crc32_result;       /* result of CRC-32 calculation */
 161         u32 desc_command;       /* type of operation to be carried out */
 162         u32 phy_next_desc;      /* next descriptor address pointer */
 163         u32 byte_count;         /* size of src/dst blocks in bytes */
 164         u32 phy_dest_addr;      /* destination block address */
 165         u32 phy_src_addr[8];    /* source block addresses */
 166         u32 reserved0;
 167         u32 reserved1;
 168 };
 169
 170 #define to_mv_sw_desc(addr_hw_desc)             \
 171         container_of(addr_hw_desc, struct mv_xor_desc_slot, hw_desc)
 172
 173 #define mv_hw_desc_slot_idx(hw_desc, idx)       \
 174         ((void *)(((unsigned long)hw_desc) + ((idx) << 5)))
 175
 176 #define MV_XOR_MIN_BYTE_COUNT   (128)
 177 #define XOR_MAX_BYTE_COUNT      ((16 * 1024 * 1024) - 1)
 178 #define MV_XOR_MAX_BYTE_COUNT   XOR_MAX_BYTE_COUNT
 179
 180
 181 #endif