2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
6 * License terms: GNU General Public License (GPL) version 2
9 #include <linux/kernel.h>
10 #include <linux/slab.h>
11 #include <linux/dmaengine.h>
12 #include <linux/platform_device.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/err.h>
17 #include <plat/ste_dma40.h>
19 #include "ste_dma40_ll.h"
21 #define D40_NAME "dma40"
23 #define D40_PHY_CHAN -1
25 /* For masking out/in 2 bit channel positions */
26 #define D40_CHAN_POS(chan) (2 * (chan / 2))
27 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
29 /* Maximum iterations taken before giving up suspending a channel */
30 #define D40_SUSPEND_MAX_IT 500
32 /* Hardware requirement on LCLA alignment */
33 #define LCLA_ALIGNMENT 0x40000
35 /* Max number of links per event group */
36 #define D40_LCLA_LINK_PER_EVENT_GRP 128
37 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
39 /* Attempts before giving up to trying to get pages that are aligned */
40 #define MAX_LCLA_ALLOC_ATTEMPTS 256
42 /* Bit markings for allocation map */
43 #define D40_ALLOC_FREE (1 << 31)
44 #define D40_ALLOC_PHY (1 << 30)
45 #define D40_ALLOC_LOG_FREE 0
47 /* Hardware designer of the block */
48 #define D40_HW_DESIGNER 0x8
51 * enum 40_command - The different commands and/or statuses.
53 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
54 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
55 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
56 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
61 D40_DMA_SUSPEND_REQ
= 2,
66 * struct d40_lli_pool - Structure for keeping LLIs in memory
68 * @base: Pointer to memory area when the pre_alloc_lli's are not large
69 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
70 * pre_alloc_lli is used.
71 * @dma_addr: DMA address, if mapped
72 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
73 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
74 * one buffer to one buffer.
80 /* Space for dst and src, plus an extra for padding */
81 u8 pre_alloc_lli
[3 * sizeof(struct d40_phy_lli
)];
85 * struct d40_desc - A descriptor is one DMA job.
87 * @lli_phy: LLI settings for physical channel. Both src and dst=
88 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
90 * @lli_log: Same as above but for logical channels.
91 * @lli_pool: The pool with two entries pre-allocated.
92 * @lli_len: Number of llis of current descriptor.
93 * @lli_current: Number of transfered llis.
94 * @lcla_alloc: Number of LCLA entries allocated.
95 * @txd: DMA engine struct. Used for among other things for communication
98 * @is_in_client_list: true if the client owns this descriptor.
101 * This descriptor is used for both logical and physical transfers.
105 struct d40_phy_lli_bidir lli_phy
;
107 struct d40_log_lli_bidir lli_log
;
109 struct d40_lli_pool lli_pool
;
114 struct dma_async_tx_descriptor txd
;
115 struct list_head node
;
117 bool is_in_client_list
;
121 * struct d40_lcla_pool - LCLA pool settings and data.
123 * @base: The virtual address of LCLA. 18 bit aligned.
124 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
125 * This pointer is only there for clean-up on error.
126 * @pages: The number of pages needed for all physical channels.
127 * Only used later for clean-up on error
128 * @lock: Lock to protect the content in this struct.
129 * @alloc_map: big map over which LCLA entry is own by which job.
131 struct d40_lcla_pool
{
134 void *base_unaligned
;
137 struct d40_desc
**alloc_map
;
141 * struct d40_phy_res - struct for handling eventlines mapped to physical
144 * @lock: A lock protection this entity.
145 * @num: The physical channel number of this entity.
146 * @allocated_src: Bit mapped to show which src event line's are mapped to
147 * this physical channel. Can also be free or physically allocated.
148 * @allocated_dst: Same as for src but is dst.
149 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
162 * struct d40_chan - Struct that describes a channel.
164 * @lock: A spinlock to protect this struct.
165 * @log_num: The logical number, if any of this channel.
166 * @completed: Starts with 1, after first interrupt it is set to dma engine's
168 * @pending_tx: The number of pending transfers. Used between interrupt handler
170 * @busy: Set to true when transfer is ongoing on this channel.
171 * @phy_chan: Pointer to physical channel which this instance runs on. If this
172 * point is NULL, then the channel is not allocated.
173 * @chan: DMA engine handle.
174 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
175 * transfer and call client callback.
176 * @client: Cliented owned descriptor list.
177 * @active: Active descriptor.
178 * @queue: Queued jobs.
179 * @dma_cfg: The client configuration of this dma channel.
180 * @configured: whether the dma_cfg configuration is valid
181 * @base: Pointer to the device instance struct.
182 * @src_def_cfg: Default cfg register setting for src.
183 * @dst_def_cfg: Default cfg register setting for dst.
184 * @log_def: Default logical channel settings.
185 * @lcla: Space for one dst src pair for logical channel transfers.
186 * @lcpa: Pointer to dst and src lcpa settings.
188 * This struct can either "be" a logical or a physical channel.
193 /* ID of the most recent completed transfer */
197 struct d40_phy_res
*phy_chan
;
198 struct dma_chan chan
;
199 struct tasklet_struct tasklet
;
200 struct list_head client
;
201 struct list_head active
;
202 struct list_head queue
;
203 struct stedma40_chan_cfg dma_cfg
;
205 struct d40_base
*base
;
206 /* Default register configurations */
209 struct d40_def_lcsp log_def
;
210 struct d40_log_lli_full
*lcpa
;
211 /* Runtime reconfiguration */
212 dma_addr_t runtime_addr
;
213 enum dma_data_direction runtime_direction
;
217 * struct d40_base - The big global struct, one for each probe'd instance.
219 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
220 * @execmd_lock: Lock for execute command usage since several channels share
221 * the same physical register.
222 * @dev: The device structure.
223 * @virtbase: The virtual base address of the DMA's register.
224 * @rev: silicon revision detected.
225 * @clk: Pointer to the DMA clock structure.
226 * @phy_start: Physical memory start of the DMA registers.
227 * @phy_size: Size of the DMA register map.
228 * @irq: The IRQ number.
229 * @num_phy_chans: The number of physical channels. Read from HW. This
230 * is the number of available channels for this driver, not counting "Secure
231 * mode" allocated physical channels.
232 * @num_log_chans: The number of logical channels. Calculated from
234 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
235 * @dma_slave: dma_device channels that can do only do slave transfers.
236 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
237 * @log_chans: Room for all possible logical channels in system.
238 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
239 * to log_chans entries.
240 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
241 * to phy_chans entries.
242 * @plat_data: Pointer to provided platform_data which is the driver
244 * @phy_res: Vector containing all physical channels.
245 * @lcla_pool: lcla pool settings and data.
246 * @lcpa_base: The virtual mapped address of LCPA.
247 * @phy_lcpa: The physical address of the LCPA.
248 * @lcpa_size: The size of the LCPA area.
249 * @desc_slab: cache for descriptors.
252 spinlock_t interrupt_lock
;
253 spinlock_t execmd_lock
;
255 void __iomem
*virtbase
;
258 phys_addr_t phy_start
;
259 resource_size_t phy_size
;
263 struct dma_device dma_both
;
264 struct dma_device dma_slave
;
265 struct dma_device dma_memcpy
;
266 struct d40_chan
*phy_chans
;
267 struct d40_chan
*log_chans
;
268 struct d40_chan
**lookup_log_chans
;
269 struct d40_chan
**lookup_phy_chans
;
270 struct stedma40_platform_data
*plat_data
;
271 /* Physical half channels */
272 struct d40_phy_res
*phy_res
;
273 struct d40_lcla_pool lcla_pool
;
276 resource_size_t lcpa_size
;
277 struct kmem_cache
*desc_slab
;
281 * struct d40_interrupt_lookup - lookup table for interrupt handler
283 * @src: Interrupt mask register.
284 * @clr: Interrupt clear register.
285 * @is_error: true if this is an error interrupt.
286 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
287 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
289 struct d40_interrupt_lookup
{
297 * struct d40_reg_val - simple lookup struct
299 * @reg: The register.
300 * @val: The value that belongs to the register in reg.
307 static struct device
*chan2dev(struct d40_chan
*d40c
)
309 return &d40c
->chan
.dev
->device
;
312 static bool chan_is_physical(struct d40_chan
*chan
)
314 return chan
->log_num
== D40_PHY_CHAN
;
317 static bool chan_is_logical(struct d40_chan
*chan
)
319 return !chan_is_physical(chan
);
322 static void __iomem
*chan_base(struct d40_chan
*chan
)
324 return chan
->base
->virtbase
+ D40_DREG_PCBASE
+
325 chan
->phy_chan
->num
* D40_DREG_PCDELTA
;
328 #define d40_err(dev, format, arg...) \
329 dev_err(dev, "[%s] " format, __func__, ## arg)
331 #define chan_err(d40c, format, arg...) \
332 d40_err(chan2dev(d40c), format, ## arg)
334 static int d40_pool_lli_alloc(struct d40_chan
*d40c
, struct d40_desc
*d40d
,
335 int lli_len
, bool is_log
)
341 align
= sizeof(struct d40_log_lli
);
343 align
= sizeof(struct d40_phy_lli
);
346 base
= d40d
->lli_pool
.pre_alloc_lli
;
347 d40d
->lli_pool
.size
= sizeof(d40d
->lli_pool
.pre_alloc_lli
);
348 d40d
->lli_pool
.base
= NULL
;
350 d40d
->lli_pool
.size
= lli_len
* 2 * align
;
352 base
= kmalloc(d40d
->lli_pool
.size
+ align
, GFP_NOWAIT
);
353 d40d
->lli_pool
.base
= base
;
355 if (d40d
->lli_pool
.base
== NULL
)
360 d40d
->lli_log
.src
= PTR_ALIGN(base
, align
);
361 d40d
->lli_log
.dst
= d40d
->lli_log
.src
+ lli_len
;
363 d40d
->lli_pool
.dma_addr
= 0;
365 d40d
->lli_phy
.src
= PTR_ALIGN(base
, align
);
366 d40d
->lli_phy
.dst
= d40d
->lli_phy
.src
+ lli_len
;
368 d40d
->lli_pool
.dma_addr
= dma_map_single(d40c
->base
->dev
,
373 if (dma_mapping_error(d40c
->base
->dev
,
374 d40d
->lli_pool
.dma_addr
)) {
375 kfree(d40d
->lli_pool
.base
);
376 d40d
->lli_pool
.base
= NULL
;
377 d40d
->lli_pool
.dma_addr
= 0;
385 static void d40_pool_lli_free(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
387 if (d40d
->lli_pool
.dma_addr
)
388 dma_unmap_single(d40c
->base
->dev
, d40d
->lli_pool
.dma_addr
,
389 d40d
->lli_pool
.size
, DMA_TO_DEVICE
);
391 kfree(d40d
->lli_pool
.base
);
392 d40d
->lli_pool
.base
= NULL
;
393 d40d
->lli_pool
.size
= 0;
394 d40d
->lli_log
.src
= NULL
;
395 d40d
->lli_log
.dst
= NULL
;
396 d40d
->lli_phy
.src
= NULL
;
397 d40d
->lli_phy
.dst
= NULL
;
400 static int d40_lcla_alloc_one(struct d40_chan
*d40c
,
401 struct d40_desc
*d40d
)
408 spin_lock_irqsave(&d40c
->base
->lcla_pool
.lock
, flags
);
410 p
= d40c
->phy_chan
->num
* D40_LCLA_LINK_PER_EVENT_GRP
;
413 * Allocate both src and dst at the same time, therefore the half
414 * start on 1 since 0 can't be used since zero is used as end marker.
416 for (i
= 1 ; i
< D40_LCLA_LINK_PER_EVENT_GRP
/ 2; i
++) {
417 if (!d40c
->base
->lcla_pool
.alloc_map
[p
+ i
]) {
418 d40c
->base
->lcla_pool
.alloc_map
[p
+ i
] = d40d
;
425 spin_unlock_irqrestore(&d40c
->base
->lcla_pool
.lock
, flags
);
430 static int d40_lcla_free_all(struct d40_chan
*d40c
,
431 struct d40_desc
*d40d
)
437 if (chan_is_physical(d40c
))
440 spin_lock_irqsave(&d40c
->base
->lcla_pool
.lock
, flags
);
442 for (i
= 1 ; i
< D40_LCLA_LINK_PER_EVENT_GRP
/ 2; i
++) {
443 if (d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
*
444 D40_LCLA_LINK_PER_EVENT_GRP
+ i
] == d40d
) {
445 d40c
->base
->lcla_pool
.alloc_map
[d40c
->phy_chan
->num
*
446 D40_LCLA_LINK_PER_EVENT_GRP
+ i
] = NULL
;
448 if (d40d
->lcla_alloc
== 0) {
455 spin_unlock_irqrestore(&d40c
->base
->lcla_pool
.lock
, flags
);
461 static void d40_desc_remove(struct d40_desc
*d40d
)
463 list_del(&d40d
->node
);
466 static struct d40_desc
*d40_desc_get(struct d40_chan
*d40c
)
468 struct d40_desc
*desc
= NULL
;
470 if (!list_empty(&d40c
->client
)) {
474 list_for_each_entry_safe(d
, _d
, &d40c
->client
, node
)
475 if (async_tx_test_ack(&d
->txd
)) {
476 d40_pool_lli_free(d40c
, d
);
479 memset(desc
, 0, sizeof(*desc
));
485 desc
= kmem_cache_zalloc(d40c
->base
->desc_slab
, GFP_NOWAIT
);
488 INIT_LIST_HEAD(&desc
->node
);
493 static void d40_desc_free(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
496 d40_pool_lli_free(d40c
, d40d
);
497 d40_lcla_free_all(d40c
, d40d
);
498 kmem_cache_free(d40c
->base
->desc_slab
, d40d
);
501 static void d40_desc_submit(struct d40_chan
*d40c
, struct d40_desc
*desc
)
503 list_add_tail(&desc
->node
, &d40c
->active
);
506 static void d40_desc_load(struct d40_chan
*d40c
, struct d40_desc
*d40d
)
508 int curr_lcla
= -EINVAL
, next_lcla
;
510 if (chan_is_physical(d40c
)) {
511 d40_phy_lli_write(d40c
->base
->virtbase
,
515 d40d
->lli_current
= d40d
->lli_len
;
518 if ((d40d
->lli_len
- d40d
->lli_current
) > 1)
519 curr_lcla
= d40_lcla_alloc_one(d40c
, d40d
);
521 d40_log_lli_lcpa_write(d40c
->lcpa
,
522 &d40d
->lli_log
.dst
[d40d
->lli_current
],
523 &d40d
->lli_log
.src
[d40d
->lli_current
],
527 for (; d40d
->lli_current
< d40d
->lli_len
; d40d
->lli_current
++) {
528 unsigned int lcla_offset
= d40c
->phy_chan
->num
* 1024 +
530 struct d40_lcla_pool
*pool
= &d40c
->base
->lcla_pool
;
531 struct d40_log_lli
*lcla
= pool
->base
+ lcla_offset
;
533 if (d40d
->lli_current
+ 1 < d40d
->lli_len
)
534 next_lcla
= d40_lcla_alloc_one(d40c
, d40d
);
538 d40_log_lli_lcla_write(lcla
,
539 &d40d
->lli_log
.dst
[d40d
->lli_current
],
540 &d40d
->lli_log
.src
[d40d
->lli_current
],
543 dma_sync_single_range_for_device(d40c
->base
->dev
,
544 pool
->dma_addr
, lcla_offset
,
545 2 * sizeof(struct d40_log_lli
),
548 curr_lcla
= next_lcla
;
550 if (curr_lcla
== -EINVAL
) {
559 static struct d40_desc
*d40_first_active_get(struct d40_chan
*d40c
)
563 if (list_empty(&d40c
->active
))
566 d
= list_first_entry(&d40c
->active
,
572 static void d40_desc_queue(struct d40_chan
*d40c
, struct d40_desc
*desc
)
574 list_add_tail(&desc
->node
, &d40c
->queue
);
577 static struct d40_desc
*d40_first_queued(struct d40_chan
*d40c
)
581 if (list_empty(&d40c
->queue
))
584 d
= list_first_entry(&d40c
->queue
,
590 static int d40_psize_2_burst_size(bool is_log
, int psize
)
593 if (psize
== STEDMA40_PSIZE_LOG_1
)
596 if (psize
== STEDMA40_PSIZE_PHY_1
)
604 * The dma only supports transmitting packages up to
605 * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
606 * dma elements required to send the entire sg list
608 static int d40_size_2_dmalen(int size
, u32 data_width1
, u32 data_width2
)
611 u32 max_w
= max(data_width1
, data_width2
);
612 u32 min_w
= min(data_width1
, data_width2
);
613 u32 seg_max
= ALIGN(STEDMA40_MAX_SEG_SIZE
<< min_w
, 1 << max_w
);
615 if (seg_max
> STEDMA40_MAX_SEG_SIZE
)
616 seg_max
-= (1 << max_w
);
618 if (!IS_ALIGNED(size
, 1 << max_w
))
624 dmalen
= size
/ seg_max
;
625 if (dmalen
* seg_max
< size
)
631 static int d40_sg_2_dmalen(struct scatterlist
*sgl
, int sg_len
,
632 u32 data_width1
, u32 data_width2
)
634 struct scatterlist
*sg
;
639 for_each_sg(sgl
, sg
, sg_len
, i
) {
640 ret
= d40_size_2_dmalen(sg_dma_len(sg
),
641 data_width1
, data_width2
);
649 /* Support functions for logical channels */
651 static int d40_channel_execute_command(struct d40_chan
*d40c
,
652 enum d40_command command
)
656 void __iomem
*active_reg
;
661 spin_lock_irqsave(&d40c
->base
->execmd_lock
, flags
);
663 if (d40c
->phy_chan
->num
% 2 == 0)
664 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVE
;
666 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVO
;
668 if (command
== D40_DMA_SUSPEND_REQ
) {
669 status
= (readl(active_reg
) &
670 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
671 D40_CHAN_POS(d40c
->phy_chan
->num
);
673 if (status
== D40_DMA_SUSPENDED
|| status
== D40_DMA_STOP
)
677 wmask
= 0xffffffff & ~(D40_CHAN_POS_MASK(d40c
->phy_chan
->num
));
678 writel(wmask
| (command
<< D40_CHAN_POS(d40c
->phy_chan
->num
)),
681 if (command
== D40_DMA_SUSPEND_REQ
) {
683 for (i
= 0 ; i
< D40_SUSPEND_MAX_IT
; i
++) {
684 status
= (readl(active_reg
) &
685 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
686 D40_CHAN_POS(d40c
->phy_chan
->num
);
690 * Reduce the number of bus accesses while
691 * waiting for the DMA to suspend.
695 if (status
== D40_DMA_STOP
||
696 status
== D40_DMA_SUSPENDED
)
700 if (i
== D40_SUSPEND_MAX_IT
) {
702 "unable to suspend the chl %d (log: %d) status %x\n",
703 d40c
->phy_chan
->num
, d40c
->log_num
,
711 spin_unlock_irqrestore(&d40c
->base
->execmd_lock
, flags
);
715 static void d40_term_all(struct d40_chan
*d40c
)
717 struct d40_desc
*d40d
;
719 /* Release active descriptors */
720 while ((d40d
= d40_first_active_get(d40c
))) {
721 d40_desc_remove(d40d
);
722 d40_desc_free(d40c
, d40d
);
725 /* Release queued descriptors waiting for transfer */
726 while ((d40d
= d40_first_queued(d40c
))) {
727 d40_desc_remove(d40d
);
728 d40_desc_free(d40c
, d40d
);
732 d40c
->pending_tx
= 0;
736 static void __d40_config_set_event(struct d40_chan
*d40c
, bool enable
,
739 void __iomem
*addr
= chan_base(d40c
) + reg
;
743 writel((D40_DEACTIVATE_EVENTLINE
<< D40_EVENTLINE_POS(event
))
744 | ~D40_EVENTLINE_MASK(event
), addr
);
749 * The hardware sometimes doesn't register the enable when src and dst
750 * event lines are active on the same logical channel. Retry to ensure
751 * it does. Usually only one retry is sufficient.
755 writel((D40_ACTIVATE_EVENTLINE
<< D40_EVENTLINE_POS(event
))
756 | ~D40_EVENTLINE_MASK(event
), addr
);
758 if (readl(addr
) & D40_EVENTLINE_MASK(event
))
763 dev_dbg(chan2dev(d40c
),
764 "[%s] workaround enable S%cLNK (%d tries)\n",
765 __func__
, reg
== D40_CHAN_REG_SSLNK
? 'S' : 'D',
771 static void d40_config_set_event(struct d40_chan
*d40c
, bool do_enable
)
775 spin_lock_irqsave(&d40c
->phy_chan
->lock
, flags
);
777 /* Enable event line connected to device (or memcpy) */
778 if ((d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) ||
779 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
)) {
780 u32 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
782 __d40_config_set_event(d40c
, do_enable
, event
,
786 if (d40c
->dma_cfg
.dir
!= STEDMA40_PERIPH_TO_MEM
) {
787 u32 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
789 __d40_config_set_event(d40c
, do_enable
, event
,
793 spin_unlock_irqrestore(&d40c
->phy_chan
->lock
, flags
);
796 static u32
d40_chan_has_events(struct d40_chan
*d40c
)
798 void __iomem
*chanbase
= chan_base(d40c
);
801 val
= readl(chanbase
+ D40_CHAN_REG_SSLNK
);
802 val
|= readl(chanbase
+ D40_CHAN_REG_SDLNK
);
807 static u32
d40_get_prmo(struct d40_chan
*d40c
)
809 static const unsigned int phy_map
[] = {
810 [STEDMA40_PCHAN_BASIC_MODE
]
811 = D40_DREG_PRMO_PCHAN_BASIC
,
812 [STEDMA40_PCHAN_MODULO_MODE
]
813 = D40_DREG_PRMO_PCHAN_MODULO
,
814 [STEDMA40_PCHAN_DOUBLE_DST_MODE
]
815 = D40_DREG_PRMO_PCHAN_DOUBLE_DST
,
817 static const unsigned int log_map
[] = {
818 [STEDMA40_LCHAN_SRC_PHY_DST_LOG
]
819 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG
,
820 [STEDMA40_LCHAN_SRC_LOG_DST_PHY
]
821 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY
,
822 [STEDMA40_LCHAN_SRC_LOG_DST_LOG
]
823 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG
,
826 if (chan_is_physical(d40c
))
827 return phy_map
[d40c
->dma_cfg
.mode_opt
];
829 return log_map
[d40c
->dma_cfg
.mode_opt
];
832 static void d40_config_write(struct d40_chan
*d40c
)
837 /* Odd addresses are even addresses + 4 */
838 addr_base
= (d40c
->phy_chan
->num
% 2) * 4;
839 /* Setup channel mode to logical or physical */
840 var
= ((u32
)(chan_is_logical(d40c
)) + 1) <<
841 D40_CHAN_POS(d40c
->phy_chan
->num
);
842 writel(var
, d40c
->base
->virtbase
+ D40_DREG_PRMSE
+ addr_base
);
844 /* Setup operational mode option register */
845 var
= d40_get_prmo(d40c
) << D40_CHAN_POS(d40c
->phy_chan
->num
);
847 writel(var
, d40c
->base
->virtbase
+ D40_DREG_PRMOE
+ addr_base
);
849 if (chan_is_logical(d40c
)) {
850 int lidx
= (d40c
->phy_chan
->num
<< D40_SREG_ELEM_LOG_LIDX_POS
)
851 & D40_SREG_ELEM_LOG_LIDX_MASK
;
852 void __iomem
*chanbase
= chan_base(d40c
);
854 /* Set default config for CFG reg */
855 writel(d40c
->src_def_cfg
, chanbase
+ D40_CHAN_REG_SSCFG
);
856 writel(d40c
->dst_def_cfg
, chanbase
+ D40_CHAN_REG_SDCFG
);
858 /* Set LIDX for lcla */
859 writel(lidx
, chanbase
+ D40_CHAN_REG_SSELT
);
860 writel(lidx
, chanbase
+ D40_CHAN_REG_SDELT
);
864 static u32
d40_residue(struct d40_chan
*d40c
)
868 if (chan_is_logical(d40c
))
869 num_elt
= (readl(&d40c
->lcpa
->lcsp2
) & D40_MEM_LCSP2_ECNT_MASK
)
870 >> D40_MEM_LCSP2_ECNT_POS
;
872 u32 val
= readl(chan_base(d40c
) + D40_CHAN_REG_SDELT
);
873 num_elt
= (val
& D40_SREG_ELEM_PHY_ECNT_MASK
)
874 >> D40_SREG_ELEM_PHY_ECNT_POS
;
877 return num_elt
* (1 << d40c
->dma_cfg
.dst_info
.data_width
);
880 static bool d40_tx_is_linked(struct d40_chan
*d40c
)
884 if (chan_is_logical(d40c
))
885 is_link
= readl(&d40c
->lcpa
->lcsp3
) & D40_MEM_LCSP3_DLOS_MASK
;
887 is_link
= readl(chan_base(d40c
) + D40_CHAN_REG_SDLNK
)
888 & D40_SREG_LNK_PHYS_LNK_MASK
;
893 static int d40_pause(struct dma_chan
*chan
)
895 struct d40_chan
*d40c
=
896 container_of(chan
, struct d40_chan
, chan
);
903 spin_lock_irqsave(&d40c
->lock
, flags
);
905 res
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
907 if (chan_is_logical(d40c
)) {
908 d40_config_set_event(d40c
, false);
909 /* Resume the other logical channels if any */
910 if (d40_chan_has_events(d40c
))
911 res
= d40_channel_execute_command(d40c
,
916 spin_unlock_irqrestore(&d40c
->lock
, flags
);
920 static int d40_resume(struct dma_chan
*chan
)
922 struct d40_chan
*d40c
=
923 container_of(chan
, struct d40_chan
, chan
);
930 spin_lock_irqsave(&d40c
->lock
, flags
);
932 if (d40c
->base
->rev
== 0)
933 if (chan_is_logical(d40c
)) {
934 res
= d40_channel_execute_command(d40c
,
935 D40_DMA_SUSPEND_REQ
);
939 /* If bytes left to transfer or linked tx resume job */
940 if (d40_residue(d40c
) || d40_tx_is_linked(d40c
)) {
942 if (chan_is_logical(d40c
))
943 d40_config_set_event(d40c
, true);
945 res
= d40_channel_execute_command(d40c
, D40_DMA_RUN
);
949 spin_unlock_irqrestore(&d40c
->lock
, flags
);
953 static dma_cookie_t
d40_tx_submit(struct dma_async_tx_descriptor
*tx
)
955 struct d40_chan
*d40c
= container_of(tx
->chan
,
958 struct d40_desc
*d40d
= container_of(tx
, struct d40_desc
, txd
);
961 spin_lock_irqsave(&d40c
->lock
, flags
);
965 if (d40c
->chan
.cookie
< 0)
966 d40c
->chan
.cookie
= 1;
968 d40d
->txd
.cookie
= d40c
->chan
.cookie
;
970 d40_desc_queue(d40c
, d40d
);
972 spin_unlock_irqrestore(&d40c
->lock
, flags
);
977 static int d40_start(struct d40_chan
*d40c
)
979 if (d40c
->base
->rev
== 0) {
982 if (chan_is_logical(d40c
)) {
983 err
= d40_channel_execute_command(d40c
,
984 D40_DMA_SUSPEND_REQ
);
990 if (chan_is_logical(d40c
))
991 d40_config_set_event(d40c
, true);
993 return d40_channel_execute_command(d40c
, D40_DMA_RUN
);
996 static struct d40_desc
*d40_queue_start(struct d40_chan
*d40c
)
998 struct d40_desc
*d40d
;
1001 /* Start queued jobs, if any */
1002 d40d
= d40_first_queued(d40c
);
1007 /* Remove from queue */
1008 d40_desc_remove(d40d
);
1010 /* Add to active queue */
1011 d40_desc_submit(d40c
, d40d
);
1013 /* Initiate DMA job */
1014 d40_desc_load(d40c
, d40d
);
1017 err
= d40_start(d40c
);
1026 /* called from interrupt context */
1027 static void dma_tc_handle(struct d40_chan
*d40c
)
1029 struct d40_desc
*d40d
;
1031 /* Get first active entry from list */
1032 d40d
= d40_first_active_get(d40c
);
1037 d40_lcla_free_all(d40c
, d40d
);
1039 if (d40d
->lli_current
< d40d
->lli_len
) {
1040 d40_desc_load(d40c
, d40d
);
1042 (void) d40_start(d40c
);
1046 if (d40_queue_start(d40c
) == NULL
)
1050 tasklet_schedule(&d40c
->tasklet
);
1054 static void dma_tasklet(unsigned long data
)
1056 struct d40_chan
*d40c
= (struct d40_chan
*) data
;
1057 struct d40_desc
*d40d
;
1058 unsigned long flags
;
1059 dma_async_tx_callback callback
;
1060 void *callback_param
;
1062 spin_lock_irqsave(&d40c
->lock
, flags
);
1064 /* Get first active entry from list */
1065 d40d
= d40_first_active_get(d40c
);
1070 d40c
->completed
= d40d
->txd
.cookie
;
1073 * If terminating a channel pending_tx is set to zero.
1074 * This prevents any finished active jobs to return to the client.
1076 if (d40c
->pending_tx
== 0) {
1077 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1081 /* Callback to client */
1082 callback
= d40d
->txd
.callback
;
1083 callback_param
= d40d
->txd
.callback_param
;
1085 if (async_tx_test_ack(&d40d
->txd
)) {
1086 d40_pool_lli_free(d40c
, d40d
);
1087 d40_desc_remove(d40d
);
1088 d40_desc_free(d40c
, d40d
);
1090 if (!d40d
->is_in_client_list
) {
1091 d40_desc_remove(d40d
);
1092 d40_lcla_free_all(d40c
, d40d
);
1093 list_add_tail(&d40d
->node
, &d40c
->client
);
1094 d40d
->is_in_client_list
= true;
1100 if (d40c
->pending_tx
)
1101 tasklet_schedule(&d40c
->tasklet
);
1103 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1105 if (callback
&& (d40d
->txd
.flags
& DMA_PREP_INTERRUPT
))
1106 callback(callback_param
);
1111 /* Rescue manouver if receiving double interrupts */
1112 if (d40c
->pending_tx
> 0)
1114 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1117 static irqreturn_t
d40_handle_interrupt(int irq
, void *data
)
1119 static const struct d40_interrupt_lookup il
[] = {
1120 {D40_DREG_LCTIS0
, D40_DREG_LCICR0
, false, 0},
1121 {D40_DREG_LCTIS1
, D40_DREG_LCICR1
, false, 32},
1122 {D40_DREG_LCTIS2
, D40_DREG_LCICR2
, false, 64},
1123 {D40_DREG_LCTIS3
, D40_DREG_LCICR3
, false, 96},
1124 {D40_DREG_LCEIS0
, D40_DREG_LCICR0
, true, 0},
1125 {D40_DREG_LCEIS1
, D40_DREG_LCICR1
, true, 32},
1126 {D40_DREG_LCEIS2
, D40_DREG_LCICR2
, true, 64},
1127 {D40_DREG_LCEIS3
, D40_DREG_LCICR3
, true, 96},
1128 {D40_DREG_PCTIS
, D40_DREG_PCICR
, false, D40_PHY_CHAN
},
1129 {D40_DREG_PCEIS
, D40_DREG_PCICR
, true, D40_PHY_CHAN
},
1133 u32 regs
[ARRAY_SIZE(il
)];
1137 struct d40_chan
*d40c
;
1138 unsigned long flags
;
1139 struct d40_base
*base
= data
;
1141 spin_lock_irqsave(&base
->interrupt_lock
, flags
);
1143 /* Read interrupt status of both logical and physical channels */
1144 for (i
= 0; i
< ARRAY_SIZE(il
); i
++)
1145 regs
[i
] = readl(base
->virtbase
+ il
[i
].src
);
1149 chan
= find_next_bit((unsigned long *)regs
,
1150 BITS_PER_LONG
* ARRAY_SIZE(il
), chan
+ 1);
1152 /* No more set bits found? */
1153 if (chan
== BITS_PER_LONG
* ARRAY_SIZE(il
))
1156 row
= chan
/ BITS_PER_LONG
;
1157 idx
= chan
& (BITS_PER_LONG
- 1);
1160 writel(1 << idx
, base
->virtbase
+ il
[row
].clr
);
1162 if (il
[row
].offset
== D40_PHY_CHAN
)
1163 d40c
= base
->lookup_phy_chans
[idx
];
1165 d40c
= base
->lookup_log_chans
[il
[row
].offset
+ idx
];
1166 spin_lock(&d40c
->lock
);
1168 if (!il
[row
].is_error
)
1169 dma_tc_handle(d40c
);
1171 d40_err(base
->dev
, "IRQ chan: %ld offset %d idx %d\n",
1172 chan
, il
[row
].offset
, idx
);
1174 spin_unlock(&d40c
->lock
);
1177 spin_unlock_irqrestore(&base
->interrupt_lock
, flags
);
1182 static int d40_validate_conf(struct d40_chan
*d40c
,
1183 struct stedma40_chan_cfg
*conf
)
1186 u32 dst_event_group
= D40_TYPE_TO_GROUP(conf
->dst_dev_type
);
1187 u32 src_event_group
= D40_TYPE_TO_GROUP(conf
->src_dev_type
);
1188 bool is_log
= conf
->mode
== STEDMA40_MODE_LOGICAL
;
1191 chan_err(d40c
, "Invalid direction.\n");
1195 if (conf
->dst_dev_type
!= STEDMA40_DEV_DST_MEMORY
&&
1196 d40c
->base
->plat_data
->dev_tx
[conf
->dst_dev_type
] == 0 &&
1197 d40c
->runtime_addr
== 0) {
1199 chan_err(d40c
, "Invalid TX channel address (%d)\n",
1200 conf
->dst_dev_type
);
1204 if (conf
->src_dev_type
!= STEDMA40_DEV_SRC_MEMORY
&&
1205 d40c
->base
->plat_data
->dev_rx
[conf
->src_dev_type
] == 0 &&
1206 d40c
->runtime_addr
== 0) {
1207 chan_err(d40c
, "Invalid RX channel address (%d)\n",
1208 conf
->src_dev_type
);
1212 if (conf
->dir
== STEDMA40_MEM_TO_PERIPH
&&
1213 dst_event_group
== STEDMA40_DEV_DST_MEMORY
) {
1214 chan_err(d40c
, "Invalid dst\n");
1218 if (conf
->dir
== STEDMA40_PERIPH_TO_MEM
&&
1219 src_event_group
== STEDMA40_DEV_SRC_MEMORY
) {
1220 chan_err(d40c
, "Invalid src\n");
1224 if (src_event_group
== STEDMA40_DEV_SRC_MEMORY
&&
1225 dst_event_group
== STEDMA40_DEV_DST_MEMORY
&& is_log
) {
1226 chan_err(d40c
, "No event line\n");
1230 if (conf
->dir
== STEDMA40_PERIPH_TO_PERIPH
&&
1231 (src_event_group
!= dst_event_group
)) {
1232 chan_err(d40c
, "Invalid event group\n");
1236 if (conf
->dir
== STEDMA40_PERIPH_TO_PERIPH
) {
1238 * DMAC HW supports it. Will be added to this driver,
1239 * in case any dma client requires it.
1241 chan_err(d40c
, "periph to periph not supported\n");
1245 if (d40_psize_2_burst_size(is_log
, conf
->src_info
.psize
) *
1246 (1 << conf
->src_info
.data_width
) !=
1247 d40_psize_2_burst_size(is_log
, conf
->dst_info
.psize
) *
1248 (1 << conf
->dst_info
.data_width
)) {
1250 * The DMAC hardware only supports
1251 * src (burst x width) == dst (burst x width)
1254 chan_err(d40c
, "src (burst x width) != dst (burst x width)\n");
1261 static bool d40_alloc_mask_set(struct d40_phy_res
*phy
, bool is_src
,
1262 int log_event_line
, bool is_log
)
1264 unsigned long flags
;
1265 spin_lock_irqsave(&phy
->lock
, flags
);
1267 /* Physical interrupts are masked per physical full channel */
1268 if (phy
->allocated_src
== D40_ALLOC_FREE
&&
1269 phy
->allocated_dst
== D40_ALLOC_FREE
) {
1270 phy
->allocated_dst
= D40_ALLOC_PHY
;
1271 phy
->allocated_src
= D40_ALLOC_PHY
;
1277 /* Logical channel */
1279 if (phy
->allocated_src
== D40_ALLOC_PHY
)
1282 if (phy
->allocated_src
== D40_ALLOC_FREE
)
1283 phy
->allocated_src
= D40_ALLOC_LOG_FREE
;
1285 if (!(phy
->allocated_src
& (1 << log_event_line
))) {
1286 phy
->allocated_src
|= 1 << log_event_line
;
1291 if (phy
->allocated_dst
== D40_ALLOC_PHY
)
1294 if (phy
->allocated_dst
== D40_ALLOC_FREE
)
1295 phy
->allocated_dst
= D40_ALLOC_LOG_FREE
;
1297 if (!(phy
->allocated_dst
& (1 << log_event_line
))) {
1298 phy
->allocated_dst
|= 1 << log_event_line
;
1305 spin_unlock_irqrestore(&phy
->lock
, flags
);
1308 spin_unlock_irqrestore(&phy
->lock
, flags
);
1312 static bool d40_alloc_mask_free(struct d40_phy_res
*phy
, bool is_src
,
1315 unsigned long flags
;
1316 bool is_free
= false;
1318 spin_lock_irqsave(&phy
->lock
, flags
);
1319 if (!log_event_line
) {
1320 phy
->allocated_dst
= D40_ALLOC_FREE
;
1321 phy
->allocated_src
= D40_ALLOC_FREE
;
1326 /* Logical channel */
1328 phy
->allocated_src
&= ~(1 << log_event_line
);
1329 if (phy
->allocated_src
== D40_ALLOC_LOG_FREE
)
1330 phy
->allocated_src
= D40_ALLOC_FREE
;
1332 phy
->allocated_dst
&= ~(1 << log_event_line
);
1333 if (phy
->allocated_dst
== D40_ALLOC_LOG_FREE
)
1334 phy
->allocated_dst
= D40_ALLOC_FREE
;
1337 is_free
= ((phy
->allocated_src
| phy
->allocated_dst
) ==
1341 spin_unlock_irqrestore(&phy
->lock
, flags
);
1346 static int d40_allocate_channel(struct d40_chan
*d40c
)
1351 struct d40_phy_res
*phys
;
1356 bool is_log
= d40c
->dma_cfg
.mode
== STEDMA40_MODE_LOGICAL
;
1358 phys
= d40c
->base
->phy_res
;
1360 if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1361 dev_type
= d40c
->dma_cfg
.src_dev_type
;
1362 log_num
= 2 * dev_type
;
1364 } else if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1365 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1366 /* dst event lines are used for logical memcpy */
1367 dev_type
= d40c
->dma_cfg
.dst_dev_type
;
1368 log_num
= 2 * dev_type
+ 1;
1373 event_group
= D40_TYPE_TO_GROUP(dev_type
);
1374 event_line
= D40_TYPE_TO_EVENT(dev_type
);
1377 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1378 /* Find physical half channel */
1379 for (i
= 0; i
< d40c
->base
->num_phy_chans
; i
++) {
1381 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1386 for (j
= 0; j
< d40c
->base
->num_phy_chans
; j
+= 8) {
1387 int phy_num
= j
+ event_group
* 2;
1388 for (i
= phy_num
; i
< phy_num
+ 2; i
++) {
1389 if (d40_alloc_mask_set(&phys
[i
],
1398 d40c
->phy_chan
= &phys
[i
];
1399 d40c
->log_num
= D40_PHY_CHAN
;
1405 /* Find logical channel */
1406 for (j
= 0; j
< d40c
->base
->num_phy_chans
; j
+= 8) {
1407 int phy_num
= j
+ event_group
* 2;
1409 * Spread logical channels across all available physical rather
1410 * than pack every logical channel at the first available phy
1414 for (i
= phy_num
; i
< phy_num
+ 2; i
++) {
1415 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1416 event_line
, is_log
))
1420 for (i
= phy_num
+ 1; i
>= phy_num
; i
--) {
1421 if (d40_alloc_mask_set(&phys
[i
], is_src
,
1422 event_line
, is_log
))
1430 d40c
->phy_chan
= &phys
[i
];
1431 d40c
->log_num
= log_num
;
1435 d40c
->base
->lookup_log_chans
[d40c
->log_num
] = d40c
;
1437 d40c
->base
->lookup_phy_chans
[d40c
->phy_chan
->num
] = d40c
;
1443 static int d40_config_memcpy(struct d40_chan
*d40c
)
1445 dma_cap_mask_t cap
= d40c
->chan
.device
->cap_mask
;
1447 if (dma_has_cap(DMA_MEMCPY
, cap
) && !dma_has_cap(DMA_SLAVE
, cap
)) {
1448 d40c
->dma_cfg
= *d40c
->base
->plat_data
->memcpy_conf_log
;
1449 d40c
->dma_cfg
.src_dev_type
= STEDMA40_DEV_SRC_MEMORY
;
1450 d40c
->dma_cfg
.dst_dev_type
= d40c
->base
->plat_data
->
1451 memcpy
[d40c
->chan
.chan_id
];
1453 } else if (dma_has_cap(DMA_MEMCPY
, cap
) &&
1454 dma_has_cap(DMA_SLAVE
, cap
)) {
1455 d40c
->dma_cfg
= *d40c
->base
->plat_data
->memcpy_conf_phy
;
1457 chan_err(d40c
, "No memcpy\n");
1465 static int d40_free_dma(struct d40_chan
*d40c
)
1470 struct d40_phy_res
*phy
= d40c
->phy_chan
;
1473 struct d40_desc
*_d
;
1476 /* Terminate all queued and active transfers */
1479 /* Release client owned descriptors */
1480 if (!list_empty(&d40c
->client
))
1481 list_for_each_entry_safe(d
, _d
, &d40c
->client
, node
) {
1482 d40_pool_lli_free(d40c
, d
);
1484 d40_desc_free(d40c
, d
);
1488 chan_err(d40c
, "phy == null\n");
1492 if (phy
->allocated_src
== D40_ALLOC_FREE
&&
1493 phy
->allocated_dst
== D40_ALLOC_FREE
) {
1494 chan_err(d40c
, "channel already free\n");
1498 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1499 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1500 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
1502 } else if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1503 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
1506 chan_err(d40c
, "Unknown direction\n");
1510 res
= d40_channel_execute_command(d40c
, D40_DMA_SUSPEND_REQ
);
1512 chan_err(d40c
, "suspend failed\n");
1516 if (chan_is_logical(d40c
)) {
1517 /* Release logical channel, deactivate the event line */
1519 d40_config_set_event(d40c
, false);
1520 d40c
->base
->lookup_log_chans
[d40c
->log_num
] = NULL
;
1523 * Check if there are more logical allocation
1524 * on this phy channel.
1526 if (!d40_alloc_mask_free(phy
, is_src
, event
)) {
1527 /* Resume the other logical channels if any */
1528 if (d40_chan_has_events(d40c
)) {
1529 res
= d40_channel_execute_command(d40c
,
1533 "Executing RUN command\n");
1540 (void) d40_alloc_mask_free(phy
, is_src
, 0);
1543 /* Release physical channel */
1544 res
= d40_channel_execute_command(d40c
, D40_DMA_STOP
);
1546 chan_err(d40c
, "Failed to stop channel\n");
1549 d40c
->phy_chan
= NULL
;
1550 d40c
->configured
= false;
1551 d40c
->base
->lookup_phy_chans
[phy
->num
] = NULL
;
1556 static bool d40_is_paused(struct d40_chan
*d40c
)
1558 void __iomem
*chanbase
= chan_base(d40c
);
1559 bool is_paused
= false;
1560 unsigned long flags
;
1561 void __iomem
*active_reg
;
1565 spin_lock_irqsave(&d40c
->lock
, flags
);
1567 if (chan_is_physical(d40c
)) {
1568 if (d40c
->phy_chan
->num
% 2 == 0)
1569 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVE
;
1571 active_reg
= d40c
->base
->virtbase
+ D40_DREG_ACTIVO
;
1573 status
= (readl(active_reg
) &
1574 D40_CHAN_POS_MASK(d40c
->phy_chan
->num
)) >>
1575 D40_CHAN_POS(d40c
->phy_chan
->num
);
1576 if (status
== D40_DMA_SUSPENDED
|| status
== D40_DMA_STOP
)
1582 if (d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
||
1583 d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_MEM
) {
1584 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.dst_dev_type
);
1585 status
= readl(chanbase
+ D40_CHAN_REG_SDLNK
);
1586 } else if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) {
1587 event
= D40_TYPE_TO_EVENT(d40c
->dma_cfg
.src_dev_type
);
1588 status
= readl(chanbase
+ D40_CHAN_REG_SSLNK
);
1590 chan_err(d40c
, "Unknown direction\n");
1594 status
= (status
& D40_EVENTLINE_MASK(event
)) >>
1595 D40_EVENTLINE_POS(event
);
1597 if (status
!= D40_DMA_RUN
)
1600 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1606 static u32
stedma40_residue(struct dma_chan
*chan
)
1608 struct d40_chan
*d40c
=
1609 container_of(chan
, struct d40_chan
, chan
);
1611 unsigned long flags
;
1613 spin_lock_irqsave(&d40c
->lock
, flags
);
1614 bytes_left
= d40_residue(d40c
);
1615 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1620 struct dma_async_tx_descriptor
*stedma40_memcpy_sg(struct dma_chan
*chan
,
1621 struct scatterlist
*sgl_dst
,
1622 struct scatterlist
*sgl_src
,
1623 unsigned int sgl_len
,
1624 unsigned long dma_flags
)
1627 struct d40_desc
*d40d
;
1628 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
,
1630 unsigned long flags
;
1632 if (d40c
->phy_chan
== NULL
) {
1633 chan_err(d40c
, "Unallocated channel.\n");
1634 return ERR_PTR(-EINVAL
);
1637 spin_lock_irqsave(&d40c
->lock
, flags
);
1638 d40d
= d40_desc_get(d40c
);
1643 d40d
->lli_len
= d40_sg_2_dmalen(sgl_dst
, sgl_len
,
1644 d40c
->dma_cfg
.src_info
.data_width
,
1645 d40c
->dma_cfg
.dst_info
.data_width
);
1646 if (d40d
->lli_len
< 0) {
1647 chan_err(d40c
, "Unaligned size\n");
1651 d40d
->lli_current
= 0;
1652 d40d
->txd
.flags
= dma_flags
;
1654 if (chan_is_logical(d40c
)) {
1656 if (d40_pool_lli_alloc(d40c
, d40d
, d40d
->lli_len
, true) < 0) {
1657 chan_err(d40c
, "Out of memory\n");
1661 (void) d40_log_sg_to_lli(sgl_src
,
1664 d40c
->log_def
.lcsp1
,
1665 d40c
->dma_cfg
.src_info
.data_width
,
1666 d40c
->dma_cfg
.dst_info
.data_width
);
1668 (void) d40_log_sg_to_lli(sgl_dst
,
1671 d40c
->log_def
.lcsp3
,
1672 d40c
->dma_cfg
.dst_info
.data_width
,
1673 d40c
->dma_cfg
.src_info
.data_width
);
1675 if (d40_pool_lli_alloc(d40c
, d40d
, d40d
->lli_len
, false) < 0) {
1676 chan_err(d40c
, "Out of memory\n");
1680 res
= d40_phy_sg_to_lli(sgl_src
,
1684 virt_to_phys(d40d
->lli_phy
.src
),
1686 d40c
->dma_cfg
.src_info
.data_width
,
1687 d40c
->dma_cfg
.dst_info
.data_width
,
1688 d40c
->dma_cfg
.src_info
.psize
);
1693 res
= d40_phy_sg_to_lli(sgl_dst
,
1697 virt_to_phys(d40d
->lli_phy
.dst
),
1699 d40c
->dma_cfg
.dst_info
.data_width
,
1700 d40c
->dma_cfg
.src_info
.data_width
,
1701 d40c
->dma_cfg
.dst_info
.psize
);
1706 dma_sync_single_for_device(d40c
->base
->dev
,
1707 d40d
->lli_pool
.dma_addr
,
1708 d40d
->lli_pool
.size
, DMA_TO_DEVICE
);
1711 dma_async_tx_descriptor_init(&d40d
->txd
, chan
);
1713 d40d
->txd
.tx_submit
= d40_tx_submit
;
1715 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1720 d40_desc_free(d40c
, d40d
);
1721 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1724 EXPORT_SYMBOL(stedma40_memcpy_sg
);
1726 bool stedma40_filter(struct dma_chan
*chan
, void *data
)
1728 struct stedma40_chan_cfg
*info
= data
;
1729 struct d40_chan
*d40c
=
1730 container_of(chan
, struct d40_chan
, chan
);
1734 err
= d40_validate_conf(d40c
, info
);
1736 d40c
->dma_cfg
= *info
;
1738 err
= d40_config_memcpy(d40c
);
1741 d40c
->configured
= true;
1745 EXPORT_SYMBOL(stedma40_filter
);
1747 static void __d40_set_prio_rt(struct d40_chan
*d40c
, int dev_type
, bool src
)
1749 bool realtime
= d40c
->dma_cfg
.realtime
;
1750 bool highprio
= d40c
->dma_cfg
.high_priority
;
1751 u32 prioreg
= highprio
? D40_DREG_PSEG1
: D40_DREG_PCEG1
;
1752 u32 rtreg
= realtime
? D40_DREG_RSEG1
: D40_DREG_RCEG1
;
1753 u32 event
= D40_TYPE_TO_EVENT(dev_type
);
1754 u32 group
= D40_TYPE_TO_GROUP(dev_type
);
1755 u32 bit
= 1 << event
;
1757 /* Destination event lines are stored in the upper halfword */
1761 writel(bit
, d40c
->base
->virtbase
+ prioreg
+ group
* 4);
1762 writel(bit
, d40c
->base
->virtbase
+ rtreg
+ group
* 4);
1765 static void d40_set_prio_realtime(struct d40_chan
*d40c
)
1767 if (d40c
->base
->rev
< 3)
1770 if ((d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
) ||
1771 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
))
1772 __d40_set_prio_rt(d40c
, d40c
->dma_cfg
.src_dev_type
, true);
1774 if ((d40c
->dma_cfg
.dir
== STEDMA40_MEM_TO_PERIPH
) ||
1775 (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_PERIPH
))
1776 __d40_set_prio_rt(d40c
, d40c
->dma_cfg
.dst_dev_type
, false);
1779 /* DMA ENGINE functions */
1780 static int d40_alloc_chan_resources(struct dma_chan
*chan
)
1783 unsigned long flags
;
1784 struct d40_chan
*d40c
=
1785 container_of(chan
, struct d40_chan
, chan
);
1787 spin_lock_irqsave(&d40c
->lock
, flags
);
1789 d40c
->completed
= chan
->cookie
= 1;
1791 /* If no dma configuration is set use default configuration (memcpy) */
1792 if (!d40c
->configured
) {
1793 err
= d40_config_memcpy(d40c
);
1795 chan_err(d40c
, "Failed to configure memcpy channel\n");
1799 is_free_phy
= (d40c
->phy_chan
== NULL
);
1801 err
= d40_allocate_channel(d40c
);
1803 chan_err(d40c
, "Failed to allocate channel\n");
1807 /* Fill in basic CFG register values */
1808 d40_phy_cfg(&d40c
->dma_cfg
, &d40c
->src_def_cfg
,
1809 &d40c
->dst_def_cfg
, chan_is_logical(d40c
));
1811 d40_set_prio_realtime(d40c
);
1813 if (chan_is_logical(d40c
)) {
1814 d40_log_cfg(&d40c
->dma_cfg
,
1815 &d40c
->log_def
.lcsp1
, &d40c
->log_def
.lcsp3
);
1817 if (d40c
->dma_cfg
.dir
== STEDMA40_PERIPH_TO_MEM
)
1818 d40c
->lcpa
= d40c
->base
->lcpa_base
+
1819 d40c
->dma_cfg
.src_dev_type
* D40_LCPA_CHAN_SIZE
;
1821 d40c
->lcpa
= d40c
->base
->lcpa_base
+
1822 d40c
->dma_cfg
.dst_dev_type
*
1823 D40_LCPA_CHAN_SIZE
+ D40_LCPA_CHAN_DST_DELTA
;
1827 * Only write channel configuration to the DMA if the physical
1828 * resource is free. In case of multiple logical channels
1829 * on the same physical resource, only the first write is necessary.
1832 d40_config_write(d40c
);
1834 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1838 static void d40_free_chan_resources(struct dma_chan
*chan
)
1840 struct d40_chan
*d40c
=
1841 container_of(chan
, struct d40_chan
, chan
);
1843 unsigned long flags
;
1845 if (d40c
->phy_chan
== NULL
) {
1846 chan_err(d40c
, "Cannot free unallocated channel\n");
1851 spin_lock_irqsave(&d40c
->lock
, flags
);
1853 err
= d40_free_dma(d40c
);
1856 chan_err(d40c
, "Failed to free channel\n");
1857 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1860 static struct dma_async_tx_descriptor
*d40_prep_memcpy(struct dma_chan
*chan
,
1864 unsigned long dma_flags
)
1866 struct d40_desc
*d40d
;
1867 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
,
1869 unsigned long flags
;
1871 if (d40c
->phy_chan
== NULL
) {
1872 chan_err(d40c
, "Channel is not allocated.\n");
1873 return ERR_PTR(-EINVAL
);
1876 spin_lock_irqsave(&d40c
->lock
, flags
);
1877 d40d
= d40_desc_get(d40c
);
1880 chan_err(d40c
, "Descriptor is NULL\n");
1884 d40d
->txd
.flags
= dma_flags
;
1885 d40d
->lli_len
= d40_size_2_dmalen(size
,
1886 d40c
->dma_cfg
.src_info
.data_width
,
1887 d40c
->dma_cfg
.dst_info
.data_width
);
1888 if (d40d
->lli_len
< 0) {
1889 chan_err(d40c
, "Unaligned size\n");
1894 dma_async_tx_descriptor_init(&d40d
->txd
, chan
);
1896 d40d
->txd
.tx_submit
= d40_tx_submit
;
1898 if (chan_is_logical(d40c
)) {
1900 if (d40_pool_lli_alloc(d40c
,d40d
, d40d
->lli_len
, true) < 0) {
1901 chan_err(d40c
, "Out of memory\n");
1904 d40d
->lli_current
= 0;
1906 if (d40_log_buf_to_lli(d40d
->lli_log
.src
,
1909 d40c
->log_def
.lcsp1
,
1910 d40c
->dma_cfg
.src_info
.data_width
,
1911 d40c
->dma_cfg
.dst_info
.data_width
,
1915 if (d40_log_buf_to_lli(d40d
->lli_log
.dst
,
1918 d40c
->log_def
.lcsp3
,
1919 d40c
->dma_cfg
.dst_info
.data_width
,
1920 d40c
->dma_cfg
.src_info
.data_width
,
1926 if (d40_pool_lli_alloc(d40c
, d40d
, d40d
->lli_len
, false) < 0) {
1927 chan_err(d40c
, "Out of memory\n");
1931 if (d40_phy_buf_to_lli(d40d
->lli_phy
.src
,
1934 d40c
->dma_cfg
.src_info
.psize
,
1938 d40c
->dma_cfg
.src_info
.data_width
,
1939 d40c
->dma_cfg
.dst_info
.data_width
,
1943 if (d40_phy_buf_to_lli(d40d
->lli_phy
.dst
,
1946 d40c
->dma_cfg
.dst_info
.psize
,
1950 d40c
->dma_cfg
.dst_info
.data_width
,
1951 d40c
->dma_cfg
.src_info
.data_width
,
1955 dma_sync_single_for_device(d40c
->base
->dev
,
1956 d40d
->lli_pool
.dma_addr
,
1957 d40d
->lli_pool
.size
, DMA_TO_DEVICE
);
1960 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1965 d40_desc_free(d40c
, d40d
);
1966 spin_unlock_irqrestore(&d40c
->lock
, flags
);
1970 static struct dma_async_tx_descriptor
*
1971 d40_prep_sg(struct dma_chan
*chan
,
1972 struct scatterlist
*dst_sg
, unsigned int dst_nents
,
1973 struct scatterlist
*src_sg
, unsigned int src_nents
,
1974 unsigned long dma_flags
)
1976 if (dst_nents
!= src_nents
)
1979 return stedma40_memcpy_sg(chan
, dst_sg
, src_sg
, dst_nents
, dma_flags
);
1982 static int d40_prep_slave_sg_log(struct d40_desc
*d40d
,
1983 struct d40_chan
*d40c
,
1984 struct scatterlist
*sgl
,
1985 unsigned int sg_len
,
1986 enum dma_data_direction direction
,
1987 unsigned long dma_flags
)
1989 dma_addr_t dev_addr
= 0;
1992 d40d
->lli_len
= d40_sg_2_dmalen(sgl
, sg_len
,
1993 d40c
->dma_cfg
.src_info
.data_width
,
1994 d40c
->dma_cfg
.dst_info
.data_width
);
1995 if (d40d
->lli_len
< 0) {
1996 chan_err(d40c
, "Unaligned size\n");
2000 if (d40_pool_lli_alloc(d40c
, d40d
, d40d
->lli_len
, true) < 0) {
2001 chan_err(d40c
, "Out of memory\n");
2005 d40d
->lli_current
= 0;
2007 if (direction
== DMA_FROM_DEVICE
)
2008 if (d40c
->runtime_addr
)
2009 dev_addr
= d40c
->runtime_addr
;
2011 dev_addr
= d40c
->base
->plat_data
->dev_rx
[d40c
->dma_cfg
.src_dev_type
];
2012 else if (direction
== DMA_TO_DEVICE
)
2013 if (d40c
->runtime_addr
)
2014 dev_addr
= d40c
->runtime_addr
;
2016 dev_addr
= d40c
->base
->plat_data
->dev_tx
[d40c
->dma_cfg
.dst_dev_type
];
2021 total_size
= d40_log_sg_to_dev(sgl
, sg_len
,
2024 d40c
->dma_cfg
.src_info
.data_width
,
2025 d40c
->dma_cfg
.dst_info
.data_width
,
2035 static int d40_prep_slave_sg_phy(struct d40_desc
*d40d
,
2036 struct d40_chan
*d40c
,
2037 struct scatterlist
*sgl
,
2038 unsigned int sgl_len
,
2039 enum dma_data_direction direction
,
2040 unsigned long dma_flags
)
2042 dma_addr_t src_dev_addr
;
2043 dma_addr_t dst_dev_addr
;
2046 d40d
->lli_len
= d40_sg_2_dmalen(sgl
, sgl_len
,
2047 d40c
->dma_cfg
.src_info
.data_width
,
2048 d40c
->dma_cfg
.dst_info
.data_width
);
2049 if (d40d
->lli_len
< 0) {
2050 chan_err(d40c
, "Unaligned size\n");
2054 if (d40_pool_lli_alloc(d40c
, d40d
, d40d
->lli_len
, false) < 0) {
2055 chan_err(d40c
, "Out of memory\n");
2059 d40d
->lli_current
= 0;
2061 if (direction
== DMA_FROM_DEVICE
) {
2063 if (d40c
->runtime_addr
)
2064 src_dev_addr
= d40c
->runtime_addr
;
2066 src_dev_addr
= d40c
->base
->plat_data
->dev_rx
[d40c
->dma_cfg
.src_dev_type
];
2067 } else if (direction
== DMA_TO_DEVICE
) {
2068 if (d40c
->runtime_addr
)
2069 dst_dev_addr
= d40c
->runtime_addr
;
2071 dst_dev_addr
= d40c
->base
->plat_data
->dev_tx
[d40c
->dma_cfg
.dst_dev_type
];
2076 res
= d40_phy_sg_to_lli(sgl
,
2080 virt_to_phys(d40d
->lli_phy
.src
),
2082 d40c
->dma_cfg
.src_info
.data_width
,
2083 d40c
->dma_cfg
.dst_info
.data_width
,
2084 d40c
->dma_cfg
.src_info
.psize
);
2088 res
= d40_phy_sg_to_lli(sgl
,
2092 virt_to_phys(d40d
->lli_phy
.dst
),
2094 d40c
->dma_cfg
.dst_info
.data_width
,
2095 d40c
->dma_cfg
.src_info
.data_width
,
2096 d40c
->dma_cfg
.dst_info
.psize
);
2100 dma_sync_single_for_device(d40c
->base
->dev
, d40d
->lli_pool
.dma_addr
,
2101 d40d
->lli_pool
.size
, DMA_TO_DEVICE
);
2105 static struct dma_async_tx_descriptor
*d40_prep_slave_sg(struct dma_chan
*chan
,
2106 struct scatterlist
*sgl
,
2107 unsigned int sg_len
,
2108 enum dma_data_direction direction
,
2109 unsigned long dma_flags
)
2111 struct d40_desc
*d40d
;
2112 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
,
2114 unsigned long flags
;
2117 if (d40c
->phy_chan
== NULL
) {
2118 chan_err(d40c
, "Cannot prepare unallocated channel\n");
2119 return ERR_PTR(-EINVAL
);
2122 spin_lock_irqsave(&d40c
->lock
, flags
);
2123 d40d
= d40_desc_get(d40c
);
2128 if (chan_is_logical(d40c
))
2129 err
= d40_prep_slave_sg_log(d40d
, d40c
, sgl
, sg_len
,
2130 direction
, dma_flags
);
2132 err
= d40_prep_slave_sg_phy(d40d
, d40c
, sgl
, sg_len
,
2133 direction
, dma_flags
);
2135 chan_err(d40c
, "Failed to prepare %s slave sg job: %d\n",
2136 chan_is_logical(d40c
) ? "log" : "phy", err
);
2140 d40d
->txd
.flags
= dma_flags
;
2142 dma_async_tx_descriptor_init(&d40d
->txd
, chan
);
2144 d40d
->txd
.tx_submit
= d40_tx_submit
;
2146 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2151 d40_desc_free(d40c
, d40d
);
2152 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2156 static enum dma_status
d40_tx_status(struct dma_chan
*chan
,
2157 dma_cookie_t cookie
,
2158 struct dma_tx_state
*txstate
)
2160 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2161 dma_cookie_t last_used
;
2162 dma_cookie_t last_complete
;
2165 if (d40c
->phy_chan
== NULL
) {
2166 chan_err(d40c
, "Cannot read status of unallocated channel\n");
2170 last_complete
= d40c
->completed
;
2171 last_used
= chan
->cookie
;
2173 if (d40_is_paused(d40c
))
2176 ret
= dma_async_is_complete(cookie
, last_complete
, last_used
);
2178 dma_set_tx_state(txstate
, last_complete
, last_used
,
2179 stedma40_residue(chan
));
2184 static void d40_issue_pending(struct dma_chan
*chan
)
2186 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2187 unsigned long flags
;
2189 if (d40c
->phy_chan
== NULL
) {
2190 chan_err(d40c
, "Channel is not allocated!\n");
2194 spin_lock_irqsave(&d40c
->lock
, flags
);
2196 /* Busy means that pending jobs are already being processed */
2198 (void) d40_queue_start(d40c
);
2200 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2203 /* Runtime reconfiguration extension */
2204 static void d40_set_runtime_config(struct dma_chan
*chan
,
2205 struct dma_slave_config
*config
)
2207 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2208 struct stedma40_chan_cfg
*cfg
= &d40c
->dma_cfg
;
2209 enum dma_slave_buswidth config_addr_width
;
2210 dma_addr_t config_addr
;
2211 u32 config_maxburst
;
2212 enum stedma40_periph_data_width addr_width
;
2215 if (config
->direction
== DMA_FROM_DEVICE
) {
2216 dma_addr_t dev_addr_rx
=
2217 d40c
->base
->plat_data
->dev_rx
[cfg
->src_dev_type
];
2219 config_addr
= config
->src_addr
;
2221 dev_dbg(d40c
->base
->dev
,
2222 "channel has a pre-wired RX address %08x "
2223 "overriding with %08x\n",
2224 dev_addr_rx
, config_addr
);
2225 if (cfg
->dir
!= STEDMA40_PERIPH_TO_MEM
)
2226 dev_dbg(d40c
->base
->dev
,
2227 "channel was not configured for peripheral "
2228 "to memory transfer (%d) overriding\n",
2230 cfg
->dir
= STEDMA40_PERIPH_TO_MEM
;
2232 config_addr_width
= config
->src_addr_width
;
2233 config_maxburst
= config
->src_maxburst
;
2235 } else if (config
->direction
== DMA_TO_DEVICE
) {
2236 dma_addr_t dev_addr_tx
=
2237 d40c
->base
->plat_data
->dev_tx
[cfg
->dst_dev_type
];
2239 config_addr
= config
->dst_addr
;
2241 dev_dbg(d40c
->base
->dev
,
2242 "channel has a pre-wired TX address %08x "
2243 "overriding with %08x\n",
2244 dev_addr_tx
, config_addr
);
2245 if (cfg
->dir
!= STEDMA40_MEM_TO_PERIPH
)
2246 dev_dbg(d40c
->base
->dev
,
2247 "channel was not configured for memory "
2248 "to peripheral transfer (%d) overriding\n",
2250 cfg
->dir
= STEDMA40_MEM_TO_PERIPH
;
2252 config_addr_width
= config
->dst_addr_width
;
2253 config_maxburst
= config
->dst_maxburst
;
2256 dev_err(d40c
->base
->dev
,
2257 "unrecognized channel direction %d\n",
2262 switch (config_addr_width
) {
2263 case DMA_SLAVE_BUSWIDTH_1_BYTE
:
2264 addr_width
= STEDMA40_BYTE_WIDTH
;
2266 case DMA_SLAVE_BUSWIDTH_2_BYTES
:
2267 addr_width
= STEDMA40_HALFWORD_WIDTH
;
2269 case DMA_SLAVE_BUSWIDTH_4_BYTES
:
2270 addr_width
= STEDMA40_WORD_WIDTH
;
2272 case DMA_SLAVE_BUSWIDTH_8_BYTES
:
2273 addr_width
= STEDMA40_DOUBLEWORD_WIDTH
;
2276 dev_err(d40c
->base
->dev
,
2277 "illegal peripheral address width "
2279 config
->src_addr_width
);
2283 if (chan_is_logical(d40c
)) {
2284 if (config_maxburst
>= 16)
2285 psize
= STEDMA40_PSIZE_LOG_16
;
2286 else if (config_maxburst
>= 8)
2287 psize
= STEDMA40_PSIZE_LOG_8
;
2288 else if (config_maxburst
>= 4)
2289 psize
= STEDMA40_PSIZE_LOG_4
;
2291 psize
= STEDMA40_PSIZE_LOG_1
;
2293 if (config_maxburst
>= 16)
2294 psize
= STEDMA40_PSIZE_PHY_16
;
2295 else if (config_maxburst
>= 8)
2296 psize
= STEDMA40_PSIZE_PHY_8
;
2297 else if (config_maxburst
>= 4)
2298 psize
= STEDMA40_PSIZE_PHY_4
;
2299 else if (config_maxburst
>= 2)
2300 psize
= STEDMA40_PSIZE_PHY_2
;
2302 psize
= STEDMA40_PSIZE_PHY_1
;
2305 /* Set up all the endpoint configs */
2306 cfg
->src_info
.data_width
= addr_width
;
2307 cfg
->src_info
.psize
= psize
;
2308 cfg
->src_info
.big_endian
= false;
2309 cfg
->src_info
.flow_ctrl
= STEDMA40_NO_FLOW_CTRL
;
2310 cfg
->dst_info
.data_width
= addr_width
;
2311 cfg
->dst_info
.psize
= psize
;
2312 cfg
->dst_info
.big_endian
= false;
2313 cfg
->dst_info
.flow_ctrl
= STEDMA40_NO_FLOW_CTRL
;
2315 /* Fill in register values */
2316 if (chan_is_logical(d40c
))
2317 d40_log_cfg(cfg
, &d40c
->log_def
.lcsp1
, &d40c
->log_def
.lcsp3
);
2319 d40_phy_cfg(cfg
, &d40c
->src_def_cfg
,
2320 &d40c
->dst_def_cfg
, false);
2322 /* These settings will take precedence later */
2323 d40c
->runtime_addr
= config_addr
;
2324 d40c
->runtime_direction
= config
->direction
;
2325 dev_dbg(d40c
->base
->dev
,
2326 "configured channel %s for %s, data width %d, "
2327 "maxburst %d bytes, LE, no flow control\n",
2328 dma_chan_name(chan
),
2329 (config
->direction
== DMA_FROM_DEVICE
) ? "RX" : "TX",
2334 static int d40_control(struct dma_chan
*chan
, enum dma_ctrl_cmd cmd
,
2337 unsigned long flags
;
2338 struct d40_chan
*d40c
= container_of(chan
, struct d40_chan
, chan
);
2340 if (d40c
->phy_chan
== NULL
) {
2341 chan_err(d40c
, "Channel is not allocated!\n");
2346 case DMA_TERMINATE_ALL
:
2347 spin_lock_irqsave(&d40c
->lock
, flags
);
2349 spin_unlock_irqrestore(&d40c
->lock
, flags
);
2352 return d40_pause(chan
);
2354 return d40_resume(chan
);
2355 case DMA_SLAVE_CONFIG
:
2356 d40_set_runtime_config(chan
,
2357 (struct dma_slave_config
*) arg
);
2363 /* Other commands are unimplemented */
2367 /* Initialization functions */
2369 static void __init
d40_chan_init(struct d40_base
*base
, struct dma_device
*dma
,
2370 struct d40_chan
*chans
, int offset
,
2374 struct d40_chan
*d40c
;
2376 INIT_LIST_HEAD(&dma
->channels
);
2378 for (i
= offset
; i
< offset
+ num_chans
; i
++) {
2381 d40c
->chan
.device
= dma
;
2383 spin_lock_init(&d40c
->lock
);
2385 d40c
->log_num
= D40_PHY_CHAN
;
2387 INIT_LIST_HEAD(&d40c
->active
);
2388 INIT_LIST_HEAD(&d40c
->queue
);
2389 INIT_LIST_HEAD(&d40c
->client
);
2391 tasklet_init(&d40c
->tasklet
, dma_tasklet
,
2392 (unsigned long) d40c
);
2394 list_add_tail(&d40c
->chan
.device_node
,
2399 static int __init
d40_dmaengine_init(struct d40_base
*base
,
2400 int num_reserved_chans
)
2404 d40_chan_init(base
, &base
->dma_slave
, base
->log_chans
,
2405 0, base
->num_log_chans
);
2407 dma_cap_zero(base
->dma_slave
.cap_mask
);
2408 dma_cap_set(DMA_SLAVE
, base
->dma_slave
.cap_mask
);
2410 base
->dma_slave
.device_alloc_chan_resources
= d40_alloc_chan_resources
;
2411 base
->dma_slave
.device_free_chan_resources
= d40_free_chan_resources
;
2412 base
->dma_slave
.device_prep_dma_memcpy
= d40_prep_memcpy
;
2413 base
->dma_slave
.device_prep_dma_sg
= d40_prep_sg
;
2414 base
->dma_slave
.device_prep_slave_sg
= d40_prep_slave_sg
;
2415 base
->dma_slave
.device_tx_status
= d40_tx_status
;
2416 base
->dma_slave
.device_issue_pending
= d40_issue_pending
;
2417 base
->dma_slave
.device_control
= d40_control
;
2418 base
->dma_slave
.dev
= base
->dev
;
2420 err
= dma_async_device_register(&base
->dma_slave
);
2423 d40_err(base
->dev
, "Failed to register slave channels\n");
2427 d40_chan_init(base
, &base
->dma_memcpy
, base
->log_chans
,
2428 base
->num_log_chans
, base
->plat_data
->memcpy_len
);
2430 dma_cap_zero(base
->dma_memcpy
.cap_mask
);
2431 dma_cap_set(DMA_MEMCPY
, base
->dma_memcpy
.cap_mask
);
2432 dma_cap_set(DMA_SG
, base
->dma_slave
.cap_mask
);
2434 base
->dma_memcpy
.device_alloc_chan_resources
= d40_alloc_chan_resources
;
2435 base
->dma_memcpy
.device_free_chan_resources
= d40_free_chan_resources
;
2436 base
->dma_memcpy
.device_prep_dma_memcpy
= d40_prep_memcpy
;
2437 base
->dma_slave
.device_prep_dma_sg
= d40_prep_sg
;
2438 base
->dma_memcpy
.device_prep_slave_sg
= d40_prep_slave_sg
;
2439 base
->dma_memcpy
.device_tx_status
= d40_tx_status
;
2440 base
->dma_memcpy
.device_issue_pending
= d40_issue_pending
;
2441 base
->dma_memcpy
.device_control
= d40_control
;
2442 base
->dma_memcpy
.dev
= base
->dev
;
2444 * This controller can only access address at even
2445 * 32bit boundaries, i.e. 2^2
2447 base
->dma_memcpy
.copy_align
= 2;
2449 err
= dma_async_device_register(&base
->dma_memcpy
);
2453 "Failed to regsiter memcpy only channels\n");
2457 d40_chan_init(base
, &base
->dma_both
, base
->phy_chans
,
2458 0, num_reserved_chans
);
2460 dma_cap_zero(base
->dma_both
.cap_mask
);
2461 dma_cap_set(DMA_SLAVE
, base
->dma_both
.cap_mask
);
2462 dma_cap_set(DMA_MEMCPY
, base
->dma_both
.cap_mask
);
2463 dma_cap_set(DMA_SG
, base
->dma_slave
.cap_mask
);
2465 base
->dma_both
.device_alloc_chan_resources
= d40_alloc_chan_resources
;
2466 base
->dma_both
.device_free_chan_resources
= d40_free_chan_resources
;
2467 base
->dma_both
.device_prep_dma_memcpy
= d40_prep_memcpy
;
2468 base
->dma_slave
.device_prep_dma_sg
= d40_prep_sg
;
2469 base
->dma_both
.device_prep_slave_sg
= d40_prep_slave_sg
;
2470 base
->dma_both
.device_tx_status
= d40_tx_status
;
2471 base
->dma_both
.device_issue_pending
= d40_issue_pending
;
2472 base
->dma_both
.device_control
= d40_control
;
2473 base
->dma_both
.dev
= base
->dev
;
2474 base
->dma_both
.copy_align
= 2;
2475 err
= dma_async_device_register(&base
->dma_both
);
2479 "Failed to register logical and physical capable channels\n");
2484 dma_async_device_unregister(&base
->dma_memcpy
);
2486 dma_async_device_unregister(&base
->dma_slave
);
2491 /* Initialization functions. */
2493 static int __init
d40_phy_res_init(struct d40_base
*base
)
2496 int num_phy_chans_avail
= 0;
2498 int odd_even_bit
= -2;
2500 val
[0] = readl(base
->virtbase
+ D40_DREG_PRSME
);
2501 val
[1] = readl(base
->virtbase
+ D40_DREG_PRSMO
);
2503 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2504 base
->phy_res
[i
].num
= i
;
2505 odd_even_bit
+= 2 * ((i
% 2) == 0);
2506 if (((val
[i
% 2] >> odd_even_bit
) & 3) == 1) {
2507 /* Mark security only channels as occupied */
2508 base
->phy_res
[i
].allocated_src
= D40_ALLOC_PHY
;
2509 base
->phy_res
[i
].allocated_dst
= D40_ALLOC_PHY
;
2511 base
->phy_res
[i
].allocated_src
= D40_ALLOC_FREE
;
2512 base
->phy_res
[i
].allocated_dst
= D40_ALLOC_FREE
;
2513 num_phy_chans_avail
++;
2515 spin_lock_init(&base
->phy_res
[i
].lock
);
2518 /* Mark disabled channels as occupied */
2519 for (i
= 0; base
->plat_data
->disabled_channels
[i
] != -1; i
++) {
2520 int chan
= base
->plat_data
->disabled_channels
[i
];
2522 base
->phy_res
[chan
].allocated_src
= D40_ALLOC_PHY
;
2523 base
->phy_res
[chan
].allocated_dst
= D40_ALLOC_PHY
;
2524 num_phy_chans_avail
--;
2527 dev_info(base
->dev
, "%d of %d physical DMA channels available\n",
2528 num_phy_chans_avail
, base
->num_phy_chans
);
2530 /* Verify settings extended vs standard */
2531 val
[0] = readl(base
->virtbase
+ D40_DREG_PRTYP
);
2533 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2535 if (base
->phy_res
[i
].allocated_src
== D40_ALLOC_FREE
&&
2536 (val
[0] & 0x3) != 1)
2538 "[%s] INFO: channel %d is misconfigured (%d)\n",
2539 __func__
, i
, val
[0] & 0x3);
2541 val
[0] = val
[0] >> 2;
2544 return num_phy_chans_avail
;
2547 static struct d40_base
* __init
d40_hw_detect_init(struct platform_device
*pdev
)
2549 static const struct d40_reg_val dma_id_regs
[] = {
2551 { .reg
= D40_DREG_PERIPHID0
, .val
= 0x0040},
2552 { .reg
= D40_DREG_PERIPHID1
, .val
= 0x0000},
2554 * D40_DREG_PERIPHID2 Depends on HW revision:
2555 * DB8500ed has 0x0008,
2557 * DB8500v1 has 0x0028
2558 * DB8500v2 has 0x0038
2560 { .reg
= D40_DREG_PERIPHID3
, .val
= 0x0000},
2563 { .reg
= D40_DREG_CELLID0
, .val
= 0x000d},
2564 { .reg
= D40_DREG_CELLID1
, .val
= 0x00f0},
2565 { .reg
= D40_DREG_CELLID2
, .val
= 0x0005},
2566 { .reg
= D40_DREG_CELLID3
, .val
= 0x00b1}
2568 struct stedma40_platform_data
*plat_data
;
2569 struct clk
*clk
= NULL
;
2570 void __iomem
*virtbase
= NULL
;
2571 struct resource
*res
= NULL
;
2572 struct d40_base
*base
= NULL
;
2573 int num_log_chans
= 0;
2579 clk
= clk_get(&pdev
->dev
, NULL
);
2582 d40_err(&pdev
->dev
, "No matching clock found\n");
2588 /* Get IO for DMAC base address */
2589 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "base");
2593 if (request_mem_region(res
->start
, resource_size(res
),
2594 D40_NAME
" I/O base") == NULL
)
2597 virtbase
= ioremap(res
->start
, resource_size(res
));
2601 /* HW version check */
2602 for (i
= 0; i
< ARRAY_SIZE(dma_id_regs
); i
++) {
2603 if (dma_id_regs
[i
].val
!=
2604 readl(virtbase
+ dma_id_regs
[i
].reg
)) {
2606 "Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n",
2609 readl(virtbase
+ dma_id_regs
[i
].reg
));
2614 /* Get silicon revision and designer */
2615 val
= readl(virtbase
+ D40_DREG_PERIPHID2
);
2617 if ((val
& D40_DREG_PERIPHID2_DESIGNER_MASK
) !=
2619 d40_err(&pdev
->dev
, "Unknown designer! Got %x wanted %x\n",
2620 val
& D40_DREG_PERIPHID2_DESIGNER_MASK
,
2625 rev
= (val
& D40_DREG_PERIPHID2_REV_MASK
) >>
2626 D40_DREG_PERIPHID2_REV_POS
;
2628 /* The number of physical channels on this HW */
2629 num_phy_chans
= 4 * (readl(virtbase
+ D40_DREG_ICFG
) & 0x7) + 4;
2631 dev_info(&pdev
->dev
, "hardware revision: %d @ 0x%x\n",
2634 plat_data
= pdev
->dev
.platform_data
;
2636 /* Count the number of logical channels in use */
2637 for (i
= 0; i
< plat_data
->dev_len
; i
++)
2638 if (plat_data
->dev_rx
[i
] != 0)
2641 for (i
= 0; i
< plat_data
->dev_len
; i
++)
2642 if (plat_data
->dev_tx
[i
] != 0)
2645 base
= kzalloc(ALIGN(sizeof(struct d40_base
), 4) +
2646 (num_phy_chans
+ num_log_chans
+ plat_data
->memcpy_len
) *
2647 sizeof(struct d40_chan
), GFP_KERNEL
);
2650 d40_err(&pdev
->dev
, "Out of memory\n");
2656 base
->num_phy_chans
= num_phy_chans
;
2657 base
->num_log_chans
= num_log_chans
;
2658 base
->phy_start
= res
->start
;
2659 base
->phy_size
= resource_size(res
);
2660 base
->virtbase
= virtbase
;
2661 base
->plat_data
= plat_data
;
2662 base
->dev
= &pdev
->dev
;
2663 base
->phy_chans
= ((void *)base
) + ALIGN(sizeof(struct d40_base
), 4);
2664 base
->log_chans
= &base
->phy_chans
[num_phy_chans
];
2666 base
->phy_res
= kzalloc(num_phy_chans
* sizeof(struct d40_phy_res
),
2671 base
->lookup_phy_chans
= kzalloc(num_phy_chans
*
2672 sizeof(struct d40_chan
*),
2674 if (!base
->lookup_phy_chans
)
2677 if (num_log_chans
+ plat_data
->memcpy_len
) {
2679 * The max number of logical channels are event lines for all
2680 * src devices and dst devices
2682 base
->lookup_log_chans
= kzalloc(plat_data
->dev_len
* 2 *
2683 sizeof(struct d40_chan
*),
2685 if (!base
->lookup_log_chans
)
2689 base
->lcla_pool
.alloc_map
= kzalloc(num_phy_chans
*
2690 sizeof(struct d40_desc
*) *
2691 D40_LCLA_LINK_PER_EVENT_GRP
,
2693 if (!base
->lcla_pool
.alloc_map
)
2696 base
->desc_slab
= kmem_cache_create(D40_NAME
, sizeof(struct d40_desc
),
2697 0, SLAB_HWCACHE_ALIGN
,
2699 if (base
->desc_slab
== NULL
)
2712 release_mem_region(res
->start
,
2713 resource_size(res
));
2718 kfree(base
->lcla_pool
.alloc_map
);
2719 kfree(base
->lookup_log_chans
);
2720 kfree(base
->lookup_phy_chans
);
2721 kfree(base
->phy_res
);
2728 static void __init
d40_hw_init(struct d40_base
*base
)
2731 static const struct d40_reg_val dma_init_reg
[] = {
2732 /* Clock every part of the DMA block from start */
2733 { .reg
= D40_DREG_GCC
, .val
= 0x0000ff01},
2735 /* Interrupts on all logical channels */
2736 { .reg
= D40_DREG_LCMIS0
, .val
= 0xFFFFFFFF},
2737 { .reg
= D40_DREG_LCMIS1
, .val
= 0xFFFFFFFF},
2738 { .reg
= D40_DREG_LCMIS2
, .val
= 0xFFFFFFFF},
2739 { .reg
= D40_DREG_LCMIS3
, .val
= 0xFFFFFFFF},
2740 { .reg
= D40_DREG_LCICR0
, .val
= 0xFFFFFFFF},
2741 { .reg
= D40_DREG_LCICR1
, .val
= 0xFFFFFFFF},
2742 { .reg
= D40_DREG_LCICR2
, .val
= 0xFFFFFFFF},
2743 { .reg
= D40_DREG_LCICR3
, .val
= 0xFFFFFFFF},
2744 { .reg
= D40_DREG_LCTIS0
, .val
= 0xFFFFFFFF},
2745 { .reg
= D40_DREG_LCTIS1
, .val
= 0xFFFFFFFF},
2746 { .reg
= D40_DREG_LCTIS2
, .val
= 0xFFFFFFFF},
2747 { .reg
= D40_DREG_LCTIS3
, .val
= 0xFFFFFFFF}
2750 u32 prmseo
[2] = {0, 0};
2751 u32 activeo
[2] = {0xFFFFFFFF, 0xFFFFFFFF};
2755 for (i
= 0; i
< ARRAY_SIZE(dma_init_reg
); i
++)
2756 writel(dma_init_reg
[i
].val
,
2757 base
->virtbase
+ dma_init_reg
[i
].reg
);
2759 /* Configure all our dma channels to default settings */
2760 for (i
= 0; i
< base
->num_phy_chans
; i
++) {
2762 activeo
[i
% 2] = activeo
[i
% 2] << 2;
2764 if (base
->phy_res
[base
->num_phy_chans
- i
- 1].allocated_src
2766 activeo
[i
% 2] |= 3;
2770 /* Enable interrupt # */
2771 pcmis
= (pcmis
<< 1) | 1;
2773 /* Clear interrupt # */
2774 pcicr
= (pcicr
<< 1) | 1;
2776 /* Set channel to physical mode */
2777 prmseo
[i
% 2] = prmseo
[i
% 2] << 2;
2782 writel(prmseo
[1], base
->virtbase
+ D40_DREG_PRMSE
);
2783 writel(prmseo
[0], base
->virtbase
+ D40_DREG_PRMSO
);
2784 writel(activeo
[1], base
->virtbase
+ D40_DREG_ACTIVE
);
2785 writel(activeo
[0], base
->virtbase
+ D40_DREG_ACTIVO
);
2787 /* Write which interrupt to enable */
2788 writel(pcmis
, base
->virtbase
+ D40_DREG_PCMIS
);
2790 /* Write which interrupt to clear */
2791 writel(pcicr
, base
->virtbase
+ D40_DREG_PCICR
);
2795 static int __init
d40_lcla_allocate(struct d40_base
*base
)
2797 struct d40_lcla_pool
*pool
= &base
->lcla_pool
;
2798 unsigned long *page_list
;
2803 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
2804 * To full fill this hardware requirement without wasting 256 kb
2805 * we allocate pages until we get an aligned one.
2807 page_list
= kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS
,
2815 /* Calculating how many pages that are required */
2816 base
->lcla_pool
.pages
= SZ_1K
* base
->num_phy_chans
/ PAGE_SIZE
;
2818 for (i
= 0; i
< MAX_LCLA_ALLOC_ATTEMPTS
; i
++) {
2819 page_list
[i
] = __get_free_pages(GFP_KERNEL
,
2820 base
->lcla_pool
.pages
);
2821 if (!page_list
[i
]) {
2823 d40_err(base
->dev
, "Failed to allocate %d pages.\n",
2824 base
->lcla_pool
.pages
);
2826 for (j
= 0; j
< i
; j
++)
2827 free_pages(page_list
[j
], base
->lcla_pool
.pages
);
2831 if ((virt_to_phys((void *)page_list
[i
]) &
2832 (LCLA_ALIGNMENT
- 1)) == 0)
2836 for (j
= 0; j
< i
; j
++)
2837 free_pages(page_list
[j
], base
->lcla_pool
.pages
);
2839 if (i
< MAX_LCLA_ALLOC_ATTEMPTS
) {
2840 base
->lcla_pool
.base
= (void *)page_list
[i
];
2843 * After many attempts and no succees with finding the correct
2844 * alignment, try with allocating a big buffer.
2847 "[%s] Failed to get %d pages @ 18 bit align.\n",
2848 __func__
, base
->lcla_pool
.pages
);
2849 base
->lcla_pool
.base_unaligned
= kmalloc(SZ_1K
*
2850 base
->num_phy_chans
+
2853 if (!base
->lcla_pool
.base_unaligned
) {
2858 base
->lcla_pool
.base
= PTR_ALIGN(base
->lcla_pool
.base_unaligned
,
2862 pool
->dma_addr
= dma_map_single(base
->dev
, pool
->base
,
2863 SZ_1K
* base
->num_phy_chans
,
2865 if (dma_mapping_error(base
->dev
, pool
->dma_addr
)) {
2871 writel(virt_to_phys(base
->lcla_pool
.base
),
2872 base
->virtbase
+ D40_DREG_LCLA
);
2878 static int __init
d40_probe(struct platform_device
*pdev
)
2882 struct d40_base
*base
;
2883 struct resource
*res
= NULL
;
2884 int num_reserved_chans
;
2887 base
= d40_hw_detect_init(pdev
);
2892 num_reserved_chans
= d40_phy_res_init(base
);
2894 platform_set_drvdata(pdev
, base
);
2896 spin_lock_init(&base
->interrupt_lock
);
2897 spin_lock_init(&base
->execmd_lock
);
2899 /* Get IO for logical channel parameter address */
2900 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "lcpa");
2903 d40_err(&pdev
->dev
, "No \"lcpa\" memory resource\n");
2906 base
->lcpa_size
= resource_size(res
);
2907 base
->phy_lcpa
= res
->start
;
2909 if (request_mem_region(res
->start
, resource_size(res
),
2910 D40_NAME
" I/O lcpa") == NULL
) {
2913 "Failed to request LCPA region 0x%x-0x%x\n",
2914 res
->start
, res
->end
);
2918 /* We make use of ESRAM memory for this. */
2919 val
= readl(base
->virtbase
+ D40_DREG_LCPA
);
2920 if (res
->start
!= val
&& val
!= 0) {
2921 dev_warn(&pdev
->dev
,
2922 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
2923 __func__
, val
, res
->start
);
2925 writel(res
->start
, base
->virtbase
+ D40_DREG_LCPA
);
2927 base
->lcpa_base
= ioremap(res
->start
, resource_size(res
));
2928 if (!base
->lcpa_base
) {
2930 d40_err(&pdev
->dev
, "Failed to ioremap LCPA region\n");
2934 ret
= d40_lcla_allocate(base
);
2936 d40_err(&pdev
->dev
, "Failed to allocate LCLA area\n");
2940 spin_lock_init(&base
->lcla_pool
.lock
);
2942 base
->irq
= platform_get_irq(pdev
, 0);
2944 ret
= request_irq(base
->irq
, d40_handle_interrupt
, 0, D40_NAME
, base
);
2946 d40_err(&pdev
->dev
, "No IRQ defined\n");
2950 err
= d40_dmaengine_init(base
, num_reserved_chans
);
2956 dev_info(base
->dev
, "initialized\n");
2961 if (base
->desc_slab
)
2962 kmem_cache_destroy(base
->desc_slab
);
2964 iounmap(base
->virtbase
);
2966 if (base
->lcla_pool
.dma_addr
)
2967 dma_unmap_single(base
->dev
, base
->lcla_pool
.dma_addr
,
2968 SZ_1K
* base
->num_phy_chans
,
2971 if (!base
->lcla_pool
.base_unaligned
&& base
->lcla_pool
.base
)
2972 free_pages((unsigned long)base
->lcla_pool
.base
,
2973 base
->lcla_pool
.pages
);
2975 kfree(base
->lcla_pool
.base_unaligned
);
2978 release_mem_region(base
->phy_lcpa
,
2980 if (base
->phy_start
)
2981 release_mem_region(base
->phy_start
,
2984 clk_disable(base
->clk
);
2988 kfree(base
->lcla_pool
.alloc_map
);
2989 kfree(base
->lookup_log_chans
);
2990 kfree(base
->lookup_phy_chans
);
2991 kfree(base
->phy_res
);
2995 d40_err(&pdev
->dev
, "probe failed\n");
2999 static struct platform_driver d40_driver
= {
3001 .owner
= THIS_MODULE
,
3006 static int __init
stedma40_init(void)
3008 return platform_driver_probe(&d40_driver
, d40_probe
);
3010 arch_initcall(stedma40_init
);