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edac: Don't add __func__ or __FILE__ for debugf[0-9] msgs
[deliverable/linux.git] / drivers / edac / i5000_edac.c
1 /*
2 * Intel 5000(P/V/X) class Memory Controllers kernel module
3 *
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * Written by Douglas Thompson Linux Networx (http://lnxi.com)
8 * norsk5@xmission.com
9 *
10 * This module is based on the following document:
11 *
12 * Intel 5000X Chipset Memory Controller Hub (MCH) - Datasheet
13 * http://developer.intel.com/design/chipsets/datashts/313070.htm
14 *
15 */
16
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/pci.h>
20 #include <linux/pci_ids.h>
21 #include <linux/slab.h>
22 #include <linux/edac.h>
23 #include <asm/mmzone.h>
24
25 #include "edac_core.h"
26
27 /*
28 * Alter this version for the I5000 module when modifications are made
29 */
30 #define I5000_REVISION " Ver: 2.0.12"
31 #define EDAC_MOD_STR "i5000_edac"
32
33 #define i5000_printk(level, fmt, arg...) \
34 edac_printk(level, "i5000", fmt, ##arg)
35
36 #define i5000_mc_printk(mci, level, fmt, arg...) \
37 edac_mc_chipset_printk(mci, level, "i5000", fmt, ##arg)
38
39 #ifndef PCI_DEVICE_ID_INTEL_FBD_0
40 #define PCI_DEVICE_ID_INTEL_FBD_0 0x25F5
41 #endif
42 #ifndef PCI_DEVICE_ID_INTEL_FBD_1
43 #define PCI_DEVICE_ID_INTEL_FBD_1 0x25F6
44 #endif
45
46 /* Device 16,
47 * Function 0: System Address
48 * Function 1: Memory Branch Map, Control, Errors Register
49 * Function 2: FSB Error Registers
50 *
51 * All 3 functions of Device 16 (0,1,2) share the SAME DID
52 */
53 #define PCI_DEVICE_ID_INTEL_I5000_DEV16 0x25F0
54
55 /* OFFSETS for Function 0 */
56
57 /* OFFSETS for Function 1 */
58 #define AMBASE 0x48
59 #define MAXCH 0x56
60 #define MAXDIMMPERCH 0x57
61 #define TOLM 0x6C
62 #define REDMEMB 0x7C
63 #define RED_ECC_LOCATOR(x) ((x) & 0x3FFFF)
64 #define REC_ECC_LOCATOR_EVEN(x) ((x) & 0x001FF)
65 #define REC_ECC_LOCATOR_ODD(x) ((x) & 0x3FE00)
66 #define MIR0 0x80
67 #define MIR1 0x84
68 #define MIR2 0x88
69 #define AMIR0 0x8C
70 #define AMIR1 0x90
71 #define AMIR2 0x94
72
73 #define FERR_FAT_FBD 0x98
74 #define NERR_FAT_FBD 0x9C
75 #define EXTRACT_FBDCHAN_INDX(x) (((x)>>28) & 0x3)
76 #define FERR_FAT_FBDCHAN 0x30000000
77 #define FERR_FAT_M3ERR 0x00000004
78 #define FERR_FAT_M2ERR 0x00000002
79 #define FERR_FAT_M1ERR 0x00000001
80 #define FERR_FAT_MASK (FERR_FAT_M1ERR | \
81 FERR_FAT_M2ERR | \
82 FERR_FAT_M3ERR)
83
84 #define FERR_NF_FBD 0xA0
85
86 /* Thermal and SPD or BFD errors */
87 #define FERR_NF_M28ERR 0x01000000
88 #define FERR_NF_M27ERR 0x00800000
89 #define FERR_NF_M26ERR 0x00400000
90 #define FERR_NF_M25ERR 0x00200000
91 #define FERR_NF_M24ERR 0x00100000
92 #define FERR_NF_M23ERR 0x00080000
93 #define FERR_NF_M22ERR 0x00040000
94 #define FERR_NF_M21ERR 0x00020000
95
96 /* Correctable errors */
97 #define FERR_NF_M20ERR 0x00010000
98 #define FERR_NF_M19ERR 0x00008000
99 #define FERR_NF_M18ERR 0x00004000
100 #define FERR_NF_M17ERR 0x00002000
101
102 /* Non-Retry or redundant Retry errors */
103 #define FERR_NF_M16ERR 0x00001000
104 #define FERR_NF_M15ERR 0x00000800
105 #define FERR_NF_M14ERR 0x00000400
106 #define FERR_NF_M13ERR 0x00000200
107
108 /* Uncorrectable errors */
109 #define FERR_NF_M12ERR 0x00000100
110 #define FERR_NF_M11ERR 0x00000080
111 #define FERR_NF_M10ERR 0x00000040
112 #define FERR_NF_M9ERR 0x00000020
113 #define FERR_NF_M8ERR 0x00000010
114 #define FERR_NF_M7ERR 0x00000008
115 #define FERR_NF_M6ERR 0x00000004
116 #define FERR_NF_M5ERR 0x00000002
117 #define FERR_NF_M4ERR 0x00000001
118
119 #define FERR_NF_UNCORRECTABLE (FERR_NF_M12ERR | \
120 FERR_NF_M11ERR | \
121 FERR_NF_M10ERR | \
122 FERR_NF_M9ERR | \
123 FERR_NF_M8ERR | \
124 FERR_NF_M7ERR | \
125 FERR_NF_M6ERR | \
126 FERR_NF_M5ERR | \
127 FERR_NF_M4ERR)
128 #define FERR_NF_CORRECTABLE (FERR_NF_M20ERR | \
129 FERR_NF_M19ERR | \
130 FERR_NF_M18ERR | \
131 FERR_NF_M17ERR)
132 #define FERR_NF_DIMM_SPARE (FERR_NF_M27ERR | \
133 FERR_NF_M28ERR)
134 #define FERR_NF_THERMAL (FERR_NF_M26ERR | \
135 FERR_NF_M25ERR | \
136 FERR_NF_M24ERR | \
137 FERR_NF_M23ERR)
138 #define FERR_NF_SPD_PROTOCOL (FERR_NF_M22ERR)
139 #define FERR_NF_NORTH_CRC (FERR_NF_M21ERR)
140 #define FERR_NF_NON_RETRY (FERR_NF_M13ERR | \
141 FERR_NF_M14ERR | \
142 FERR_NF_M15ERR)
143
144 #define NERR_NF_FBD 0xA4
145 #define FERR_NF_MASK (FERR_NF_UNCORRECTABLE | \
146 FERR_NF_CORRECTABLE | \
147 FERR_NF_DIMM_SPARE | \
148 FERR_NF_THERMAL | \
149 FERR_NF_SPD_PROTOCOL | \
150 FERR_NF_NORTH_CRC | \
151 FERR_NF_NON_RETRY)
152
153 #define EMASK_FBD 0xA8
154 #define EMASK_FBD_M28ERR 0x08000000
155 #define EMASK_FBD_M27ERR 0x04000000
156 #define EMASK_FBD_M26ERR 0x02000000
157 #define EMASK_FBD_M25ERR 0x01000000
158 #define EMASK_FBD_M24ERR 0x00800000
159 #define EMASK_FBD_M23ERR 0x00400000
160 #define EMASK_FBD_M22ERR 0x00200000
161 #define EMASK_FBD_M21ERR 0x00100000
162 #define EMASK_FBD_M20ERR 0x00080000
163 #define EMASK_FBD_M19ERR 0x00040000
164 #define EMASK_FBD_M18ERR 0x00020000
165 #define EMASK_FBD_M17ERR 0x00010000
166
167 #define EMASK_FBD_M15ERR 0x00004000
168 #define EMASK_FBD_M14ERR 0x00002000
169 #define EMASK_FBD_M13ERR 0x00001000
170 #define EMASK_FBD_M12ERR 0x00000800
171 #define EMASK_FBD_M11ERR 0x00000400
172 #define EMASK_FBD_M10ERR 0x00000200
173 #define EMASK_FBD_M9ERR 0x00000100
174 #define EMASK_FBD_M8ERR 0x00000080
175 #define EMASK_FBD_M7ERR 0x00000040
176 #define EMASK_FBD_M6ERR 0x00000020
177 #define EMASK_FBD_M5ERR 0x00000010
178 #define EMASK_FBD_M4ERR 0x00000008
179 #define EMASK_FBD_M3ERR 0x00000004
180 #define EMASK_FBD_M2ERR 0x00000002
181 #define EMASK_FBD_M1ERR 0x00000001
182
183 #define ENABLE_EMASK_FBD_FATAL_ERRORS (EMASK_FBD_M1ERR | \
184 EMASK_FBD_M2ERR | \
185 EMASK_FBD_M3ERR)
186
187 #define ENABLE_EMASK_FBD_UNCORRECTABLE (EMASK_FBD_M4ERR | \
188 EMASK_FBD_M5ERR | \
189 EMASK_FBD_M6ERR | \
190 EMASK_FBD_M7ERR | \
191 EMASK_FBD_M8ERR | \
192 EMASK_FBD_M9ERR | \
193 EMASK_FBD_M10ERR | \
194 EMASK_FBD_M11ERR | \
195 EMASK_FBD_M12ERR)
196 #define ENABLE_EMASK_FBD_CORRECTABLE (EMASK_FBD_M17ERR | \
197 EMASK_FBD_M18ERR | \
198 EMASK_FBD_M19ERR | \
199 EMASK_FBD_M20ERR)
200 #define ENABLE_EMASK_FBD_DIMM_SPARE (EMASK_FBD_M27ERR | \
201 EMASK_FBD_M28ERR)
202 #define ENABLE_EMASK_FBD_THERMALS (EMASK_FBD_M26ERR | \
203 EMASK_FBD_M25ERR | \
204 EMASK_FBD_M24ERR | \
205 EMASK_FBD_M23ERR)
206 #define ENABLE_EMASK_FBD_SPD_PROTOCOL (EMASK_FBD_M22ERR)
207 #define ENABLE_EMASK_FBD_NORTH_CRC (EMASK_FBD_M21ERR)
208 #define ENABLE_EMASK_FBD_NON_RETRY (EMASK_FBD_M15ERR | \
209 EMASK_FBD_M14ERR | \
210 EMASK_FBD_M13ERR)
211
212 #define ENABLE_EMASK_ALL (ENABLE_EMASK_FBD_NON_RETRY | \
213 ENABLE_EMASK_FBD_NORTH_CRC | \
214 ENABLE_EMASK_FBD_SPD_PROTOCOL | \
215 ENABLE_EMASK_FBD_THERMALS | \
216 ENABLE_EMASK_FBD_DIMM_SPARE | \
217 ENABLE_EMASK_FBD_FATAL_ERRORS | \
218 ENABLE_EMASK_FBD_CORRECTABLE | \
219 ENABLE_EMASK_FBD_UNCORRECTABLE)
220
221 #define ERR0_FBD 0xAC
222 #define ERR1_FBD 0xB0
223 #define ERR2_FBD 0xB4
224 #define MCERR_FBD 0xB8
225 #define NRECMEMA 0xBE
226 #define NREC_BANK(x) (((x)>>12) & 0x7)
227 #define NREC_RDWR(x) (((x)>>11) & 1)
228 #define NREC_RANK(x) (((x)>>8) & 0x7)
229 #define NRECMEMB 0xC0
230 #define NREC_CAS(x) (((x)>>16) & 0xFFFFFF)
231 #define NREC_RAS(x) ((x) & 0x7FFF)
232 #define NRECFGLOG 0xC4
233 #define NREEECFBDA 0xC8
234 #define NREEECFBDB 0xCC
235 #define NREEECFBDC 0xD0
236 #define NREEECFBDD 0xD4
237 #define NREEECFBDE 0xD8
238 #define REDMEMA 0xDC
239 #define RECMEMA 0xE2
240 #define REC_BANK(x) (((x)>>12) & 0x7)
241 #define REC_RDWR(x) (((x)>>11) & 1)
242 #define REC_RANK(x) (((x)>>8) & 0x7)
243 #define RECMEMB 0xE4
244 #define REC_CAS(x) (((x)>>16) & 0xFFFFFF)
245 #define REC_RAS(x) ((x) & 0x7FFF)
246 #define RECFGLOG 0xE8
247 #define RECFBDA 0xEC
248 #define RECFBDB 0xF0
249 #define RECFBDC 0xF4
250 #define RECFBDD 0xF8
251 #define RECFBDE 0xFC
252
253 /* OFFSETS for Function 2 */
254
255 /*
256 * Device 21,
257 * Function 0: Memory Map Branch 0
258 *
259 * Device 22,
260 * Function 0: Memory Map Branch 1
261 */
262 #define PCI_DEVICE_ID_I5000_BRANCH_0 0x25F5
263 #define PCI_DEVICE_ID_I5000_BRANCH_1 0x25F6
264
265 #define AMB_PRESENT_0 0x64
266 #define AMB_PRESENT_1 0x66
267 #define MTR0 0x80
268 #define MTR1 0x84
269 #define MTR2 0x88
270 #define MTR3 0x8C
271
272 #define NUM_MTRS 4
273 #define CHANNELS_PER_BRANCH 2
274 #define MAX_BRANCHES 2
275
276 /* Defines to extract the vaious fields from the
277 * MTRx - Memory Technology Registers
278 */
279 #define MTR_DIMMS_PRESENT(mtr) ((mtr) & (0x1 << 8))
280 #define MTR_DRAM_WIDTH(mtr) ((((mtr) >> 6) & 0x1) ? 8 : 4)
281 #define MTR_DRAM_BANKS(mtr) ((((mtr) >> 5) & 0x1) ? 8 : 4)
282 #define MTR_DRAM_BANKS_ADDR_BITS(mtr) ((MTR_DRAM_BANKS(mtr) == 8) ? 3 : 2)
283 #define MTR_DIMM_RANK(mtr) (((mtr) >> 4) & 0x1)
284 #define MTR_DIMM_RANK_ADDR_BITS(mtr) (MTR_DIMM_RANK(mtr) ? 2 : 1)
285 #define MTR_DIMM_ROWS(mtr) (((mtr) >> 2) & 0x3)
286 #define MTR_DIMM_ROWS_ADDR_BITS(mtr) (MTR_DIMM_ROWS(mtr) + 13)
287 #define MTR_DIMM_COLS(mtr) ((mtr) & 0x3)
288 #define MTR_DIMM_COLS_ADDR_BITS(mtr) (MTR_DIMM_COLS(mtr) + 10)
289
290 #ifdef CONFIG_EDAC_DEBUG
291 static char *numrow_toString[] = {
292 "8,192 - 13 rows",
293 "16,384 - 14 rows",
294 "32,768 - 15 rows",
295 "reserved"
296 };
297
298 static char *numcol_toString[] = {
299 "1,024 - 10 columns",
300 "2,048 - 11 columns",
301 "4,096 - 12 columns",
302 "reserved"
303 };
304 #endif
305
306 /* enables the report of miscellaneous messages as CE errors - default off */
307 static int misc_messages;
308
309 /* Enumeration of supported devices */
310 enum i5000_chips {
311 I5000P = 0,
312 I5000V = 1, /* future */
313 I5000X = 2 /* future */
314 };
315
316 /* Device name and register DID (Device ID) */
317 struct i5000_dev_info {
318 const char *ctl_name; /* name for this device */
319 u16 fsb_mapping_errors; /* DID for the branchmap,control */
320 };
321
322 /* Table of devices attributes supported by this driver */
323 static const struct i5000_dev_info i5000_devs[] = {
324 [I5000P] = {
325 .ctl_name = "I5000",
326 .fsb_mapping_errors = PCI_DEVICE_ID_INTEL_I5000_DEV16,
327 },
328 };
329
330 struct i5000_dimm_info {
331 int megabytes; /* size, 0 means not present */
332 int dual_rank;
333 };
334
335 #define MAX_CHANNELS 6 /* max possible channels */
336 #define MAX_CSROWS (8*2) /* max possible csrows per channel */
337
338 /* driver private data structure */
339 struct i5000_pvt {
340 struct pci_dev *system_address; /* 16.0 */
341 struct pci_dev *branchmap_werrors; /* 16.1 */
342 struct pci_dev *fsb_error_regs; /* 16.2 */
343 struct pci_dev *branch_0; /* 21.0 */
344 struct pci_dev *branch_1; /* 22.0 */
345
346 u16 tolm; /* top of low memory */
347 u64 ambase; /* AMB BAR */
348
349 u16 mir0, mir1, mir2;
350
351 u16 b0_mtr[NUM_MTRS]; /* Memory Technlogy Reg */
352 u16 b0_ambpresent0; /* Branch 0, Channel 0 */
353 u16 b0_ambpresent1; /* Brnach 0, Channel 1 */
354
355 u16 b1_mtr[NUM_MTRS]; /* Memory Technlogy Reg */
356 u16 b1_ambpresent0; /* Branch 1, Channel 8 */
357 u16 b1_ambpresent1; /* Branch 1, Channel 1 */
358
359 /* DIMM information matrix, allocating architecture maximums */
360 struct i5000_dimm_info dimm_info[MAX_CSROWS][MAX_CHANNELS];
361
362 /* Actual values for this controller */
363 int maxch; /* Max channels */
364 int maxdimmperch; /* Max DIMMs per channel */
365 };
366
367 /* I5000 MCH error information retrieved from Hardware */
368 struct i5000_error_info {
369
370 /* These registers are always read from the MC */
371 u32 ferr_fat_fbd; /* First Errors Fatal */
372 u32 nerr_fat_fbd; /* Next Errors Fatal */
373 u32 ferr_nf_fbd; /* First Errors Non-Fatal */
374 u32 nerr_nf_fbd; /* Next Errors Non-Fatal */
375
376 /* These registers are input ONLY if there was a Recoverable Error */
377 u32 redmemb; /* Recoverable Mem Data Error log B */
378 u16 recmema; /* Recoverable Mem Error log A */
379 u32 recmemb; /* Recoverable Mem Error log B */
380
381 /* These registers are input ONLY if there was a
382 * Non-Recoverable Error */
383 u16 nrecmema; /* Non-Recoverable Mem log A */
384 u16 nrecmemb; /* Non-Recoverable Mem log B */
385
386 };
387
388 static struct edac_pci_ctl_info *i5000_pci;
389
390 /*
391 * i5000_get_error_info Retrieve the hardware error information from
392 * the hardware and cache it in the 'info'
393 * structure
394 */
395 static void i5000_get_error_info(struct mem_ctl_info *mci,
396 struct i5000_error_info *info)
397 {
398 struct i5000_pvt *pvt;
399 u32 value;
400
401 pvt = mci->pvt_info;
402
403 /* read in the 1st FATAL error register */
404 pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
405
406 /* Mask only the bits that the doc says are valid
407 */
408 value &= (FERR_FAT_FBDCHAN | FERR_FAT_MASK);
409
410 /* If there is an error, then read in the */
411 /* NEXT FATAL error register and the Memory Error Log Register A */
412 if (value & FERR_FAT_MASK) {
413 info->ferr_fat_fbd = value;
414
415 /* harvest the various error data we need */
416 pci_read_config_dword(pvt->branchmap_werrors,
417 NERR_FAT_FBD, &info->nerr_fat_fbd);
418 pci_read_config_word(pvt->branchmap_werrors,
419 NRECMEMA, &info->nrecmema);
420 pci_read_config_word(pvt->branchmap_werrors,
421 NRECMEMB, &info->nrecmemb);
422
423 /* Clear the error bits, by writing them back */
424 pci_write_config_dword(pvt->branchmap_werrors,
425 FERR_FAT_FBD, value);
426 } else {
427 info->ferr_fat_fbd = 0;
428 info->nerr_fat_fbd = 0;
429 info->nrecmema = 0;
430 info->nrecmemb = 0;
431 }
432
433 /* read in the 1st NON-FATAL error register */
434 pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
435
436 /* If there is an error, then read in the 1st NON-FATAL error
437 * register as well */
438 if (value & FERR_NF_MASK) {
439 info->ferr_nf_fbd = value;
440
441 /* harvest the various error data we need */
442 pci_read_config_dword(pvt->branchmap_werrors,
443 NERR_NF_FBD, &info->nerr_nf_fbd);
444 pci_read_config_word(pvt->branchmap_werrors,
445 RECMEMA, &info->recmema);
446 pci_read_config_dword(pvt->branchmap_werrors,
447 RECMEMB, &info->recmemb);
448 pci_read_config_dword(pvt->branchmap_werrors,
449 REDMEMB, &info->redmemb);
450
451 /* Clear the error bits, by writing them back */
452 pci_write_config_dword(pvt->branchmap_werrors,
453 FERR_NF_FBD, value);
454 } else {
455 info->ferr_nf_fbd = 0;
456 info->nerr_nf_fbd = 0;
457 info->recmema = 0;
458 info->recmemb = 0;
459 info->redmemb = 0;
460 }
461 }
462
463 /*
464 * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
465 * struct i5000_error_info *info,
466 * int handle_errors);
467 *
468 * handle the Intel FATAL errors, if any
469 */
470 static void i5000_process_fatal_error_info(struct mem_ctl_info *mci,
471 struct i5000_error_info *info,
472 int handle_errors)
473 {
474 char msg[EDAC_MC_LABEL_LEN + 1 + 160];
475 char *specific = NULL;
476 u32 allErrors;
477 int channel;
478 int bank;
479 int rank;
480 int rdwr;
481 int ras, cas;
482
483 /* mask off the Error bits that are possible */
484 allErrors = (info->ferr_fat_fbd & FERR_FAT_MASK);
485 if (!allErrors)
486 return; /* if no error, return now */
487
488 channel = EXTRACT_FBDCHAN_INDX(info->ferr_fat_fbd);
489
490 /* Use the NON-Recoverable macros to extract data */
491 bank = NREC_BANK(info->nrecmema);
492 rank = NREC_RANK(info->nrecmema);
493 rdwr = NREC_RDWR(info->nrecmema);
494 ras = NREC_RAS(info->nrecmemb);
495 cas = NREC_CAS(info->nrecmemb);
496
497 debugf0("\t\tCSROW= %d Channel= %d "
498 "(DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
499 rank, channel, bank,
500 rdwr ? "Write" : "Read", ras, cas);
501
502 /* Only 1 bit will be on */
503 switch (allErrors) {
504 case FERR_FAT_M1ERR:
505 specific = "Alert on non-redundant retry or fast "
506 "reset timeout";
507 break;
508 case FERR_FAT_M2ERR:
509 specific = "Northbound CRC error on non-redundant "
510 "retry";
511 break;
512 case FERR_FAT_M3ERR:
513 {
514 static int done;
515
516 /*
517 * This error is generated to inform that the intelligent
518 * throttling is disabled and the temperature passed the
519 * specified middle point. Since this is something the BIOS
520 * should take care of, we'll warn only once to avoid
521 * worthlessly flooding the log.
522 */
523 if (done)
524 return;
525 done++;
526
527 specific = ">Tmid Thermal event with intelligent "
528 "throttling disabled";
529 }
530 break;
531 }
532
533 /* Form out message */
534 snprintf(msg, sizeof(msg),
535 "Bank=%d RAS=%d CAS=%d FATAL Err=0x%x (%s)",
536 bank, ras, cas, allErrors, specific);
537
538 /* Call the helper to output message */
539 edac_mc_handle_error(HW_EVENT_ERR_FATAL, mci, 0, 0, 0,
540 channel >> 1, channel & 1, rank,
541 rdwr ? "Write error" : "Read error",
542 msg, NULL);
543 }
544
545 /*
546 * i5000_process_fatal_error_info(struct mem_ctl_info *mci,
547 * struct i5000_error_info *info,
548 * int handle_errors);
549 *
550 * handle the Intel NON-FATAL errors, if any
551 */
552 static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
553 struct i5000_error_info *info,
554 int handle_errors)
555 {
556 char msg[EDAC_MC_LABEL_LEN + 1 + 170];
557 char *specific = NULL;
558 u32 allErrors;
559 u32 ue_errors;
560 u32 ce_errors;
561 u32 misc_errors;
562 int branch;
563 int channel;
564 int bank;
565 int rank;
566 int rdwr;
567 int ras, cas;
568
569 /* mask off the Error bits that are possible */
570 allErrors = (info->ferr_nf_fbd & FERR_NF_MASK);
571 if (!allErrors)
572 return; /* if no error, return now */
573
574 /* ONLY ONE of the possible error bits will be set, as per the docs */
575 ue_errors = allErrors & FERR_NF_UNCORRECTABLE;
576 if (ue_errors) {
577 debugf0("\tUncorrected bits= 0x%x\n", ue_errors);
578
579 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
580
581 /*
582 * According with i5000 datasheet, bit 28 has no significance
583 * for errors M4Err-M12Err and M17Err-M21Err, on FERR_NF_FBD
584 */
585 channel = branch & 2;
586
587 bank = NREC_BANK(info->nrecmema);
588 rank = NREC_RANK(info->nrecmema);
589 rdwr = NREC_RDWR(info->nrecmema);
590 ras = NREC_RAS(info->nrecmemb);
591 cas = NREC_CAS(info->nrecmemb);
592
593 debugf0
594 ("\t\tCSROW= %d Channels= %d,%d (Branch= %d "
595 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
596 rank, channel, channel + 1, branch >> 1, bank,
597 rdwr ? "Write" : "Read", ras, cas);
598
599 switch (ue_errors) {
600 case FERR_NF_M12ERR:
601 specific = "Non-Aliased Uncorrectable Patrol Data ECC";
602 break;
603 case FERR_NF_M11ERR:
604 specific = "Non-Aliased Uncorrectable Spare-Copy "
605 "Data ECC";
606 break;
607 case FERR_NF_M10ERR:
608 specific = "Non-Aliased Uncorrectable Mirrored Demand "
609 "Data ECC";
610 break;
611 case FERR_NF_M9ERR:
612 specific = "Non-Aliased Uncorrectable Non-Mirrored "
613 "Demand Data ECC";
614 break;
615 case FERR_NF_M8ERR:
616 specific = "Aliased Uncorrectable Patrol Data ECC";
617 break;
618 case FERR_NF_M7ERR:
619 specific = "Aliased Uncorrectable Spare-Copy Data ECC";
620 break;
621 case FERR_NF_M6ERR:
622 specific = "Aliased Uncorrectable Mirrored Demand "
623 "Data ECC";
624 break;
625 case FERR_NF_M5ERR:
626 specific = "Aliased Uncorrectable Non-Mirrored Demand "
627 "Data ECC";
628 break;
629 case FERR_NF_M4ERR:
630 specific = "Uncorrectable Data ECC on Replay";
631 break;
632 }
633
634 /* Form out message */
635 snprintf(msg, sizeof(msg),
636 "Rank=%d Bank=%d RAS=%d CAS=%d, UE Err=0x%x (%s)",
637 rank, bank, ras, cas, ue_errors, specific);
638
639 /* Call the helper to output message */
640 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0,
641 channel >> 1, -1, rank,
642 rdwr ? "Write error" : "Read error",
643 msg, NULL);
644 }
645
646 /* Check correctable errors */
647 ce_errors = allErrors & FERR_NF_CORRECTABLE;
648 if (ce_errors) {
649 debugf0("\tCorrected bits= 0x%x\n", ce_errors);
650
651 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
652
653 channel = 0;
654 if (REC_ECC_LOCATOR_ODD(info->redmemb))
655 channel = 1;
656
657 /* Convert channel to be based from zero, instead of
658 * from branch base of 0 */
659 channel += branch;
660
661 bank = REC_BANK(info->recmema);
662 rank = REC_RANK(info->recmema);
663 rdwr = REC_RDWR(info->recmema);
664 ras = REC_RAS(info->recmemb);
665 cas = REC_CAS(info->recmemb);
666
667 debugf0("\t\tCSROW= %d Channel= %d (Branch %d "
668 "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
669 rank, channel, branch >> 1, bank,
670 rdwr ? "Write" : "Read", ras, cas);
671
672 switch (ce_errors) {
673 case FERR_NF_M17ERR:
674 specific = "Correctable Non-Mirrored Demand Data ECC";
675 break;
676 case FERR_NF_M18ERR:
677 specific = "Correctable Mirrored Demand Data ECC";
678 break;
679 case FERR_NF_M19ERR:
680 specific = "Correctable Spare-Copy Data ECC";
681 break;
682 case FERR_NF_M20ERR:
683 specific = "Correctable Patrol Data ECC";
684 break;
685 }
686
687 /* Form out message */
688 snprintf(msg, sizeof(msg),
689 "Rank=%d Bank=%d RDWR=%s RAS=%d "
690 "CAS=%d, CE Err=0x%x (%s))", branch >> 1, bank,
691 rdwr ? "Write" : "Read", ras, cas, ce_errors,
692 specific);
693
694 /* Call the helper to output message */
695 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 0, 0, 0,
696 channel >> 1, channel % 2, rank,
697 rdwr ? "Write error" : "Read error",
698 msg, NULL);
699 }
700
701 if (!misc_messages)
702 return;
703
704 misc_errors = allErrors & (FERR_NF_NON_RETRY | FERR_NF_NORTH_CRC |
705 FERR_NF_SPD_PROTOCOL | FERR_NF_DIMM_SPARE);
706 if (misc_errors) {
707 switch (misc_errors) {
708 case FERR_NF_M13ERR:
709 specific = "Non-Retry or Redundant Retry FBD Memory "
710 "Alert or Redundant Fast Reset Timeout";
711 break;
712 case FERR_NF_M14ERR:
713 specific = "Non-Retry or Redundant Retry FBD "
714 "Configuration Alert";
715 break;
716 case FERR_NF_M15ERR:
717 specific = "Non-Retry or Redundant Retry FBD "
718 "Northbound CRC error on read data";
719 break;
720 case FERR_NF_M21ERR:
721 specific = "FBD Northbound CRC error on "
722 "FBD Sync Status";
723 break;
724 case FERR_NF_M22ERR:
725 specific = "SPD protocol error";
726 break;
727 case FERR_NF_M27ERR:
728 specific = "DIMM-spare copy started";
729 break;
730 case FERR_NF_M28ERR:
731 specific = "DIMM-spare copy completed";
732 break;
733 }
734 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
735
736 /* Form out message */
737 snprintf(msg, sizeof(msg),
738 "Err=%#x (%s)", misc_errors, specific);
739
740 /* Call the helper to output message */
741 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 0, 0, 0,
742 branch >> 1, -1, -1,
743 "Misc error", msg, NULL);
744 }
745 }
746
747 /*
748 * i5000_process_error_info Process the error info that is
749 * in the 'info' structure, previously retrieved from hardware
750 */
751 static void i5000_process_error_info(struct mem_ctl_info *mci,
752 struct i5000_error_info *info,
753 int handle_errors)
754 {
755 /* First handle any fatal errors that occurred */
756 i5000_process_fatal_error_info(mci, info, handle_errors);
757
758 /* now handle any non-fatal errors that occurred */
759 i5000_process_nonfatal_error_info(mci, info, handle_errors);
760 }
761
762 /*
763 * i5000_clear_error Retrieve any error from the hardware
764 * but do NOT process that error.
765 * Used for 'clearing' out of previous errors
766 * Called by the Core module.
767 */
768 static void i5000_clear_error(struct mem_ctl_info *mci)
769 {
770 struct i5000_error_info info;
771
772 i5000_get_error_info(mci, &info);
773 }
774
775 /*
776 * i5000_check_error Retrieve and process errors reported by the
777 * hardware. Called by the Core module.
778 */
779 static void i5000_check_error(struct mem_ctl_info *mci)
780 {
781 struct i5000_error_info info;
782 debugf4("MC%d\n", mci->mc_idx);
783 i5000_get_error_info(mci, &info);
784 i5000_process_error_info(mci, &info, 1);
785 }
786
787 /*
788 * i5000_get_devices Find and perform 'get' operation on the MCH's
789 * device/functions we want to reference for this driver
790 *
791 * Need to 'get' device 16 func 1 and func 2
792 */
793 static int i5000_get_devices(struct mem_ctl_info *mci, int dev_idx)
794 {
795 //const struct i5000_dev_info *i5000_dev = &i5000_devs[dev_idx];
796 struct i5000_pvt *pvt;
797 struct pci_dev *pdev;
798
799 pvt = mci->pvt_info;
800
801 /* Attempt to 'get' the MCH register we want */
802 pdev = NULL;
803 while (1) {
804 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
805 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
806
807 /* End of list, leave */
808 if (pdev == NULL) {
809 i5000_printk(KERN_ERR,
810 "'system address,Process Bus' "
811 "device not found:"
812 "vendor 0x%x device 0x%x FUNC 1 "
813 "(broken BIOS?)\n",
814 PCI_VENDOR_ID_INTEL,
815 PCI_DEVICE_ID_INTEL_I5000_DEV16);
816
817 return 1;
818 }
819
820 /* Scan for device 16 func 1 */
821 if (PCI_FUNC(pdev->devfn) == 1)
822 break;
823 }
824
825 pvt->branchmap_werrors = pdev;
826
827 /* Attempt to 'get' the MCH register we want */
828 pdev = NULL;
829 while (1) {
830 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
831 PCI_DEVICE_ID_INTEL_I5000_DEV16, pdev);
832
833 if (pdev == NULL) {
834 i5000_printk(KERN_ERR,
835 "MC: 'branchmap,control,errors' "
836 "device not found:"
837 "vendor 0x%x device 0x%x Func 2 "
838 "(broken BIOS?)\n",
839 PCI_VENDOR_ID_INTEL,
840 PCI_DEVICE_ID_INTEL_I5000_DEV16);
841
842 pci_dev_put(pvt->branchmap_werrors);
843 return 1;
844 }
845
846 /* Scan for device 16 func 1 */
847 if (PCI_FUNC(pdev->devfn) == 2)
848 break;
849 }
850
851 pvt->fsb_error_regs = pdev;
852
853 debugf1("System Address, processor bus- PCI Bus ID: %s %x:%x\n",
854 pci_name(pvt->system_address),
855 pvt->system_address->vendor, pvt->system_address->device);
856 debugf1("Branchmap, control and errors - PCI Bus ID: %s %x:%x\n",
857 pci_name(pvt->branchmap_werrors),
858 pvt->branchmap_werrors->vendor, pvt->branchmap_werrors->device);
859 debugf1("FSB Error Regs - PCI Bus ID: %s %x:%x\n",
860 pci_name(pvt->fsb_error_regs),
861 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
862
863 pdev = NULL;
864 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
865 PCI_DEVICE_ID_I5000_BRANCH_0, pdev);
866
867 if (pdev == NULL) {
868 i5000_printk(KERN_ERR,
869 "MC: 'BRANCH 0' device not found:"
870 "vendor 0x%x device 0x%x Func 0 (broken BIOS?)\n",
871 PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_I5000_BRANCH_0);
872
873 pci_dev_put(pvt->branchmap_werrors);
874 pci_dev_put(pvt->fsb_error_regs);
875 return 1;
876 }
877
878 pvt->branch_0 = pdev;
879
880 /* If this device claims to have more than 2 channels then
881 * fetch Branch 1's information
882 */
883 if (pvt->maxch >= CHANNELS_PER_BRANCH) {
884 pdev = NULL;
885 pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
886 PCI_DEVICE_ID_I5000_BRANCH_1, pdev);
887
888 if (pdev == NULL) {
889 i5000_printk(KERN_ERR,
890 "MC: 'BRANCH 1' device not found:"
891 "vendor 0x%x device 0x%x Func 0 "
892 "(broken BIOS?)\n",
893 PCI_VENDOR_ID_INTEL,
894 PCI_DEVICE_ID_I5000_BRANCH_1);
895
896 pci_dev_put(pvt->branchmap_werrors);
897 pci_dev_put(pvt->fsb_error_regs);
898 pci_dev_put(pvt->branch_0);
899 return 1;
900 }
901
902 pvt->branch_1 = pdev;
903 }
904
905 return 0;
906 }
907
908 /*
909 * i5000_put_devices 'put' all the devices that we have
910 * reserved via 'get'
911 */
912 static void i5000_put_devices(struct mem_ctl_info *mci)
913 {
914 struct i5000_pvt *pvt;
915
916 pvt = mci->pvt_info;
917
918 pci_dev_put(pvt->branchmap_werrors); /* FUNC 1 */
919 pci_dev_put(pvt->fsb_error_regs); /* FUNC 2 */
920 pci_dev_put(pvt->branch_0); /* DEV 21 */
921
922 /* Only if more than 2 channels do we release the second branch */
923 if (pvt->maxch >= CHANNELS_PER_BRANCH)
924 pci_dev_put(pvt->branch_1); /* DEV 22 */
925 }
926
927 /*
928 * determine_amb_resent
929 *
930 * the information is contained in NUM_MTRS different registers
931 * determineing which of the NUM_MTRS requires knowing
932 * which channel is in question
933 *
934 * 2 branches, each with 2 channels
935 * b0_ambpresent0 for channel '0'
936 * b0_ambpresent1 for channel '1'
937 * b1_ambpresent0 for channel '2'
938 * b1_ambpresent1 for channel '3'
939 */
940 static int determine_amb_present_reg(struct i5000_pvt *pvt, int channel)
941 {
942 int amb_present;
943
944 if (channel < CHANNELS_PER_BRANCH) {
945 if (channel & 0x1)
946 amb_present = pvt->b0_ambpresent1;
947 else
948 amb_present = pvt->b0_ambpresent0;
949 } else {
950 if (channel & 0x1)
951 amb_present = pvt->b1_ambpresent1;
952 else
953 amb_present = pvt->b1_ambpresent0;
954 }
955
956 return amb_present;
957 }
958
959 /*
960 * determine_mtr(pvt, csrow, channel)
961 *
962 * return the proper MTR register as determine by the csrow and channel desired
963 */
964 static int determine_mtr(struct i5000_pvt *pvt, int slot, int channel)
965 {
966 int mtr;
967
968 if (channel < CHANNELS_PER_BRANCH)
969 mtr = pvt->b0_mtr[slot];
970 else
971 mtr = pvt->b1_mtr[slot];
972
973 return mtr;
974 }
975
976 /*
977 */
978 static void decode_mtr(int slot_row, u16 mtr)
979 {
980 int ans;
981
982 ans = MTR_DIMMS_PRESENT(mtr);
983
984 debugf2("\tMTR%d=0x%x: DIMMs are %s\n", slot_row, mtr,
985 ans ? "Present" : "NOT Present");
986 if (!ans)
987 return;
988
989 debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
990 debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
991 debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANK(mtr) ? "double" : "single");
992 debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);
993 debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
994 }
995
996 static void handle_channel(struct i5000_pvt *pvt, int slot, int channel,
997 struct i5000_dimm_info *dinfo)
998 {
999 int mtr;
1000 int amb_present_reg;
1001 int addrBits;
1002
1003 mtr = determine_mtr(pvt, slot, channel);
1004 if (MTR_DIMMS_PRESENT(mtr)) {
1005 amb_present_reg = determine_amb_present_reg(pvt, channel);
1006
1007 /* Determine if there is a DIMM present in this DIMM slot */
1008 if (amb_present_reg) {
1009 dinfo->dual_rank = MTR_DIMM_RANK(mtr);
1010
1011 /* Start with the number of bits for a Bank
1012 * on the DRAM */
1013 addrBits = MTR_DRAM_BANKS_ADDR_BITS(mtr);
1014 /* Add the number of ROW bits */
1015 addrBits += MTR_DIMM_ROWS_ADDR_BITS(mtr);
1016 /* add the number of COLUMN bits */
1017 addrBits += MTR_DIMM_COLS_ADDR_BITS(mtr);
1018
1019 addrBits += 6; /* add 64 bits per DIMM */
1020 addrBits -= 20; /* divide by 2^^20 */
1021 addrBits -= 3; /* 8 bits per bytes */
1022
1023 dinfo->megabytes = 1 << addrBits;
1024 }
1025 }
1026 }
1027
1028 /*
1029 * calculate_dimm_size
1030 *
1031 * also will output a DIMM matrix map, if debug is enabled, for viewing
1032 * how the DIMMs are populated
1033 */
1034 static void calculate_dimm_size(struct i5000_pvt *pvt)
1035 {
1036 struct i5000_dimm_info *dinfo;
1037 int slot, channel, branch;
1038 char *p, *mem_buffer;
1039 int space, n;
1040
1041 /* ================= Generate some debug output ================= */
1042 space = PAGE_SIZE;
1043 mem_buffer = p = kmalloc(space, GFP_KERNEL);
1044 if (p == NULL) {
1045 i5000_printk(KERN_ERR, "MC: %s:%s() kmalloc() failed\n",
1046 __FILE__, __func__);
1047 return;
1048 }
1049
1050 /* Scan all the actual slots
1051 * and calculate the information for each DIMM
1052 * Start with the highest slot first, to display it first
1053 * and work toward the 0th slot
1054 */
1055 for (slot = pvt->maxdimmperch - 1; slot >= 0; slot--) {
1056
1057 /* on an odd slot, first output a 'boundary' marker,
1058 * then reset the message buffer */
1059 if (slot & 0x1) {
1060 n = snprintf(p, space, "--------------------------"
1061 "--------------------------------");
1062 p += n;
1063 space -= n;
1064 debugf2("%s\n", mem_buffer);
1065 p = mem_buffer;
1066 space = PAGE_SIZE;
1067 }
1068 n = snprintf(p, space, "slot %2d ", slot);
1069 p += n;
1070 space -= n;
1071
1072 for (channel = 0; channel < pvt->maxch; channel++) {
1073 dinfo = &pvt->dimm_info[slot][channel];
1074 handle_channel(pvt, slot, channel, dinfo);
1075 if (dinfo->megabytes)
1076 n = snprintf(p, space, "%4d MB %dR| ",
1077 dinfo->megabytes, dinfo->dual_rank + 1);
1078 else
1079 n = snprintf(p, space, "%4d MB | ", 0);
1080 p += n;
1081 space -= n;
1082 }
1083 p += n;
1084 space -= n;
1085 debugf2("%s\n", mem_buffer);
1086 p = mem_buffer;
1087 space = PAGE_SIZE;
1088 }
1089
1090 /* Output the last bottom 'boundary' marker */
1091 n = snprintf(p, space, "--------------------------"
1092 "--------------------------------");
1093 p += n;
1094 space -= n;
1095 debugf2("%s\n", mem_buffer);
1096 p = mem_buffer;
1097 space = PAGE_SIZE;
1098
1099 /* now output the 'channel' labels */
1100 n = snprintf(p, space, " ");
1101 p += n;
1102 space -= n;
1103 for (channel = 0; channel < pvt->maxch; channel++) {
1104 n = snprintf(p, space, "channel %d | ", channel);
1105 p += n;
1106 space -= n;
1107 }
1108 debugf2("%s\n", mem_buffer);
1109 p = mem_buffer;
1110 space = PAGE_SIZE;
1111
1112 n = snprintf(p, space, " ");
1113 p += n;
1114 for (branch = 0; branch < MAX_BRANCHES; branch++) {
1115 n = snprintf(p, space, " branch %d | ", branch);
1116 p += n;
1117 space -= n;
1118 }
1119
1120 /* output the last message and free buffer */
1121 debugf2("%s\n", mem_buffer);
1122 kfree(mem_buffer);
1123 }
1124
1125 /*
1126 * i5000_get_mc_regs read in the necessary registers and
1127 * cache locally
1128 *
1129 * Fills in the private data members
1130 */
1131 static void i5000_get_mc_regs(struct mem_ctl_info *mci)
1132 {
1133 struct i5000_pvt *pvt;
1134 u32 actual_tolm;
1135 u16 limit;
1136 int slot_row;
1137 int maxch;
1138 int maxdimmperch;
1139 int way0, way1;
1140
1141 pvt = mci->pvt_info;
1142
1143 pci_read_config_dword(pvt->system_address, AMBASE,
1144 (u32 *) & pvt->ambase);
1145 pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
1146 ((u32 *) & pvt->ambase) + sizeof(u32));
1147
1148 maxdimmperch = pvt->maxdimmperch;
1149 maxch = pvt->maxch;
1150
1151 debugf2("AMBASE= 0x%lx MAXCH= %d MAX-DIMM-Per-CH= %d\n",
1152 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
1153
1154 /* Get the Branch Map regs */
1155 pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
1156 pvt->tolm >>= 12;
1157 debugf2("\nTOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm,
1158 pvt->tolm);
1159
1160 actual_tolm = pvt->tolm << 28;
1161 debugf2("Actual TOLM byte addr=%u (0x%x)\n", actual_tolm, actual_tolm);
1162
1163 pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
1164 pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
1165 pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir2);
1166
1167 /* Get the MIR[0-2] regs */
1168 limit = (pvt->mir0 >> 4) & 0x0FFF;
1169 way0 = pvt->mir0 & 0x1;
1170 way1 = pvt->mir0 & 0x2;
1171 debugf2("MIR0: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0);
1172 limit = (pvt->mir1 >> 4) & 0x0FFF;
1173 way0 = pvt->mir1 & 0x1;
1174 way1 = pvt->mir1 & 0x2;
1175 debugf2("MIR1: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0);
1176 limit = (pvt->mir2 >> 4) & 0x0FFF;
1177 way0 = pvt->mir2 & 0x1;
1178 way1 = pvt->mir2 & 0x2;
1179 debugf2("MIR2: limit= 0x%x WAY1= %u WAY0= %x\n", limit, way1, way0);
1180
1181 /* Get the MTR[0-3] regs */
1182 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1183 int where = MTR0 + (slot_row * sizeof(u32));
1184
1185 pci_read_config_word(pvt->branch_0, where,
1186 &pvt->b0_mtr[slot_row]);
1187
1188 debugf2("MTR%d where=0x%x B0 value=0x%x\n", slot_row, where,
1189 pvt->b0_mtr[slot_row]);
1190
1191 if (pvt->maxch >= CHANNELS_PER_BRANCH) {
1192 pci_read_config_word(pvt->branch_1, where,
1193 &pvt->b1_mtr[slot_row]);
1194 debugf2("MTR%d where=0x%x B1 value=0x%x\n", slot_row,
1195 where, pvt->b1_mtr[slot_row]);
1196 } else {
1197 pvt->b1_mtr[slot_row] = 0;
1198 }
1199 }
1200
1201 /* Read and dump branch 0's MTRs */
1202 debugf2("\nMemory Technology Registers:\n");
1203 debugf2(" Branch 0:\n");
1204 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1205 decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
1206 }
1207 pci_read_config_word(pvt->branch_0, AMB_PRESENT_0,
1208 &pvt->b0_ambpresent0);
1209 debugf2("\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
1210 pci_read_config_word(pvt->branch_0, AMB_PRESENT_1,
1211 &pvt->b0_ambpresent1);
1212 debugf2("\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
1213
1214 /* Only if we have 2 branchs (4 channels) */
1215 if (pvt->maxch < CHANNELS_PER_BRANCH) {
1216 pvt->b1_ambpresent0 = 0;
1217 pvt->b1_ambpresent1 = 0;
1218 } else {
1219 /* Read and dump branch 1's MTRs */
1220 debugf2(" Branch 1:\n");
1221 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
1222 decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
1223 }
1224 pci_read_config_word(pvt->branch_1, AMB_PRESENT_0,
1225 &pvt->b1_ambpresent0);
1226 debugf2("\t\tAMB-Branch 1-present0 0x%x:\n",
1227 pvt->b1_ambpresent0);
1228 pci_read_config_word(pvt->branch_1, AMB_PRESENT_1,
1229 &pvt->b1_ambpresent1);
1230 debugf2("\t\tAMB-Branch 1-present1 0x%x:\n",
1231 pvt->b1_ambpresent1);
1232 }
1233
1234 /* Go and determine the size of each DIMM and place in an
1235 * orderly matrix */
1236 calculate_dimm_size(pvt);
1237 }
1238
1239 /*
1240 * i5000_init_csrows Initialize the 'csrows' table within
1241 * the mci control structure with the
1242 * addressing of memory.
1243 *
1244 * return:
1245 * 0 success
1246 * 1 no actual memory found on this MC
1247 */
1248 static int i5000_init_csrows(struct mem_ctl_info *mci)
1249 {
1250 struct i5000_pvt *pvt;
1251 struct dimm_info *dimm;
1252 int empty, channel_count;
1253 int max_csrows;
1254 int mtr;
1255 int csrow_megs;
1256 int channel;
1257 int slot;
1258
1259 pvt = mci->pvt_info;
1260
1261 channel_count = pvt->maxch;
1262 max_csrows = pvt->maxdimmperch * 2;
1263
1264 empty = 1; /* Assume NO memory */
1265
1266 /*
1267 * FIXME: The memory layout used to map slot/channel into the
1268 * real memory architecture is weird: branch+slot are "csrows"
1269 * and channel is channel. That required an extra array (dimm_info)
1270 * to map the dimms. A good cleanup would be to remove this array,
1271 * and do a loop here with branch, channel, slot
1272 */
1273 for (slot = 0; slot < max_csrows; slot++) {
1274 for (channel = 0; channel < pvt->maxch; channel++) {
1275
1276 mtr = determine_mtr(pvt, slot, channel);
1277
1278 if (!MTR_DIMMS_PRESENT(mtr))
1279 continue;
1280
1281 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
1282 channel / MAX_BRANCHES,
1283 channel % MAX_BRANCHES, slot);
1284
1285 csrow_megs = pvt->dimm_info[slot][channel].megabytes;
1286 dimm->grain = 8;
1287
1288 /* Assume DDR2 for now */
1289 dimm->mtype = MEM_FB_DDR2;
1290
1291 /* ask what device type on this row */
1292 if (MTR_DRAM_WIDTH(mtr))
1293 dimm->dtype = DEV_X8;
1294 else
1295 dimm->dtype = DEV_X4;
1296
1297 dimm->edac_mode = EDAC_S8ECD8ED;
1298 dimm->nr_pages = csrow_megs << 8;
1299 }
1300
1301 empty = 0;
1302 }
1303
1304 return empty;
1305 }
1306
1307 /*
1308 * i5000_enable_error_reporting
1309 * Turn on the memory reporting features of the hardware
1310 */
1311 static void i5000_enable_error_reporting(struct mem_ctl_info *mci)
1312 {
1313 struct i5000_pvt *pvt;
1314 u32 fbd_error_mask;
1315
1316 pvt = mci->pvt_info;
1317
1318 /* Read the FBD Error Mask Register */
1319 pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1320 &fbd_error_mask);
1321
1322 /* Enable with a '0' */
1323 fbd_error_mask &= ~(ENABLE_EMASK_ALL);
1324
1325 pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
1326 fbd_error_mask);
1327 }
1328
1329 /*
1330 * i5000_get_dimm_and_channel_counts(pdev, &nr_csrows, &num_channels)
1331 *
1332 * ask the device how many channels are present and how many CSROWS
1333 * as well
1334 */
1335 static void i5000_get_dimm_and_channel_counts(struct pci_dev *pdev,
1336 int *num_dimms_per_channel,
1337 int *num_channels)
1338 {
1339 u8 value;
1340
1341 /* Need to retrieve just how many channels and dimms per channel are
1342 * supported on this memory controller
1343 */
1344 pci_read_config_byte(pdev, MAXDIMMPERCH, &value);
1345 *num_dimms_per_channel = (int)value;
1346
1347 pci_read_config_byte(pdev, MAXCH, &value);
1348 *num_channels = (int)value;
1349 }
1350
1351 /*
1352 * i5000_probe1 Probe for ONE instance of device to see if it is
1353 * present.
1354 * return:
1355 * 0 for FOUND a device
1356 * < 0 for error code
1357 */
1358 static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
1359 {
1360 struct mem_ctl_info *mci;
1361 struct edac_mc_layer layers[3];
1362 struct i5000_pvt *pvt;
1363 int num_channels;
1364 int num_dimms_per_channel;
1365
1366 debugf0("MC: %s(), pdev bus %u dev=0x%x fn=0x%x\n",
1367 __FILE__, pdev->bus->number,
1368 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
1369
1370 /* We only are looking for func 0 of the set */
1371 if (PCI_FUNC(pdev->devfn) != 0)
1372 return -ENODEV;
1373
1374 /* Ask the devices for the number of CSROWS and CHANNELS so
1375 * that we can calculate the memory resources, etc
1376 *
1377 * The Chipset will report what it can handle which will be greater
1378 * or equal to what the motherboard manufacturer will implement.
1379 *
1380 * As we don't have a motherboard identification routine to determine
1381 * actual number of slots/dimms per channel, we thus utilize the
1382 * resource as specified by the chipset. Thus, we might have
1383 * have more DIMMs per channel than actually on the mobo, but this
1384 * allows the driver to support up to the chipset max, without
1385 * some fancy mobo determination.
1386 */
1387 i5000_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel,
1388 &num_channels);
1389
1390 debugf0("MC: Number of Branches=2 Channels= %d DIMMS= %d\n",
1391 num_channels, num_dimms_per_channel);
1392
1393 /* allocate a new MC control structure */
1394
1395 layers[0].type = EDAC_MC_LAYER_BRANCH;
1396 layers[0].size = MAX_BRANCHES;
1397 layers[0].is_virt_csrow = false;
1398 layers[1].type = EDAC_MC_LAYER_CHANNEL;
1399 layers[1].size = num_channels / MAX_BRANCHES;
1400 layers[1].is_virt_csrow = false;
1401 layers[2].type = EDAC_MC_LAYER_SLOT;
1402 layers[2].size = num_dimms_per_channel;
1403 layers[2].is_virt_csrow = true;
1404 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
1405 if (mci == NULL)
1406 return -ENOMEM;
1407
1408 debugf0("MC: %s(): mci = %p\n", __FILE__, mci);
1409
1410 mci->pdev = &pdev->dev; /* record ptr to the generic device */
1411
1412 pvt = mci->pvt_info;
1413 pvt->system_address = pdev; /* Record this device in our private */
1414 pvt->maxch = num_channels;
1415 pvt->maxdimmperch = num_dimms_per_channel;
1416
1417 /* 'get' the pci devices we want to reserve for our use */
1418 if (i5000_get_devices(mci, dev_idx))
1419 goto fail0;
1420
1421 /* Time to get serious */
1422 i5000_get_mc_regs(mci); /* retrieve the hardware registers */
1423
1424 mci->mc_idx = 0;
1425 mci->mtype_cap = MEM_FLAG_FB_DDR2;
1426 mci->edac_ctl_cap = EDAC_FLAG_NONE;
1427 mci->edac_cap = EDAC_FLAG_NONE;
1428 mci->mod_name = "i5000_edac.c";
1429 mci->mod_ver = I5000_REVISION;
1430 mci->ctl_name = i5000_devs[dev_idx].ctl_name;
1431 mci->dev_name = pci_name(pdev);
1432 mci->ctl_page_to_phys = NULL;
1433
1434 /* Set the function pointer to an actual operation function */
1435 mci->edac_check = i5000_check_error;
1436
1437 /* initialize the MC control structure 'csrows' table
1438 * with the mapping and control information */
1439 if (i5000_init_csrows(mci)) {
1440 debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
1441 " because i5000_init_csrows() returned nonzero "
1442 "value\n");
1443 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
1444 } else {
1445 debugf1("MC: Enable error reporting now\n");
1446 i5000_enable_error_reporting(mci);
1447 }
1448
1449 /* add this new MC control structure to EDAC's list of MCs */
1450 if (edac_mc_add_mc(mci)) {
1451 debugf0("MC: %s(): failed edac_mc_add_mc()\n",
1452 __FILE__);
1453 /* FIXME: perhaps some code should go here that disables error
1454 * reporting if we just enabled it
1455 */
1456 goto fail1;
1457 }
1458
1459 i5000_clear_error(mci);
1460
1461 /* allocating generic PCI control info */
1462 i5000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
1463 if (!i5000_pci) {
1464 printk(KERN_WARNING
1465 "%s(): Unable to create PCI control\n",
1466 __func__);
1467 printk(KERN_WARNING
1468 "%s(): PCI error report via EDAC not setup\n",
1469 __func__);
1470 }
1471
1472 return 0;
1473
1474 /* Error exit unwinding stack */
1475 fail1:
1476
1477 i5000_put_devices(mci);
1478
1479 fail0:
1480 edac_mc_free(mci);
1481 return -ENODEV;
1482 }
1483
1484 /*
1485 * i5000_init_one constructor for one instance of device
1486 *
1487 * returns:
1488 * negative on error
1489 * count (>= 0)
1490 */
1491 static int __devinit i5000_init_one(struct pci_dev *pdev,
1492 const struct pci_device_id *id)
1493 {
1494 int rc;
1495
1496 debugf0("MC: %s()\n", __FILE__);
1497
1498 /* wake up device */
1499 rc = pci_enable_device(pdev);
1500 if (rc)
1501 return rc;
1502
1503 /* now probe and enable the device */
1504 return i5000_probe1(pdev, id->driver_data);
1505 }
1506
1507 /*
1508 * i5000_remove_one destructor for one instance of device
1509 *
1510 */
1511 static void __devexit i5000_remove_one(struct pci_dev *pdev)
1512 {
1513 struct mem_ctl_info *mci;
1514
1515 debugf0("%s()\n", __FILE__);
1516
1517 if (i5000_pci)
1518 edac_pci_release_generic_ctl(i5000_pci);
1519
1520 if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
1521 return;
1522
1523 /* retrieve references to resources, and free those resources */
1524 i5000_put_devices(mci);
1525 edac_mc_free(mci);
1526 }
1527
1528 /*
1529 * pci_device_id table for which devices we are looking for
1530 *
1531 * The "E500P" device is the first device supported.
1532 */
1533 static DEFINE_PCI_DEVICE_TABLE(i5000_pci_tbl) = {
1534 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000_DEV16),
1535 .driver_data = I5000P},
1536
1537 {0,} /* 0 terminated list. */
1538 };
1539
1540 MODULE_DEVICE_TABLE(pci, i5000_pci_tbl);
1541
1542 /*
1543 * i5000_driver pci_driver structure for this module
1544 *
1545 */
1546 static struct pci_driver i5000_driver = {
1547 .name = KBUILD_BASENAME,
1548 .probe = i5000_init_one,
1549 .remove = __devexit_p(i5000_remove_one),
1550 .id_table = i5000_pci_tbl,
1551 };
1552
1553 /*
1554 * i5000_init Module entry function
1555 * Try to initialize this module for its devices
1556 */
1557 static int __init i5000_init(void)
1558 {
1559 int pci_rc;
1560
1561 debugf2("MC: %s()\n", __FILE__);
1562
1563 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
1564 opstate_init();
1565
1566 pci_rc = pci_register_driver(&i5000_driver);
1567
1568 return (pci_rc < 0) ? pci_rc : 0;
1569 }
1570
1571 /*
1572 * i5000_exit() Module exit function
1573 * Unregister the driver
1574 */
1575 static void __exit i5000_exit(void)
1576 {
1577 debugf2("MC: %s()\n", __FILE__);
1578 pci_unregister_driver(&i5000_driver);
1579 }
1580
1581 module_init(i5000_init);
1582 module_exit(i5000_exit);
1583
1584 MODULE_LICENSE("GPL");
1585 MODULE_AUTHOR
1586 ("Linux Networx (http://lnxi.com) Doug Thompson <norsk5@xmission.com>");
1587 MODULE_DESCRIPTION("MC Driver for Intel I5000 memory controllers - "
1588 I5000_REVISION);
1589
1590 module_param(edac_op_state, int, 0444);
1591 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
1592 module_param(misc_messages, int, 0444);
1593 MODULE_PARM_DESC(misc_messages, "Log miscellaneous non fatal messages");
1594
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