drivers/edac/i82860_edac.c

   1 /*
   2  * Intel 82860 Memory Controller kernel module
   3  * (C) 2005 Red Hat (http://www.redhat.com)
   4  * This file may be distributed under the terms of the
   5  * GNU General Public License.
   6  *
   7  * Written by Ben Woodard <woodard@redhat.com>
   8  * shamelessly copied from and based upon the edac_i82875 driver
   9  * by Thayne Harbaugh of Linux Networx. (http://lnxi.com)
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/pci_ids.h>
  16 #include <linux/edac.h>
  17 #include "edac_core.h"
  18
  19 #define  I82860_REVISION " Ver: 2.0.2"
  20 #define EDAC_MOD_STR    "i82860_edac"
  21
  22 #define i82860_printk(level, fmt, arg...) \
  23         edac_printk(level, "i82860", fmt, ##arg)
  24
  25 #define i82860_mc_printk(mci, level, fmt, arg...) \
  26         edac_mc_chipset_printk(mci, level, "i82860", fmt, ##arg)
  27
  28 #ifndef PCI_DEVICE_ID_INTEL_82860_0
  29 #define PCI_DEVICE_ID_INTEL_82860_0     0x2531
  30 #endif                          /* PCI_DEVICE_ID_INTEL_82860_0 */
  31
  32 #define I82860_MCHCFG 0x50
  33 #define I82860_GBA 0x60
  34 #define I82860_GBA_MASK 0x7FF
  35 #define I82860_GBA_SHIFT 24
  36 #define I82860_ERRSTS 0xC8
  37 #define I82860_EAP 0xE4
  38 #define I82860_DERRCTL_STS 0xE2
  39
  40 enum i82860_chips {
  41         I82860 = 0,
  42 };
  43
  44 struct i82860_dev_info {
  45         const char *ctl_name;
  46 };
  47
  48 struct i82860_error_info {
  49         u16 errsts;
  50         u32 eap;
  51         u16 derrsyn;
  52         u16 errsts2;
  53 };
  54
  55 static const struct i82860_dev_info i82860_devs[] = {
  56         [I82860] = {
  57                 .ctl_name = "i82860"},
  58 };
  59
  60 static struct pci_dev *mci_pdev;        /* init dev: in case that AGP code
  61                                          * has already registered driver
  62                                          */
  63 static struct edac_pci_ctl_info *i82860_pci;
  64
  65 static void i82860_get_error_info(struct mem_ctl_info *mci,
  66                                 struct i82860_error_info *info)
  67 {
  68         struct pci_dev *pdev;
  69
  70         pdev = to_pci_dev(mci->dev);
  71
  72         /*
  73          * This is a mess because there is no atomic way to read all the
  74          * registers at once and the registers can transition from CE being
  75          * overwritten by UE.
  76          */
  77         pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts);
  78         pci_read_config_dword(pdev, I82860_EAP, &info->eap);
  79         pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
  80         pci_read_config_word(pdev, I82860_ERRSTS, &info->errsts2);
  81
  82         pci_write_bits16(pdev, I82860_ERRSTS, 0x0003, 0x0003);
  83
  84         /*
  85          * If the error is the same for both reads then the first set of reads
  86          * is valid.  If there is a change then there is a CE no info and the
  87          * second set of reads is valid and should be UE info.
  88          */
  89         if (!(info->errsts2 & 0x0003))
  90                 return;
  91
  92         if ((info->errsts ^ info->errsts2) & 0x0003) {
  93                 pci_read_config_dword(pdev, I82860_EAP, &info->eap);
  94                 pci_read_config_word(pdev, I82860_DERRCTL_STS, &info->derrsyn);
  95         }
  96 }
  97
  98 static int i82860_process_error_info(struct mem_ctl_info *mci,
  99                                 struct i82860_error_info *info,
 100                                 int handle_errors)
 101 {
 102         struct dimm_info *dimm;
 103         int row;
 104
 105         if (!(info->errsts2 & 0x0003))
 106                 return 0;
 107
 108         if (!handle_errors)
 109                 return 1;
 110
 111         if ((info->errsts ^ info->errsts2) & 0x0003) {
 112                 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0,
 113                                      -1, -1, -1, "UE overwrote CE", "", NULL);
 114                 info->errsts = info->errsts2;
 115         }
 116
 117         info->eap >>= PAGE_SHIFT;
 118         row = edac_mc_find_csrow_by_page(mci, info->eap);
 119         dimm = mci->csrows[row].channels[0].dimm;
 120
 121         if (info->errsts & 0x0002)
 122                 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
 123                                      info->eap, 0, 0,
 124                                      dimm->location[0], dimm->location[1], -1,
 125                                      "i82860 UE", "", NULL);
 126         else
 127                 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
 128                                      info->eap, 0, info->derrsyn,
 129                                      dimm->location[0], dimm->location[1], -1,
 130                                      "i82860 CE", "", NULL);
 131
 132         return 1;
 133 }
 134
 135 static void i82860_check(struct mem_ctl_info *mci)
 136 {
 137         struct i82860_error_info info;
 138
 139         debugf1("MC%d: %s()\n", mci->mc_idx, __func__);
 140         i82860_get_error_info(mci, &info);
 141         i82860_process_error_info(mci, &info, 1);
 142 }
 143
 144 static void i82860_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev)
 145 {
 146         unsigned long last_cumul_size;
 147         u16 mchcfg_ddim;        /* DRAM Data Integrity Mode 0=none, 2=edac */
 148         u16 value;
 149         u32 cumul_size;
 150         struct csrow_info *csrow;
 151         struct dimm_info *dimm;
 152         int index;
 153
 154         pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim);
 155         mchcfg_ddim = mchcfg_ddim & 0x180;
 156         last_cumul_size = 0;
 157
 158         /* The group row boundary (GRA) reg values are boundary address
 159          * for each DRAM row with a granularity of 16MB.  GRA regs are
 160          * cumulative; therefore GRA15 will contain the total memory contained
 161          * in all eight rows.
 162          */
 163         for (index = 0; index < mci->nr_csrows; index++) {
 164                 csrow = &mci->csrows[index];
 165                 dimm = csrow->channels[0].dimm;
 166
 167                 pci_read_config_word(pdev, I82860_GBA + index * 2, &value);
 168                 cumul_size = (value & I82860_GBA_MASK) <<
 169                         (I82860_GBA_SHIFT - PAGE_SHIFT);
 170                 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
 171                         cumul_size);
 172
 173                 if (cumul_size == last_cumul_size)
 174                         continue;       /* not populated */
 175
 176                 csrow->first_page = last_cumul_size;
 177                 csrow->last_page = cumul_size - 1;
 178                 dimm->nr_pages = cumul_size - last_cumul_size;
 179                 last_cumul_size = cumul_size;
 180                 dimm->grain = 1 << 12;  /* I82860_EAP has 4KiB reolution */
 181                 dimm->mtype = MEM_RMBS;
 182                 dimm->dtype = DEV_UNKNOWN;
 183                 dimm->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
 184         }
 185 }
 186
 187 static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
 188 {
 189         struct mem_ctl_info *mci;
 190         struct edac_mc_layer layers[2];
 191         struct i82860_error_info discard;
 192
 193         /*
 194          * RDRAM has channels but these don't map onto the csrow abstraction.
 195          * According with the datasheet, there are 2 Rambus channels, supporting
 196          * up to 16 direct RDRAM devices.
 197          * The device groups from the GRA registers seem to map reasonably
 198          * well onto the notion of a chip select row.
 199          * There are 16 GRA registers and since the name is associated with
 200          * the channel and the GRA registers map to physical devices so we are
 201          * going to make 1 channel for group.
 202          */
 203         layers[0].type = EDAC_MC_LAYER_CHANNEL;
 204         layers[0].size = 2;
 205         layers[0].is_virt_csrow = true;
 206         layers[1].type = EDAC_MC_LAYER_SLOT;
 207         layers[1].size = 8;
 208         layers[1].is_virt_csrow = true;
 209         mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
 210         if (!mci)
 211                 return -ENOMEM;
 212
 213         debugf3("%s(): init mci\n", __func__);
 214         mci->dev = &pdev->dev;
 215         mci->mtype_cap = MEM_FLAG_DDR;
 216         mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
 217         /* I"m not sure about this but I think that all RDRAM is SECDED */
 218         mci->edac_cap = EDAC_FLAG_SECDED;
 219         mci->mod_name = EDAC_MOD_STR;
 220         mci->mod_ver = I82860_REVISION;
 221         mci->ctl_name = i82860_devs[dev_idx].ctl_name;
 222         mci->dev_name = pci_name(pdev);
 223         mci->edac_check = i82860_check;
 224         mci->ctl_page_to_phys = NULL;
 225         i82860_init_csrows(mci, pdev);
 226         i82860_get_error_info(mci, &discard);   /* clear counters */
 227
 228         /* Here we assume that we will never see multiple instances of this
 229          * type of memory controller.  The ID is therefore hardcoded to 0.
 230          */
 231         if (edac_mc_add_mc(mci)) {
 232                 debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
 233                 goto fail;
 234         }
 235
 236         /* allocating generic PCI control info */
 237         i82860_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
 238         if (!i82860_pci) {
 239                 printk(KERN_WARNING
 240                         "%s(): Unable to create PCI control\n",
 241                         __func__);
 242                 printk(KERN_WARNING
 243                         "%s(): PCI error report via EDAC not setup\n",
 244                         __func__);
 245         }
 246
 247         /* get this far and it's successful */
 248         debugf3("%s(): success\n", __func__);
 249
 250         return 0;
 251
 252 fail:
 253         edac_mc_free(mci);
 254         return -ENODEV;
 255 }
 256
 257 /* returns count (>= 0), or negative on error */
 258 static int __devinit i82860_init_one(struct pci_dev *pdev,
 259                                 const struct pci_device_id *ent)
 260 {
 261         int rc;
 262
 263         debugf0("%s()\n", __func__);
 264         i82860_printk(KERN_INFO, "i82860 init one\n");
 265
 266         if (pci_enable_device(pdev) < 0)
 267                 return -EIO;
 268
 269         rc = i82860_probe1(pdev, ent->driver_data);
 270
 271         if (rc == 0)
 272                 mci_pdev = pci_dev_get(pdev);
 273
 274         return rc;
 275 }
 276
 277 static void __devexit i82860_remove_one(struct pci_dev *pdev)
 278 {
 279         struct mem_ctl_info *mci;
 280
 281         debugf0("%s()\n", __func__);
 282
 283         if (i82860_pci)
 284                 edac_pci_release_generic_ctl(i82860_pci);
 285
 286         if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
 287                 return;
 288
 289         edac_mc_free(mci);
 290 }
 291
 292 static DEFINE_PCI_DEVICE_TABLE(i82860_pci_tbl) = {
 293         {
 294          PCI_VEND_DEV(INTEL, 82860_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 295          I82860},
 296         {
 297          0,
 298          }                      /* 0 terminated list. */
 299 };
 300
 301 MODULE_DEVICE_TABLE(pci, i82860_pci_tbl);
 302
 303 static struct pci_driver i82860_driver = {
 304         .name = EDAC_MOD_STR,
 305         .probe = i82860_init_one,
 306         .remove = __devexit_p(i82860_remove_one),
 307         .id_table = i82860_pci_tbl,
 308 };
 309
 310 static int __init i82860_init(void)
 311 {
 312         int pci_rc;
 313
 314         debugf3("%s()\n", __func__);
 315
 316        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
 317        opstate_init();
 318
 319         if ((pci_rc = pci_register_driver(&i82860_driver)) < 0)
 320                 goto fail0;
 321
 322         if (!mci_pdev) {
 323                 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
 324                                         PCI_DEVICE_ID_INTEL_82860_0, NULL);
 325
 326                 if (mci_pdev == NULL) {
 327                         debugf0("860 pci_get_device fail\n");
 328                         pci_rc = -ENODEV;
 329                         goto fail1;
 330                 }
 331
 332                 pci_rc = i82860_init_one(mci_pdev, i82860_pci_tbl);
 333
 334                 if (pci_rc < 0) {
 335                         debugf0("860 init fail\n");
 336                         pci_rc = -ENODEV;
 337                         goto fail1;
 338                 }
 339         }
 340
 341         return 0;
 342
 343 fail1:
 344         pci_unregister_driver(&i82860_driver);
 345
 346 fail0:
 347         if (mci_pdev != NULL)
 348                 pci_dev_put(mci_pdev);
 349
 350         return pci_rc;
 351 }
 352
 353 static void __exit i82860_exit(void)
 354 {
 355         debugf3("%s()\n", __func__);
 356
 357         pci_unregister_driver(&i82860_driver);
 358
 359         if (mci_pdev != NULL)
 360                 pci_dev_put(mci_pdev);
 361 }
 362
 363 module_init(i82860_init);
 364 module_exit(i82860_exit);
 365
 366 MODULE_LICENSE("GPL");
 367 MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com) "
 368                 "Ben Woodard <woodard@redhat.com>");
 369 MODULE_DESCRIPTION("ECC support for Intel 82860 memory hub controllers");
 370
 371 module_param(edac_op_state, int, 0444);
 372 MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");