2 * Intel D82875P Memory Controller kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
7 * Written by Thayne Harbaugh
9 * Wang Zhenyu at intel.com
11 * $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $
13 * Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/pci_ids.h>
20 #include <linux/edac.h>
21 #include "edac_core.h"
23 #define I82875P_REVISION " Ver: 2.0.2"
24 #define EDAC_MOD_STR "i82875p_edac"
26 #define i82875p_printk(level, fmt, arg...) \
27 edac_printk(level, "i82875p", fmt, ##arg)
29 #define i82875p_mc_printk(mci, level, fmt, arg...) \
30 edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg)
32 #ifndef PCI_DEVICE_ID_INTEL_82875_0
33 #define PCI_DEVICE_ID_INTEL_82875_0 0x2578
34 #endif /* PCI_DEVICE_ID_INTEL_82875_0 */
36 #ifndef PCI_DEVICE_ID_INTEL_82875_6
37 #define PCI_DEVICE_ID_INTEL_82875_6 0x257e
38 #endif /* PCI_DEVICE_ID_INTEL_82875_6 */
40 /* four csrows in dual channel, eight in single channel */
41 #define I82875P_NR_DIMMS 8
42 #define I82875P_NR_CSROWS(nr_chans) (I82875P_NR_DIMMS / (nr_chans))
44 /* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */
45 #define I82875P_EAP 0x58 /* Error Address Pointer (32b)
51 #define I82875P_DERRSYN 0x5c /* DRAM Error Syndrome (8b)
53 * 7:0 DRAM ECC Syndrome
56 #define I82875P_DES 0x5d /* DRAM Error Status (8b)
62 #define I82875P_ERRSTS 0xc8 /* Error Status Register (16b)
65 * 9 non-DRAM lock error (ndlock)
66 * 8 Sftwr Generated SMI
69 * 5 MCH detects unimplemented cycle
70 * 4 AGP access outside GA
71 * 3 Invalid AGP access
72 * 2 Invalid GA translation table
73 * 1 Unsupported AGP command
77 #define I82875P_ERRCMD 0xca /* Error Command (16b)
80 * 9 SERR on non-DRAM lock
83 * 6 target abort on high exception
84 * 5 detect unimplemented cyc
85 * 4 AGP access outside of GA
86 * 3 SERR on invalid AGP access
87 * 2 invalid translation table
88 * 1 SERR on unsupported AGP command
92 /* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */
93 #define I82875P_PCICMD6 0x04 /* PCI Command Register (16b)
96 * 9 fast back-to-back - ro 0
97 * 8 SERR enable - ro 0
98 * 7 addr/data stepping - ro 0
99 * 6 parity err enable - ro 0
100 * 5 VGA palette snoop - ro 0
101 * 4 mem wr & invalidate - ro 0
102 * 3 special cycle - ro 0
103 * 2 bus master - ro 0
104 * 1 mem access dev6 - 0(dis),1(en)
105 * 0 IO access dev3 - 0(dis),1(en)
108 #define I82875P_BAR6 0x10 /* Mem Delays Base ADDR Reg (32b)
110 * 31:12 mem base addr [31:12]
111 * 11:4 address mask - ro 0
112 * 3 prefetchable - ro 0(non),1(pre)
113 * 2:1 mem type - ro 0
117 /* Intel 82875p MMIO register space - device 0 function 0 - MMR space */
119 #define I82875P_DRB_SHIFT 26 /* 64MiB grain */
120 #define I82875P_DRB 0x00 /* DRAM Row Boundary (8b x 8)
123 * 6:0 64MiB row boundary addr
126 #define I82875P_DRA 0x10 /* DRAM Row Attribute (4b x 8)
139 #define I82875P_DRC 0x68 /* DRAM Controller Mode (32b)
144 * 22:21 nr chan 00=1,01=2
146 * 19:18 Data Integ Mode 00=none,01=ecc
152 * 1:0 DRAM type 01=DDR
160 struct pci_dev
*ovrfl_pdev
;
161 void __iomem
*ovrfl_window
;
164 struct i82875p_dev_info
{
165 const char *ctl_name
;
168 struct i82875p_error_info
{
176 static const struct i82875p_dev_info i82875p_devs
[] = {
178 .ctl_name
= "i82875p"},
181 static struct pci_dev
*mci_pdev
; /* init dev: in case that AGP code has
182 * already registered driver
185 static struct edac_pci_ctl_info
*i82875p_pci
;
187 static void i82875p_get_error_info(struct mem_ctl_info
*mci
,
188 struct i82875p_error_info
*info
)
190 struct pci_dev
*pdev
;
192 pdev
= to_pci_dev(mci
->dev
);
195 * This is a mess because there is no atomic way to read all the
196 * registers at once and the registers can transition from CE being
199 pci_read_config_word(pdev
, I82875P_ERRSTS
, &info
->errsts
);
201 if (!(info
->errsts
& 0x0081))
204 pci_read_config_dword(pdev
, I82875P_EAP
, &info
->eap
);
205 pci_read_config_byte(pdev
, I82875P_DES
, &info
->des
);
206 pci_read_config_byte(pdev
, I82875P_DERRSYN
, &info
->derrsyn
);
207 pci_read_config_word(pdev
, I82875P_ERRSTS
, &info
->errsts2
);
210 * If the error is the same then we can for both reads then
211 * the first set of reads is valid. If there is a change then
212 * there is a CE no info and the second set of reads is valid
213 * and should be UE info.
215 if ((info
->errsts
^ info
->errsts2
) & 0x0081) {
216 pci_read_config_dword(pdev
, I82875P_EAP
, &info
->eap
);
217 pci_read_config_byte(pdev
, I82875P_DES
, &info
->des
);
218 pci_read_config_byte(pdev
, I82875P_DERRSYN
, &info
->derrsyn
);
221 pci_write_bits16(pdev
, I82875P_ERRSTS
, 0x0081, 0x0081);
224 static int i82875p_process_error_info(struct mem_ctl_info
*mci
,
225 struct i82875p_error_info
*info
,
230 multi_chan
= mci
->csrows
[0].nr_channels
- 1;
232 if (!(info
->errsts
& 0x0081))
238 if ((info
->errsts
^ info
->errsts2
) & 0x0081) {
239 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED
, mci
, 0, 0, 0,
241 "UE overwrote CE", "", NULL
);
242 info
->errsts
= info
->errsts2
;
245 info
->eap
>>= PAGE_SHIFT
;
246 row
= edac_mc_find_csrow_by_page(mci
, info
->eap
);
248 if (info
->errsts
& 0x0080)
249 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED
, mci
,
252 "i82875p UE", "", NULL
);
254 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED
, mci
,
255 info
->eap
, 0, info
->derrsyn
,
256 row
, multi_chan
? (info
->des
& 0x1) : 0,
257 -1, "i82875p CE", "", NULL
);
262 static void i82875p_check(struct mem_ctl_info
*mci
)
264 struct i82875p_error_info info
;
266 debugf1("MC%d: %s()\n", mci
->mc_idx
, __func__
);
267 i82875p_get_error_info(mci
, &info
);
268 i82875p_process_error_info(mci
, &info
, 1);
271 /* Return 0 on success or 1 on failure. */
272 static int i82875p_setup_overfl_dev(struct pci_dev
*pdev
,
273 struct pci_dev
**ovrfl_pdev
,
274 void __iomem
**ovrfl_window
)
277 void __iomem
*window
;
281 *ovrfl_window
= NULL
;
282 dev
= pci_get_device(PCI_VEND_DEV(INTEL
, 82875_6
), NULL
);
285 /* Intel tells BIOS developers to hide device 6 which
286 * configures the overflow device access containing
287 * the DRBs - this is where we expose device 6.
288 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
290 pci_write_bits8(pdev
, 0xf4, 0x2, 0x2);
291 dev
= pci_scan_single_device(pdev
->bus
, PCI_DEVFN(6, 0));
296 err
= pci_bus_add_device(dev
);
298 i82875p_printk(KERN_ERR
,
299 "%s(): pci_bus_add_device() Failed\n",
302 pci_bus_assign_resources(dev
->bus
);
307 if (pci_enable_device(dev
)) {
308 i82875p_printk(KERN_ERR
, "%s(): Failed to enable overflow "
309 "device\n", __func__
);
313 if (pci_request_regions(dev
, pci_name(dev
))) {
319 /* cache is irrelevant for PCI bus reads/writes */
320 window
= pci_ioremap_bar(dev
, 0);
321 if (window
== NULL
) {
322 i82875p_printk(KERN_ERR
, "%s(): Failed to ioremap bar6\n",
327 *ovrfl_window
= window
;
331 pci_release_regions(dev
);
335 pci_disable_device(dev
);
337 /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
341 /* Return 1 if dual channel mode is active. Else return 0. */
342 static inline int dual_channel_active(u32 drc
)
344 return (drc
>> 21) & 0x1;
347 static void i82875p_init_csrows(struct mem_ctl_info
*mci
,
348 struct pci_dev
*pdev
,
349 void __iomem
* ovrfl_window
, u32 drc
)
351 struct csrow_info
*csrow
;
352 struct dimm_info
*dimm
;
353 unsigned nr_chans
= dual_channel_active(drc
) + 1;
354 unsigned long last_cumul_size
;
356 u32 drc_ddim
; /* DRAM Data Integrity Mode 0=none,2=edac */
357 u32 cumul_size
, nr_pages
;
360 drc_ddim
= (drc
>> 18) & 0x1;
363 /* The dram row boundary (DRB) reg values are boundary address
364 * for each DRAM row with a granularity of 32 or 64MB (single/dual
365 * channel operation). DRB regs are cumulative; therefore DRB7 will
366 * contain the total memory contained in all eight rows.
369 for (index
= 0; index
< mci
->nr_csrows
; index
++) {
370 csrow
= &mci
->csrows
[index
];
372 value
= readb(ovrfl_window
+ I82875P_DRB
+ index
);
373 cumul_size
= value
<< (I82875P_DRB_SHIFT
- PAGE_SHIFT
);
374 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__
, index
,
376 if (cumul_size
== last_cumul_size
)
377 continue; /* not populated */
379 csrow
->first_page
= last_cumul_size
;
380 csrow
->last_page
= cumul_size
- 1;
381 nr_pages
= cumul_size
- last_cumul_size
;
382 last_cumul_size
= cumul_size
;
384 for (j
= 0; j
< nr_chans
; j
++) {
385 dimm
= csrow
->channels
[j
].dimm
;
387 dimm
->nr_pages
= nr_pages
/ nr_chans
;
388 dimm
->grain
= 1 << 12; /* I82875P_EAP has 4KiB reolution */
389 dimm
->mtype
= MEM_DDR
;
390 dimm
->dtype
= DEV_UNKNOWN
;
391 dimm
->edac_mode
= drc_ddim
? EDAC_SECDED
: EDAC_NONE
;
396 static int i82875p_probe1(struct pci_dev
*pdev
, int dev_idx
)
399 struct mem_ctl_info
*mci
;
400 struct edac_mc_layer layers
[2];
401 struct i82875p_pvt
*pvt
;
402 struct pci_dev
*ovrfl_pdev
;
403 void __iomem
*ovrfl_window
;
406 struct i82875p_error_info discard
;
408 debugf0("%s()\n", __func__
);
410 ovrfl_pdev
= pci_get_device(PCI_VEND_DEV(INTEL
, 82875_6
), NULL
);
412 if (i82875p_setup_overfl_dev(pdev
, &ovrfl_pdev
, &ovrfl_window
))
414 drc
= readl(ovrfl_window
+ I82875P_DRC
);
415 nr_chans
= dual_channel_active(drc
) + 1;
417 layers
[0].type
= EDAC_MC_LAYER_CHIP_SELECT
;
418 layers
[0].size
= I82875P_NR_CSROWS(nr_chans
);
419 layers
[0].is_virt_csrow
= true;
420 layers
[1].type
= EDAC_MC_LAYER_CHANNEL
;
421 layers
[1].size
= nr_chans
;
422 layers
[1].is_virt_csrow
= false;
423 mci
= edac_mc_alloc(0, ARRAY_SIZE(layers
), layers
, sizeof(*pvt
));
429 /* Keeps mci available after edac_mc_del_mc() till edac_mc_free() */
430 kobject_get(&mci
->edac_mci_kobj
);
432 debugf3("%s(): init mci\n", __func__
);
433 mci
->dev
= &pdev
->dev
;
434 mci
->mtype_cap
= MEM_FLAG_DDR
;
435 mci
->edac_ctl_cap
= EDAC_FLAG_NONE
| EDAC_FLAG_SECDED
;
436 mci
->edac_cap
= EDAC_FLAG_UNKNOWN
;
437 mci
->mod_name
= EDAC_MOD_STR
;
438 mci
->mod_ver
= I82875P_REVISION
;
439 mci
->ctl_name
= i82875p_devs
[dev_idx
].ctl_name
;
440 mci
->dev_name
= pci_name(pdev
);
441 mci
->edac_check
= i82875p_check
;
442 mci
->ctl_page_to_phys
= NULL
;
443 debugf3("%s(): init pvt\n", __func__
);
444 pvt
= (struct i82875p_pvt
*)mci
->pvt_info
;
445 pvt
->ovrfl_pdev
= ovrfl_pdev
;
446 pvt
->ovrfl_window
= ovrfl_window
;
447 i82875p_init_csrows(mci
, pdev
, ovrfl_window
, drc
);
448 i82875p_get_error_info(mci
, &discard
); /* clear counters */
450 /* Here we assume that we will never see multiple instances of this
451 * type of memory controller. The ID is therefore hardcoded to 0.
453 if (edac_mc_add_mc(mci
)) {
454 debugf3("%s(): failed edac_mc_add_mc()\n", __func__
);
458 /* allocating generic PCI control info */
459 i82875p_pci
= edac_pci_create_generic_ctl(&pdev
->dev
, EDAC_MOD_STR
);
462 "%s(): Unable to create PCI control\n",
465 "%s(): PCI error report via EDAC not setup\n",
469 /* get this far and it's successful */
470 debugf3("%s(): success\n", __func__
);
474 kobject_put(&mci
->edac_mci_kobj
);
478 iounmap(ovrfl_window
);
479 pci_release_regions(ovrfl_pdev
);
481 pci_disable_device(ovrfl_pdev
);
482 /* NOTE: the ovrfl proc entry and pci_dev are intentionally left */
486 /* returns count (>= 0), or negative on error */
487 static int __devinit
i82875p_init_one(struct pci_dev
*pdev
,
488 const struct pci_device_id
*ent
)
492 debugf0("%s()\n", __func__
);
493 i82875p_printk(KERN_INFO
, "i82875p init one\n");
495 if (pci_enable_device(pdev
) < 0)
498 rc
= i82875p_probe1(pdev
, ent
->driver_data
);
500 if (mci_pdev
== NULL
)
501 mci_pdev
= pci_dev_get(pdev
);
506 static void __devexit
i82875p_remove_one(struct pci_dev
*pdev
)
508 struct mem_ctl_info
*mci
;
509 struct i82875p_pvt
*pvt
= NULL
;
511 debugf0("%s()\n", __func__
);
514 edac_pci_release_generic_ctl(i82875p_pci
);
516 if ((mci
= edac_mc_del_mc(&pdev
->dev
)) == NULL
)
519 pvt
= (struct i82875p_pvt
*)mci
->pvt_info
;
521 if (pvt
->ovrfl_window
)
522 iounmap(pvt
->ovrfl_window
);
524 if (pvt
->ovrfl_pdev
) {
526 pci_release_regions(pvt
->ovrfl_pdev
);
527 #endif /*CORRECT_BIOS */
528 pci_disable_device(pvt
->ovrfl_pdev
);
529 pci_dev_put(pvt
->ovrfl_pdev
);
535 static DEFINE_PCI_DEVICE_TABLE(i82875p_pci_tbl
) = {
537 PCI_VEND_DEV(INTEL
, 82875_0
), PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
541 } /* 0 terminated list. */
544 MODULE_DEVICE_TABLE(pci
, i82875p_pci_tbl
);
546 static struct pci_driver i82875p_driver
= {
547 .name
= EDAC_MOD_STR
,
548 .probe
= i82875p_init_one
,
549 .remove
= __devexit_p(i82875p_remove_one
),
550 .id_table
= i82875p_pci_tbl
,
553 static int __init
i82875p_init(void)
557 debugf3("%s()\n", __func__
);
559 /* Ensure that the OPSTATE is set correctly for POLL or NMI */
562 pci_rc
= pci_register_driver(&i82875p_driver
);
567 if (mci_pdev
== NULL
) {
568 mci_pdev
= pci_get_device(PCI_VENDOR_ID_INTEL
,
569 PCI_DEVICE_ID_INTEL_82875_0
, NULL
);
572 debugf0("875p pci_get_device fail\n");
577 pci_rc
= i82875p_init_one(mci_pdev
, i82875p_pci_tbl
);
580 debugf0("875p init fail\n");
589 pci_unregister_driver(&i82875p_driver
);
592 if (mci_pdev
!= NULL
)
593 pci_dev_put(mci_pdev
);
598 static void __exit
i82875p_exit(void)
600 debugf3("%s()\n", __func__
);
602 i82875p_remove_one(mci_pdev
);
603 pci_dev_put(mci_pdev
);
605 pci_unregister_driver(&i82875p_driver
);
609 module_init(i82875p_init
);
610 module_exit(i82875p_exit
);
612 MODULE_LICENSE("GPL");
613 MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh");
614 MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers");
616 module_param(edac_op_state
, int, 0444);
617 MODULE_PARM_DESC(edac_op_state
, "EDAC Error Reporting state: 0=Poll,1=NMI");