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Merge git://git.infradead.org/mtd-2.6
[deliverable/linux.git] / drivers / firewire / fw-ohci.c
1 /*
2 * Driver for OHCI 1394 controllers
3 *
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/gfp.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
28 #include <linux/mm.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/pci.h>
32 #include <linux/spinlock.h>
33
34 #include <asm/page.h>
35 #include <asm/system.h>
36
37 #ifdef CONFIG_PPC_PMAC
38 #include <asm/pmac_feature.h>
39 #endif
40
41 #include "fw-ohci.h"
42 #include "fw-transaction.h"
43
44 #define DESCRIPTOR_OUTPUT_MORE 0
45 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
46 #define DESCRIPTOR_INPUT_MORE (2 << 12)
47 #define DESCRIPTOR_INPUT_LAST (3 << 12)
48 #define DESCRIPTOR_STATUS (1 << 11)
49 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
50 #define DESCRIPTOR_PING (1 << 7)
51 #define DESCRIPTOR_YY (1 << 6)
52 #define DESCRIPTOR_NO_IRQ (0 << 4)
53 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
54 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
55 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
56 #define DESCRIPTOR_WAIT (3 << 0)
57
58 struct descriptor {
59 __le16 req_count;
60 __le16 control;
61 __le32 data_address;
62 __le32 branch_address;
63 __le16 res_count;
64 __le16 transfer_status;
65 } __attribute__((aligned(16)));
66
67 struct db_descriptor {
68 __le16 first_size;
69 __le16 control;
70 __le16 second_req_count;
71 __le16 first_req_count;
72 __le32 branch_address;
73 __le16 second_res_count;
74 __le16 first_res_count;
75 __le32 reserved0;
76 __le32 first_buffer;
77 __le32 second_buffer;
78 __le32 reserved1;
79 } __attribute__((aligned(16)));
80
81 #define CONTROL_SET(regs) (regs)
82 #define CONTROL_CLEAR(regs) ((regs) + 4)
83 #define COMMAND_PTR(regs) ((regs) + 12)
84 #define CONTEXT_MATCH(regs) ((regs) + 16)
85
86 struct ar_buffer {
87 struct descriptor descriptor;
88 struct ar_buffer *next;
89 __le32 data[0];
90 };
91
92 struct ar_context {
93 struct fw_ohci *ohci;
94 struct ar_buffer *current_buffer;
95 struct ar_buffer *last_buffer;
96 void *pointer;
97 u32 regs;
98 struct tasklet_struct tasklet;
99 };
100
101 struct context;
102
103 typedef int (*descriptor_callback_t)(struct context *ctx,
104 struct descriptor *d,
105 struct descriptor *last);
106
107 /*
108 * A buffer that contains a block of DMA-able coherent memory used for
109 * storing a portion of a DMA descriptor program.
110 */
111 struct descriptor_buffer {
112 struct list_head list;
113 dma_addr_t buffer_bus;
114 size_t buffer_size;
115 size_t used;
116 struct descriptor buffer[0];
117 };
118
119 struct context {
120 struct fw_ohci *ohci;
121 u32 regs;
122 int total_allocation;
123
124 /*
125 * List of page-sized buffers for storing DMA descriptors.
126 * Head of list contains buffers in use and tail of list contains
127 * free buffers.
128 */
129 struct list_head buffer_list;
130
131 /*
132 * Pointer to a buffer inside buffer_list that contains the tail
133 * end of the current DMA program.
134 */
135 struct descriptor_buffer *buffer_tail;
136
137 /*
138 * The descriptor containing the branch address of the first
139 * descriptor that has not yet been filled by the device.
140 */
141 struct descriptor *last;
142
143 /*
144 * The last descriptor in the DMA program. It contains the branch
145 * address that must be updated upon appending a new descriptor.
146 */
147 struct descriptor *prev;
148
149 descriptor_callback_t callback;
150
151 struct tasklet_struct tasklet;
152 };
153
154 #define IT_HEADER_SY(v) ((v) << 0)
155 #define IT_HEADER_TCODE(v) ((v) << 4)
156 #define IT_HEADER_CHANNEL(v) ((v) << 8)
157 #define IT_HEADER_TAG(v) ((v) << 14)
158 #define IT_HEADER_SPEED(v) ((v) << 16)
159 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
160
161 struct iso_context {
162 struct fw_iso_context base;
163 struct context context;
164 int excess_bytes;
165 void *header;
166 size_t header_length;
167 };
168
169 #define CONFIG_ROM_SIZE 1024
170
171 struct fw_ohci {
172 struct fw_card card;
173
174 __iomem char *registers;
175 dma_addr_t self_id_bus;
176 __le32 *self_id_cpu;
177 struct tasklet_struct bus_reset_tasklet;
178 int node_id;
179 int generation;
180 int request_generation; /* for timestamping incoming requests */
181 u32 bus_seconds;
182
183 bool use_dualbuffer;
184 bool old_uninorth;
185 bool bus_reset_packet_quirk;
186
187 /*
188 * Spinlock for accessing fw_ohci data. Never call out of
189 * this driver with this lock held.
190 */
191 spinlock_t lock;
192 u32 self_id_buffer[512];
193
194 /* Config rom buffers */
195 __be32 *config_rom;
196 dma_addr_t config_rom_bus;
197 __be32 *next_config_rom;
198 dma_addr_t next_config_rom_bus;
199 u32 next_header;
200
201 struct ar_context ar_request_ctx;
202 struct ar_context ar_response_ctx;
203 struct context at_request_ctx;
204 struct context at_response_ctx;
205
206 u32 it_context_mask;
207 struct iso_context *it_context_list;
208 u32 ir_context_mask;
209 struct iso_context *ir_context_list;
210 };
211
212 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
213 {
214 return container_of(card, struct fw_ohci, card);
215 }
216
217 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
218 #define IR_CONTEXT_BUFFER_FILL 0x80000000
219 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
220 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
221 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
222 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
223
224 #define CONTEXT_RUN 0x8000
225 #define CONTEXT_WAKE 0x1000
226 #define CONTEXT_DEAD 0x0800
227 #define CONTEXT_ACTIVE 0x0400
228
229 #define OHCI1394_MAX_AT_REQ_RETRIES 0x2
230 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
231 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
232
233 #define FW_OHCI_MAJOR 240
234 #define OHCI1394_REGISTER_SIZE 0x800
235 #define OHCI_LOOP_COUNT 500
236 #define OHCI1394_PCI_HCI_Control 0x40
237 #define SELF_ID_BUF_SIZE 0x800
238 #define OHCI_TCODE_PHY_PACKET 0x0e
239 #define OHCI_VERSION_1_1 0x010010
240
241 static char ohci_driver_name[] = KBUILD_MODNAME;
242
243 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
244
245 #define OHCI_PARAM_DEBUG_AT_AR 1
246 #define OHCI_PARAM_DEBUG_SELFIDS 2
247 #define OHCI_PARAM_DEBUG_IRQS 4
248 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
249
250 static int param_debug;
251 module_param_named(debug, param_debug, int, 0644);
252 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
253 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
254 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
255 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
256 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
257 ", or a combination, or all = -1)");
258
259 static void log_irqs(u32 evt)
260 {
261 if (likely(!(param_debug &
262 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
263 return;
264
265 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
266 !(evt & OHCI1394_busReset))
267 return;
268
269 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
270 evt & OHCI1394_selfIDComplete ? " selfID" : "",
271 evt & OHCI1394_RQPkt ? " AR_req" : "",
272 evt & OHCI1394_RSPkt ? " AR_resp" : "",
273 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
274 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
275 evt & OHCI1394_isochRx ? " IR" : "",
276 evt & OHCI1394_isochTx ? " IT" : "",
277 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
278 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
279 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
280 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
281 evt & OHCI1394_busReset ? " busReset" : "",
282 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
283 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
284 OHCI1394_respTxComplete | OHCI1394_isochRx |
285 OHCI1394_isochTx | OHCI1394_postedWriteErr |
286 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
287 OHCI1394_regAccessFail | OHCI1394_busReset)
288 ? " ?" : "");
289 }
290
291 static const char *speed[] = {
292 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
293 };
294 static const char *power[] = {
295 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
296 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
297 };
298 static const char port[] = { '.', '-', 'p', 'c', };
299
300 static char _p(u32 *s, int shift)
301 {
302 return port[*s >> shift & 3];
303 }
304
305 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
306 {
307 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
308 return;
309
310 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
311 self_id_count, generation, node_id);
312
313 for (; self_id_count--; ++s)
314 if ((*s & 1 << 23) == 0)
315 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
316 "%s gc=%d %s %s%s%s\n",
317 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
318 speed[*s >> 14 & 3], *s >> 16 & 63,
319 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
320 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
321 else
322 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
323 *s, *s >> 24 & 63,
324 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
325 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
326 }
327
328 static const char *evts[] = {
329 [0x00] = "evt_no_status", [0x01] = "-reserved-",
330 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
331 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
332 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
333 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
334 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
335 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
336 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
337 [0x10] = "-reserved-", [0x11] = "ack_complete",
338 [0x12] = "ack_pending ", [0x13] = "-reserved-",
339 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
340 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
341 [0x18] = "-reserved-", [0x19] = "-reserved-",
342 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
343 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
344 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
345 [0x20] = "pending/cancelled",
346 };
347 static const char *tcodes[] = {
348 [0x0] = "QW req", [0x1] = "BW req",
349 [0x2] = "W resp", [0x3] = "-reserved-",
350 [0x4] = "QR req", [0x5] = "BR req",
351 [0x6] = "QR resp", [0x7] = "BR resp",
352 [0x8] = "cycle start", [0x9] = "Lk req",
353 [0xa] = "async stream packet", [0xb] = "Lk resp",
354 [0xc] = "-reserved-", [0xd] = "-reserved-",
355 [0xe] = "link internal", [0xf] = "-reserved-",
356 };
357 static const char *phys[] = {
358 [0x0] = "phy config packet", [0x1] = "link-on packet",
359 [0x2] = "self-id packet", [0x3] = "-reserved-",
360 };
361
362 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
363 {
364 int tcode = header[0] >> 4 & 0xf;
365 char specific[12];
366
367 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
368 return;
369
370 if (unlikely(evt >= ARRAY_SIZE(evts)))
371 evt = 0x1f;
372
373 if (evt == OHCI1394_evt_bus_reset) {
374 fw_notify("A%c evt_bus_reset, generation %d\n",
375 dir, (header[2] >> 16) & 0xff);
376 return;
377 }
378
379 if (header[0] == ~header[1]) {
380 fw_notify("A%c %s, %s, %08x\n",
381 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
382 return;
383 }
384
385 switch (tcode) {
386 case 0x0: case 0x6: case 0x8:
387 snprintf(specific, sizeof(specific), " = %08x",
388 be32_to_cpu((__force __be32)header[3]));
389 break;
390 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
391 snprintf(specific, sizeof(specific), " %x,%x",
392 header[3] >> 16, header[3] & 0xffff);
393 break;
394 default:
395 specific[0] = '\0';
396 }
397
398 switch (tcode) {
399 case 0xe: case 0xa:
400 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
401 break;
402 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
403 fw_notify("A%c spd %x tl %02x, "
404 "%04x -> %04x, %s, "
405 "%s, %04x%08x%s\n",
406 dir, speed, header[0] >> 10 & 0x3f,
407 header[1] >> 16, header[0] >> 16, evts[evt],
408 tcodes[tcode], header[1] & 0xffff, header[2], specific);
409 break;
410 default:
411 fw_notify("A%c spd %x tl %02x, "
412 "%04x -> %04x, %s, "
413 "%s%s\n",
414 dir, speed, header[0] >> 10 & 0x3f,
415 header[1] >> 16, header[0] >> 16, evts[evt],
416 tcodes[tcode], specific);
417 }
418 }
419
420 #else
421
422 #define log_irqs(evt)
423 #define log_selfids(node_id, generation, self_id_count, sid)
424 #define log_ar_at_event(dir, speed, header, evt)
425
426 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
427
428 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
429 {
430 writel(data, ohci->registers + offset);
431 }
432
433 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
434 {
435 return readl(ohci->registers + offset);
436 }
437
438 static inline void flush_writes(const struct fw_ohci *ohci)
439 {
440 /* Do a dummy read to flush writes. */
441 reg_read(ohci, OHCI1394_Version);
442 }
443
444 static int
445 ohci_update_phy_reg(struct fw_card *card, int addr,
446 int clear_bits, int set_bits)
447 {
448 struct fw_ohci *ohci = fw_ohci(card);
449 u32 val, old;
450
451 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
452 flush_writes(ohci);
453 msleep(2);
454 val = reg_read(ohci, OHCI1394_PhyControl);
455 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
456 fw_error("failed to set phy reg bits.\n");
457 return -EBUSY;
458 }
459
460 old = OHCI1394_PhyControl_ReadData(val);
461 old = (old & ~clear_bits) | set_bits;
462 reg_write(ohci, OHCI1394_PhyControl,
463 OHCI1394_PhyControl_Write(addr, old));
464
465 return 0;
466 }
467
468 static int ar_context_add_page(struct ar_context *ctx)
469 {
470 struct device *dev = ctx->ohci->card.device;
471 struct ar_buffer *ab;
472 dma_addr_t uninitialized_var(ab_bus);
473 size_t offset;
474
475 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
476 if (ab == NULL)
477 return -ENOMEM;
478
479 ab->next = NULL;
480 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
481 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
482 DESCRIPTOR_STATUS |
483 DESCRIPTOR_BRANCH_ALWAYS);
484 offset = offsetof(struct ar_buffer, data);
485 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
486 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
487 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
488 ab->descriptor.branch_address = 0;
489
490 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
491 ctx->last_buffer->next = ab;
492 ctx->last_buffer = ab;
493
494 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
495 flush_writes(ctx->ohci);
496
497 return 0;
498 }
499
500 static void ar_context_release(struct ar_context *ctx)
501 {
502 struct ar_buffer *ab, *ab_next;
503 size_t offset;
504 dma_addr_t ab_bus;
505
506 for (ab = ctx->current_buffer; ab; ab = ab_next) {
507 ab_next = ab->next;
508 offset = offsetof(struct ar_buffer, data);
509 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
510 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
511 ab, ab_bus);
512 }
513 }
514
515 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
516 #define cond_le32_to_cpu(v) \
517 (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
518 #else
519 #define cond_le32_to_cpu(v) le32_to_cpu(v)
520 #endif
521
522 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
523 {
524 struct fw_ohci *ohci = ctx->ohci;
525 struct fw_packet p;
526 u32 status, length, tcode;
527 int evt;
528
529 p.header[0] = cond_le32_to_cpu(buffer[0]);
530 p.header[1] = cond_le32_to_cpu(buffer[1]);
531 p.header[2] = cond_le32_to_cpu(buffer[2]);
532
533 tcode = (p.header[0] >> 4) & 0x0f;
534 switch (tcode) {
535 case TCODE_WRITE_QUADLET_REQUEST:
536 case TCODE_READ_QUADLET_RESPONSE:
537 p.header[3] = (__force __u32) buffer[3];
538 p.header_length = 16;
539 p.payload_length = 0;
540 break;
541
542 case TCODE_READ_BLOCK_REQUEST :
543 p.header[3] = cond_le32_to_cpu(buffer[3]);
544 p.header_length = 16;
545 p.payload_length = 0;
546 break;
547
548 case TCODE_WRITE_BLOCK_REQUEST:
549 case TCODE_READ_BLOCK_RESPONSE:
550 case TCODE_LOCK_REQUEST:
551 case TCODE_LOCK_RESPONSE:
552 p.header[3] = cond_le32_to_cpu(buffer[3]);
553 p.header_length = 16;
554 p.payload_length = p.header[3] >> 16;
555 break;
556
557 case TCODE_WRITE_RESPONSE:
558 case TCODE_READ_QUADLET_REQUEST:
559 case OHCI_TCODE_PHY_PACKET:
560 p.header_length = 12;
561 p.payload_length = 0;
562 break;
563
564 default:
565 /* FIXME: Stop context, discard everything, and restart? */
566 p.header_length = 0;
567 p.payload_length = 0;
568 }
569
570 p.payload = (void *) buffer + p.header_length;
571
572 /* FIXME: What to do about evt_* errors? */
573 length = (p.header_length + p.payload_length + 3) / 4;
574 status = cond_le32_to_cpu(buffer[length]);
575 evt = (status >> 16) & 0x1f;
576
577 p.ack = evt - 16;
578 p.speed = (status >> 21) & 0x7;
579 p.timestamp = status & 0xffff;
580 p.generation = ohci->request_generation;
581
582 log_ar_at_event('R', p.speed, p.header, evt);
583
584 /*
585 * The OHCI bus reset handler synthesizes a phy packet with
586 * the new generation number when a bus reset happens (see
587 * section 8.4.2.3). This helps us determine when a request
588 * was received and make sure we send the response in the same
589 * generation. We only need this for requests; for responses
590 * we use the unique tlabel for finding the matching
591 * request.
592 *
593 * Alas some chips sometimes emit bus reset packets with a
594 * wrong generation. We set the correct generation for these
595 * at a slightly incorrect time (in bus_reset_tasklet).
596 */
597 if (evt == OHCI1394_evt_bus_reset) {
598 if (!ohci->bus_reset_packet_quirk)
599 ohci->request_generation = (p.header[2] >> 16) & 0xff;
600 } else if (ctx == &ohci->ar_request_ctx) {
601 fw_core_handle_request(&ohci->card, &p);
602 } else {
603 fw_core_handle_response(&ohci->card, &p);
604 }
605
606 return buffer + length + 1;
607 }
608
609 static void ar_context_tasklet(unsigned long data)
610 {
611 struct ar_context *ctx = (struct ar_context *)data;
612 struct fw_ohci *ohci = ctx->ohci;
613 struct ar_buffer *ab;
614 struct descriptor *d;
615 void *buffer, *end;
616
617 ab = ctx->current_buffer;
618 d = &ab->descriptor;
619
620 if (d->res_count == 0) {
621 size_t size, rest, offset;
622 dma_addr_t start_bus;
623 void *start;
624
625 /*
626 * This descriptor is finished and we may have a
627 * packet split across this and the next buffer. We
628 * reuse the page for reassembling the split packet.
629 */
630
631 offset = offsetof(struct ar_buffer, data);
632 start = buffer = ab;
633 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
634
635 ab = ab->next;
636 d = &ab->descriptor;
637 size = buffer + PAGE_SIZE - ctx->pointer;
638 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
639 memmove(buffer, ctx->pointer, size);
640 memcpy(buffer + size, ab->data, rest);
641 ctx->current_buffer = ab;
642 ctx->pointer = (void *) ab->data + rest;
643 end = buffer + size + rest;
644
645 while (buffer < end)
646 buffer = handle_ar_packet(ctx, buffer);
647
648 dma_free_coherent(ohci->card.device, PAGE_SIZE,
649 start, start_bus);
650 ar_context_add_page(ctx);
651 } else {
652 buffer = ctx->pointer;
653 ctx->pointer = end =
654 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
655
656 while (buffer < end)
657 buffer = handle_ar_packet(ctx, buffer);
658 }
659 }
660
661 static int
662 ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
663 {
664 struct ar_buffer ab;
665
666 ctx->regs = regs;
667 ctx->ohci = ohci;
668 ctx->last_buffer = &ab;
669 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
670
671 ar_context_add_page(ctx);
672 ar_context_add_page(ctx);
673 ctx->current_buffer = ab.next;
674 ctx->pointer = ctx->current_buffer->data;
675
676 return 0;
677 }
678
679 static void ar_context_run(struct ar_context *ctx)
680 {
681 struct ar_buffer *ab = ctx->current_buffer;
682 dma_addr_t ab_bus;
683 size_t offset;
684
685 offset = offsetof(struct ar_buffer, data);
686 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
687
688 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
689 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
690 flush_writes(ctx->ohci);
691 }
692
693 static struct descriptor *
694 find_branch_descriptor(struct descriptor *d, int z)
695 {
696 int b, key;
697
698 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
699 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
700
701 /* figure out which descriptor the branch address goes in */
702 if (z == 2 && (b == 3 || key == 2))
703 return d;
704 else
705 return d + z - 1;
706 }
707
708 static void context_tasklet(unsigned long data)
709 {
710 struct context *ctx = (struct context *) data;
711 struct descriptor *d, *last;
712 u32 address;
713 int z;
714 struct descriptor_buffer *desc;
715
716 desc = list_entry(ctx->buffer_list.next,
717 struct descriptor_buffer, list);
718 last = ctx->last;
719 while (last->branch_address != 0) {
720 struct descriptor_buffer *old_desc = desc;
721 address = le32_to_cpu(last->branch_address);
722 z = address & 0xf;
723 address &= ~0xf;
724
725 /* If the branch address points to a buffer outside of the
726 * current buffer, advance to the next buffer. */
727 if (address < desc->buffer_bus ||
728 address >= desc->buffer_bus + desc->used)
729 desc = list_entry(desc->list.next,
730 struct descriptor_buffer, list);
731 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
732 last = find_branch_descriptor(d, z);
733
734 if (!ctx->callback(ctx, d, last))
735 break;
736
737 if (old_desc != desc) {
738 /* If we've advanced to the next buffer, move the
739 * previous buffer to the free list. */
740 unsigned long flags;
741 old_desc->used = 0;
742 spin_lock_irqsave(&ctx->ohci->lock, flags);
743 list_move_tail(&old_desc->list, &ctx->buffer_list);
744 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
745 }
746 ctx->last = last;
747 }
748 }
749
750 /*
751 * Allocate a new buffer and add it to the list of free buffers for this
752 * context. Must be called with ohci->lock held.
753 */
754 static int
755 context_add_buffer(struct context *ctx)
756 {
757 struct descriptor_buffer *desc;
758 dma_addr_t uninitialized_var(bus_addr);
759 int offset;
760
761 /*
762 * 16MB of descriptors should be far more than enough for any DMA
763 * program. This will catch run-away userspace or DoS attacks.
764 */
765 if (ctx->total_allocation >= 16*1024*1024)
766 return -ENOMEM;
767
768 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
769 &bus_addr, GFP_ATOMIC);
770 if (!desc)
771 return -ENOMEM;
772
773 offset = (void *)&desc->buffer - (void *)desc;
774 desc->buffer_size = PAGE_SIZE - offset;
775 desc->buffer_bus = bus_addr + offset;
776 desc->used = 0;
777
778 list_add_tail(&desc->list, &ctx->buffer_list);
779 ctx->total_allocation += PAGE_SIZE;
780
781 return 0;
782 }
783
784 static int
785 context_init(struct context *ctx, struct fw_ohci *ohci,
786 u32 regs, descriptor_callback_t callback)
787 {
788 ctx->ohci = ohci;
789 ctx->regs = regs;
790 ctx->total_allocation = 0;
791
792 INIT_LIST_HEAD(&ctx->buffer_list);
793 if (context_add_buffer(ctx) < 0)
794 return -ENOMEM;
795
796 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
797 struct descriptor_buffer, list);
798
799 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
800 ctx->callback = callback;
801
802 /*
803 * We put a dummy descriptor in the buffer that has a NULL
804 * branch address and looks like it's been sent. That way we
805 * have a descriptor to append DMA programs to.
806 */
807 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
808 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
809 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
810 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
811 ctx->last = ctx->buffer_tail->buffer;
812 ctx->prev = ctx->buffer_tail->buffer;
813
814 return 0;
815 }
816
817 static void
818 context_release(struct context *ctx)
819 {
820 struct fw_card *card = &ctx->ohci->card;
821 struct descriptor_buffer *desc, *tmp;
822
823 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
824 dma_free_coherent(card->device, PAGE_SIZE, desc,
825 desc->buffer_bus -
826 ((void *)&desc->buffer - (void *)desc));
827 }
828
829 /* Must be called with ohci->lock held */
830 static struct descriptor *
831 context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
832 {
833 struct descriptor *d = NULL;
834 struct descriptor_buffer *desc = ctx->buffer_tail;
835
836 if (z * sizeof(*d) > desc->buffer_size)
837 return NULL;
838
839 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
840 /* No room for the descriptor in this buffer, so advance to the
841 * next one. */
842
843 if (desc->list.next == &ctx->buffer_list) {
844 /* If there is no free buffer next in the list,
845 * allocate one. */
846 if (context_add_buffer(ctx) < 0)
847 return NULL;
848 }
849 desc = list_entry(desc->list.next,
850 struct descriptor_buffer, list);
851 ctx->buffer_tail = desc;
852 }
853
854 d = desc->buffer + desc->used / sizeof(*d);
855 memset(d, 0, z * sizeof(*d));
856 *d_bus = desc->buffer_bus + desc->used;
857
858 return d;
859 }
860
861 static void context_run(struct context *ctx, u32 extra)
862 {
863 struct fw_ohci *ohci = ctx->ohci;
864
865 reg_write(ohci, COMMAND_PTR(ctx->regs),
866 le32_to_cpu(ctx->last->branch_address));
867 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
868 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
869 flush_writes(ohci);
870 }
871
872 static void context_append(struct context *ctx,
873 struct descriptor *d, int z, int extra)
874 {
875 dma_addr_t d_bus;
876 struct descriptor_buffer *desc = ctx->buffer_tail;
877
878 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
879
880 desc->used += (z + extra) * sizeof(*d);
881 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
882 ctx->prev = find_branch_descriptor(d, z);
883
884 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
885 flush_writes(ctx->ohci);
886 }
887
888 static void context_stop(struct context *ctx)
889 {
890 u32 reg;
891 int i;
892
893 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
894 flush_writes(ctx->ohci);
895
896 for (i = 0; i < 10; i++) {
897 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
898 if ((reg & CONTEXT_ACTIVE) == 0)
899 break;
900
901 fw_notify("context_stop: still active (0x%08x)\n", reg);
902 mdelay(1);
903 }
904 }
905
906 struct driver_data {
907 struct fw_packet *packet;
908 };
909
910 /*
911 * This function apppends a packet to the DMA queue for transmission.
912 * Must always be called with the ochi->lock held to ensure proper
913 * generation handling and locking around packet queue manipulation.
914 */
915 static int
916 at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
917 {
918 struct fw_ohci *ohci = ctx->ohci;
919 dma_addr_t d_bus, uninitialized_var(payload_bus);
920 struct driver_data *driver_data;
921 struct descriptor *d, *last;
922 __le32 *header;
923 int z, tcode;
924 u32 reg;
925
926 d = context_get_descriptors(ctx, 4, &d_bus);
927 if (d == NULL) {
928 packet->ack = RCODE_SEND_ERROR;
929 return -1;
930 }
931
932 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
933 d[0].res_count = cpu_to_le16(packet->timestamp);
934
935 /*
936 * The DMA format for asyncronous link packets is different
937 * from the IEEE1394 layout, so shift the fields around
938 * accordingly. If header_length is 8, it's a PHY packet, to
939 * which we need to prepend an extra quadlet.
940 */
941
942 header = (__le32 *) &d[1];
943 if (packet->header_length > 8) {
944 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
945 (packet->speed << 16));
946 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
947 (packet->header[0] & 0xffff0000));
948 header[2] = cpu_to_le32(packet->header[2]);
949
950 tcode = (packet->header[0] >> 4) & 0x0f;
951 if (TCODE_IS_BLOCK_PACKET(tcode))
952 header[3] = cpu_to_le32(packet->header[3]);
953 else
954 header[3] = (__force __le32) packet->header[3];
955
956 d[0].req_count = cpu_to_le16(packet->header_length);
957 } else {
958 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
959 (packet->speed << 16));
960 header[1] = cpu_to_le32(packet->header[0]);
961 header[2] = cpu_to_le32(packet->header[1]);
962 d[0].req_count = cpu_to_le16(12);
963 }
964
965 driver_data = (struct driver_data *) &d[3];
966 driver_data->packet = packet;
967 packet->driver_data = driver_data;
968
969 if (packet->payload_length > 0) {
970 payload_bus =
971 dma_map_single(ohci->card.device, packet->payload,
972 packet->payload_length, DMA_TO_DEVICE);
973 if (dma_mapping_error(ohci->card.device, payload_bus)) {
974 packet->ack = RCODE_SEND_ERROR;
975 return -1;
976 }
977
978 d[2].req_count = cpu_to_le16(packet->payload_length);
979 d[2].data_address = cpu_to_le32(payload_bus);
980 last = &d[2];
981 z = 3;
982 } else {
983 last = &d[0];
984 z = 2;
985 }
986
987 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
988 DESCRIPTOR_IRQ_ALWAYS |
989 DESCRIPTOR_BRANCH_ALWAYS);
990
991 /*
992 * If the controller and packet generations don't match, we need to
993 * bail out and try again. If IntEvent.busReset is set, the AT context
994 * is halted, so appending to the context and trying to run it is
995 * futile. Most controllers do the right thing and just flush the AT
996 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
997 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
998 * up stalling out. So we just bail out in software and try again
999 * later, and everyone is happy.
1000 * FIXME: Document how the locking works.
1001 */
1002 if (ohci->generation != packet->generation ||
1003 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1004 if (packet->payload_length > 0)
1005 dma_unmap_single(ohci->card.device, payload_bus,
1006 packet->payload_length, DMA_TO_DEVICE);
1007 packet->ack = RCODE_GENERATION;
1008 return -1;
1009 }
1010
1011 context_append(ctx, d, z, 4 - z);
1012
1013 /* If the context isn't already running, start it up. */
1014 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1015 if ((reg & CONTEXT_RUN) == 0)
1016 context_run(ctx, 0);
1017
1018 return 0;
1019 }
1020
1021 static int handle_at_packet(struct context *context,
1022 struct descriptor *d,
1023 struct descriptor *last)
1024 {
1025 struct driver_data *driver_data;
1026 struct fw_packet *packet;
1027 struct fw_ohci *ohci = context->ohci;
1028 dma_addr_t payload_bus;
1029 int evt;
1030
1031 if (last->transfer_status == 0)
1032 /* This descriptor isn't done yet, stop iteration. */
1033 return 0;
1034
1035 driver_data = (struct driver_data *) &d[3];
1036 packet = driver_data->packet;
1037 if (packet == NULL)
1038 /* This packet was cancelled, just continue. */
1039 return 1;
1040
1041 payload_bus = le32_to_cpu(last->data_address);
1042 if (payload_bus != 0)
1043 dma_unmap_single(ohci->card.device, payload_bus,
1044 packet->payload_length, DMA_TO_DEVICE);
1045
1046 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1047 packet->timestamp = le16_to_cpu(last->res_count);
1048
1049 log_ar_at_event('T', packet->speed, packet->header, evt);
1050
1051 switch (evt) {
1052 case OHCI1394_evt_timeout:
1053 /* Async response transmit timed out. */
1054 packet->ack = RCODE_CANCELLED;
1055 break;
1056
1057 case OHCI1394_evt_flushed:
1058 /*
1059 * The packet was flushed should give same error as
1060 * when we try to use a stale generation count.
1061 */
1062 packet->ack = RCODE_GENERATION;
1063 break;
1064
1065 case OHCI1394_evt_missing_ack:
1066 /*
1067 * Using a valid (current) generation count, but the
1068 * node is not on the bus or not sending acks.
1069 */
1070 packet->ack = RCODE_NO_ACK;
1071 break;
1072
1073 case ACK_COMPLETE + 0x10:
1074 case ACK_PENDING + 0x10:
1075 case ACK_BUSY_X + 0x10:
1076 case ACK_BUSY_A + 0x10:
1077 case ACK_BUSY_B + 0x10:
1078 case ACK_DATA_ERROR + 0x10:
1079 case ACK_TYPE_ERROR + 0x10:
1080 packet->ack = evt - 0x10;
1081 break;
1082
1083 default:
1084 packet->ack = RCODE_SEND_ERROR;
1085 break;
1086 }
1087
1088 packet->callback(packet, &ohci->card, packet->ack);
1089
1090 return 1;
1091 }
1092
1093 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1094 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1095 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1096 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1097 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1098
1099 static void
1100 handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
1101 {
1102 struct fw_packet response;
1103 int tcode, length, i;
1104
1105 tcode = HEADER_GET_TCODE(packet->header[0]);
1106 if (TCODE_IS_BLOCK_PACKET(tcode))
1107 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1108 else
1109 length = 4;
1110
1111 i = csr - CSR_CONFIG_ROM;
1112 if (i + length > CONFIG_ROM_SIZE) {
1113 fw_fill_response(&response, packet->header,
1114 RCODE_ADDRESS_ERROR, NULL, 0);
1115 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1116 fw_fill_response(&response, packet->header,
1117 RCODE_TYPE_ERROR, NULL, 0);
1118 } else {
1119 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1120 (void *) ohci->config_rom + i, length);
1121 }
1122
1123 fw_core_handle_response(&ohci->card, &response);
1124 }
1125
1126 static void
1127 handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
1128 {
1129 struct fw_packet response;
1130 int tcode, length, ext_tcode, sel;
1131 __be32 *payload, lock_old;
1132 u32 lock_arg, lock_data;
1133
1134 tcode = HEADER_GET_TCODE(packet->header[0]);
1135 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1136 payload = packet->payload;
1137 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1138
1139 if (tcode == TCODE_LOCK_REQUEST &&
1140 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1141 lock_arg = be32_to_cpu(payload[0]);
1142 lock_data = be32_to_cpu(payload[1]);
1143 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1144 lock_arg = 0;
1145 lock_data = 0;
1146 } else {
1147 fw_fill_response(&response, packet->header,
1148 RCODE_TYPE_ERROR, NULL, 0);
1149 goto out;
1150 }
1151
1152 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1153 reg_write(ohci, OHCI1394_CSRData, lock_data);
1154 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1155 reg_write(ohci, OHCI1394_CSRControl, sel);
1156
1157 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1158 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1159 else
1160 fw_notify("swap not done yet\n");
1161
1162 fw_fill_response(&response, packet->header,
1163 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1164 out:
1165 fw_core_handle_response(&ohci->card, &response);
1166 }
1167
1168 static void
1169 handle_local_request(struct context *ctx, struct fw_packet *packet)
1170 {
1171 u64 offset;
1172 u32 csr;
1173
1174 if (ctx == &ctx->ohci->at_request_ctx) {
1175 packet->ack = ACK_PENDING;
1176 packet->callback(packet, &ctx->ohci->card, packet->ack);
1177 }
1178
1179 offset =
1180 ((unsigned long long)
1181 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1182 packet->header[2];
1183 csr = offset - CSR_REGISTER_BASE;
1184
1185 /* Handle config rom reads. */
1186 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1187 handle_local_rom(ctx->ohci, packet, csr);
1188 else switch (csr) {
1189 case CSR_BUS_MANAGER_ID:
1190 case CSR_BANDWIDTH_AVAILABLE:
1191 case CSR_CHANNELS_AVAILABLE_HI:
1192 case CSR_CHANNELS_AVAILABLE_LO:
1193 handle_local_lock(ctx->ohci, packet, csr);
1194 break;
1195 default:
1196 if (ctx == &ctx->ohci->at_request_ctx)
1197 fw_core_handle_request(&ctx->ohci->card, packet);
1198 else
1199 fw_core_handle_response(&ctx->ohci->card, packet);
1200 break;
1201 }
1202
1203 if (ctx == &ctx->ohci->at_response_ctx) {
1204 packet->ack = ACK_COMPLETE;
1205 packet->callback(packet, &ctx->ohci->card, packet->ack);
1206 }
1207 }
1208
1209 static void
1210 at_context_transmit(struct context *ctx, struct fw_packet *packet)
1211 {
1212 unsigned long flags;
1213 int retval;
1214
1215 spin_lock_irqsave(&ctx->ohci->lock, flags);
1216
1217 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1218 ctx->ohci->generation == packet->generation) {
1219 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1220 handle_local_request(ctx, packet);
1221 return;
1222 }
1223
1224 retval = at_context_queue_packet(ctx, packet);
1225 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1226
1227 if (retval < 0)
1228 packet->callback(packet, &ctx->ohci->card, packet->ack);
1229
1230 }
1231
1232 static void bus_reset_tasklet(unsigned long data)
1233 {
1234 struct fw_ohci *ohci = (struct fw_ohci *)data;
1235 int self_id_count, i, j, reg;
1236 int generation, new_generation;
1237 unsigned long flags;
1238 void *free_rom = NULL;
1239 dma_addr_t free_rom_bus = 0;
1240
1241 reg = reg_read(ohci, OHCI1394_NodeID);
1242 if (!(reg & OHCI1394_NodeID_idValid)) {
1243 fw_notify("node ID not valid, new bus reset in progress\n");
1244 return;
1245 }
1246 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1247 fw_notify("malconfigured bus\n");
1248 return;
1249 }
1250 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1251 OHCI1394_NodeID_nodeNumber);
1252
1253 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1254 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1255 fw_notify("inconsistent self IDs\n");
1256 return;
1257 }
1258 /*
1259 * The count in the SelfIDCount register is the number of
1260 * bytes in the self ID receive buffer. Since we also receive
1261 * the inverted quadlets and a header quadlet, we shift one
1262 * bit extra to get the actual number of self IDs.
1263 */
1264 self_id_count = (reg >> 3) & 0x3ff;
1265 if (self_id_count == 0) {
1266 fw_notify("inconsistent self IDs\n");
1267 return;
1268 }
1269 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1270 rmb();
1271
1272 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1273 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1274 fw_notify("inconsistent self IDs\n");
1275 return;
1276 }
1277 ohci->self_id_buffer[j] =
1278 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1279 }
1280 rmb();
1281
1282 /*
1283 * Check the consistency of the self IDs we just read. The
1284 * problem we face is that a new bus reset can start while we
1285 * read out the self IDs from the DMA buffer. If this happens,
1286 * the DMA buffer will be overwritten with new self IDs and we
1287 * will read out inconsistent data. The OHCI specification
1288 * (section 11.2) recommends a technique similar to
1289 * linux/seqlock.h, where we remember the generation of the
1290 * self IDs in the buffer before reading them out and compare
1291 * it to the current generation after reading them out. If
1292 * the two generations match we know we have a consistent set
1293 * of self IDs.
1294 */
1295
1296 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1297 if (new_generation != generation) {
1298 fw_notify("recursive bus reset detected, "
1299 "discarding self ids\n");
1300 return;
1301 }
1302
1303 /* FIXME: Document how the locking works. */
1304 spin_lock_irqsave(&ohci->lock, flags);
1305
1306 ohci->generation = generation;
1307 context_stop(&ohci->at_request_ctx);
1308 context_stop(&ohci->at_response_ctx);
1309 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1310
1311 if (ohci->bus_reset_packet_quirk)
1312 ohci->request_generation = generation;
1313
1314 /*
1315 * This next bit is unrelated to the AT context stuff but we
1316 * have to do it under the spinlock also. If a new config rom
1317 * was set up before this reset, the old one is now no longer
1318 * in use and we can free it. Update the config rom pointers
1319 * to point to the current config rom and clear the
1320 * next_config_rom pointer so a new udpate can take place.
1321 */
1322
1323 if (ohci->next_config_rom != NULL) {
1324 if (ohci->next_config_rom != ohci->config_rom) {
1325 free_rom = ohci->config_rom;
1326 free_rom_bus = ohci->config_rom_bus;
1327 }
1328 ohci->config_rom = ohci->next_config_rom;
1329 ohci->config_rom_bus = ohci->next_config_rom_bus;
1330 ohci->next_config_rom = NULL;
1331
1332 /*
1333 * Restore config_rom image and manually update
1334 * config_rom registers. Writing the header quadlet
1335 * will indicate that the config rom is ready, so we
1336 * do that last.
1337 */
1338 reg_write(ohci, OHCI1394_BusOptions,
1339 be32_to_cpu(ohci->config_rom[2]));
1340 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1341 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1342 }
1343
1344 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1345 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1346 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1347 #endif
1348
1349 spin_unlock_irqrestore(&ohci->lock, flags);
1350
1351 if (free_rom)
1352 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1353 free_rom, free_rom_bus);
1354
1355 log_selfids(ohci->node_id, generation,
1356 self_id_count, ohci->self_id_buffer);
1357
1358 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1359 self_id_count, ohci->self_id_buffer);
1360 }
1361
1362 static irqreturn_t irq_handler(int irq, void *data)
1363 {
1364 struct fw_ohci *ohci = data;
1365 u32 event, iso_event, cycle_time;
1366 int i;
1367
1368 event = reg_read(ohci, OHCI1394_IntEventClear);
1369
1370 if (!event || !~event)
1371 return IRQ_NONE;
1372
1373 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1374 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1375 log_irqs(event);
1376
1377 if (event & OHCI1394_selfIDComplete)
1378 tasklet_schedule(&ohci->bus_reset_tasklet);
1379
1380 if (event & OHCI1394_RQPkt)
1381 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1382
1383 if (event & OHCI1394_RSPkt)
1384 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1385
1386 if (event & OHCI1394_reqTxComplete)
1387 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1388
1389 if (event & OHCI1394_respTxComplete)
1390 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1391
1392 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1393 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1394
1395 while (iso_event) {
1396 i = ffs(iso_event) - 1;
1397 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1398 iso_event &= ~(1 << i);
1399 }
1400
1401 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1402 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1403
1404 while (iso_event) {
1405 i = ffs(iso_event) - 1;
1406 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1407 iso_event &= ~(1 << i);
1408 }
1409
1410 if (unlikely(event & OHCI1394_regAccessFail))
1411 fw_error("Register access failure - "
1412 "please notify linux1394-devel@lists.sf.net\n");
1413
1414 if (unlikely(event & OHCI1394_postedWriteErr))
1415 fw_error("PCI posted write error\n");
1416
1417 if (unlikely(event & OHCI1394_cycleTooLong)) {
1418 if (printk_ratelimit())
1419 fw_notify("isochronous cycle too long\n");
1420 reg_write(ohci, OHCI1394_LinkControlSet,
1421 OHCI1394_LinkControl_cycleMaster);
1422 }
1423
1424 if (event & OHCI1394_cycle64Seconds) {
1425 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1426 if ((cycle_time & 0x80000000) == 0)
1427 ohci->bus_seconds++;
1428 }
1429
1430 return IRQ_HANDLED;
1431 }
1432
1433 static int software_reset(struct fw_ohci *ohci)
1434 {
1435 int i;
1436
1437 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1438
1439 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1440 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1441 OHCI1394_HCControl_softReset) == 0)
1442 return 0;
1443 msleep(1);
1444 }
1445
1446 return -EBUSY;
1447 }
1448
1449 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1450 {
1451 struct fw_ohci *ohci = fw_ohci(card);
1452 struct pci_dev *dev = to_pci_dev(card->device);
1453 u32 lps;
1454 int i;
1455
1456 if (software_reset(ohci)) {
1457 fw_error("Failed to reset ohci card.\n");
1458 return -EBUSY;
1459 }
1460
1461 /*
1462 * Now enable LPS, which we need in order to start accessing
1463 * most of the registers. In fact, on some cards (ALI M5251),
1464 * accessing registers in the SClk domain without LPS enabled
1465 * will lock up the machine. Wait 50msec to make sure we have
1466 * full link enabled. However, with some cards (well, at least
1467 * a JMicron PCIe card), we have to try again sometimes.
1468 */
1469 reg_write(ohci, OHCI1394_HCControlSet,
1470 OHCI1394_HCControl_LPS |
1471 OHCI1394_HCControl_postedWriteEnable);
1472 flush_writes(ohci);
1473
1474 for (lps = 0, i = 0; !lps && i < 3; i++) {
1475 msleep(50);
1476 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1477 OHCI1394_HCControl_LPS;
1478 }
1479
1480 if (!lps) {
1481 fw_error("Failed to set Link Power Status\n");
1482 return -EIO;
1483 }
1484
1485 reg_write(ohci, OHCI1394_HCControlClear,
1486 OHCI1394_HCControl_noByteSwapData);
1487
1488 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1489 reg_write(ohci, OHCI1394_LinkControlClear,
1490 OHCI1394_LinkControl_rcvPhyPkt);
1491 reg_write(ohci, OHCI1394_LinkControlSet,
1492 OHCI1394_LinkControl_rcvSelfID |
1493 OHCI1394_LinkControl_cycleTimerEnable |
1494 OHCI1394_LinkControl_cycleMaster);
1495
1496 reg_write(ohci, OHCI1394_ATRetries,
1497 OHCI1394_MAX_AT_REQ_RETRIES |
1498 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1499 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1500
1501 ar_context_run(&ohci->ar_request_ctx);
1502 ar_context_run(&ohci->ar_response_ctx);
1503
1504 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1505 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1506 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1507 reg_write(ohci, OHCI1394_IntMaskSet,
1508 OHCI1394_selfIDComplete |
1509 OHCI1394_RQPkt | OHCI1394_RSPkt |
1510 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1511 OHCI1394_isochRx | OHCI1394_isochTx |
1512 OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1513 OHCI1394_cycle64Seconds | OHCI1394_regAccessFail |
1514 OHCI1394_masterIntEnable);
1515 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1516 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1517
1518 /* Activate link_on bit and contender bit in our self ID packets.*/
1519 if (ohci_update_phy_reg(card, 4, 0,
1520 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1521 return -EIO;
1522
1523 /*
1524 * When the link is not yet enabled, the atomic config rom
1525 * update mechanism described below in ohci_set_config_rom()
1526 * is not active. We have to update ConfigRomHeader and
1527 * BusOptions manually, and the write to ConfigROMmap takes
1528 * effect immediately. We tie this to the enabling of the
1529 * link, so we have a valid config rom before enabling - the
1530 * OHCI requires that ConfigROMhdr and BusOptions have valid
1531 * values before enabling.
1532 *
1533 * However, when the ConfigROMmap is written, some controllers
1534 * always read back quadlets 0 and 2 from the config rom to
1535 * the ConfigRomHeader and BusOptions registers on bus reset.
1536 * They shouldn't do that in this initial case where the link
1537 * isn't enabled. This means we have to use the same
1538 * workaround here, setting the bus header to 0 and then write
1539 * the right values in the bus reset tasklet.
1540 */
1541
1542 if (config_rom) {
1543 ohci->next_config_rom =
1544 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1545 &ohci->next_config_rom_bus,
1546 GFP_KERNEL);
1547 if (ohci->next_config_rom == NULL)
1548 return -ENOMEM;
1549
1550 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1551 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1552 } else {
1553 /*
1554 * In the suspend case, config_rom is NULL, which
1555 * means that we just reuse the old config rom.
1556 */
1557 ohci->next_config_rom = ohci->config_rom;
1558 ohci->next_config_rom_bus = ohci->config_rom_bus;
1559 }
1560
1561 ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]);
1562 ohci->next_config_rom[0] = 0;
1563 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1564 reg_write(ohci, OHCI1394_BusOptions,
1565 be32_to_cpu(ohci->next_config_rom[2]));
1566 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1567
1568 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1569
1570 if (request_irq(dev->irq, irq_handler,
1571 IRQF_SHARED, ohci_driver_name, ohci)) {
1572 fw_error("Failed to allocate shared interrupt %d.\n",
1573 dev->irq);
1574 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1575 ohci->config_rom, ohci->config_rom_bus);
1576 return -EIO;
1577 }
1578
1579 reg_write(ohci, OHCI1394_HCControlSet,
1580 OHCI1394_HCControl_linkEnable |
1581 OHCI1394_HCControl_BIBimageValid);
1582 flush_writes(ohci);
1583
1584 /*
1585 * We are ready to go, initiate bus reset to finish the
1586 * initialization.
1587 */
1588
1589 fw_core_initiate_bus_reset(&ohci->card, 1);
1590
1591 return 0;
1592 }
1593
1594 static int
1595 ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1596 {
1597 struct fw_ohci *ohci;
1598 unsigned long flags;
1599 int retval = -EBUSY;
1600 __be32 *next_config_rom;
1601 dma_addr_t uninitialized_var(next_config_rom_bus);
1602
1603 ohci = fw_ohci(card);
1604
1605 /*
1606 * When the OHCI controller is enabled, the config rom update
1607 * mechanism is a bit tricky, but easy enough to use. See
1608 * section 5.5.6 in the OHCI specification.
1609 *
1610 * The OHCI controller caches the new config rom address in a
1611 * shadow register (ConfigROMmapNext) and needs a bus reset
1612 * for the changes to take place. When the bus reset is
1613 * detected, the controller loads the new values for the
1614 * ConfigRomHeader and BusOptions registers from the specified
1615 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1616 * shadow register. All automatically and atomically.
1617 *
1618 * Now, there's a twist to this story. The automatic load of
1619 * ConfigRomHeader and BusOptions doesn't honor the
1620 * noByteSwapData bit, so with a be32 config rom, the
1621 * controller will load be32 values in to these registers
1622 * during the atomic update, even on litte endian
1623 * architectures. The workaround we use is to put a 0 in the
1624 * header quadlet; 0 is endian agnostic and means that the
1625 * config rom isn't ready yet. In the bus reset tasklet we
1626 * then set up the real values for the two registers.
1627 *
1628 * We use ohci->lock to avoid racing with the code that sets
1629 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1630 */
1631
1632 next_config_rom =
1633 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1634 &next_config_rom_bus, GFP_KERNEL);
1635 if (next_config_rom == NULL)
1636 return -ENOMEM;
1637
1638 spin_lock_irqsave(&ohci->lock, flags);
1639
1640 if (ohci->next_config_rom == NULL) {
1641 ohci->next_config_rom = next_config_rom;
1642 ohci->next_config_rom_bus = next_config_rom_bus;
1643
1644 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1645 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1646 length * 4);
1647
1648 ohci->next_header = config_rom[0];
1649 ohci->next_config_rom[0] = 0;
1650
1651 reg_write(ohci, OHCI1394_ConfigROMmap,
1652 ohci->next_config_rom_bus);
1653 retval = 0;
1654 }
1655
1656 spin_unlock_irqrestore(&ohci->lock, flags);
1657
1658 /*
1659 * Now initiate a bus reset to have the changes take
1660 * effect. We clean up the old config rom memory and DMA
1661 * mappings in the bus reset tasklet, since the OHCI
1662 * controller could need to access it before the bus reset
1663 * takes effect.
1664 */
1665 if (retval == 0)
1666 fw_core_initiate_bus_reset(&ohci->card, 1);
1667 else
1668 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1669 next_config_rom, next_config_rom_bus);
1670
1671 return retval;
1672 }
1673
1674 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1675 {
1676 struct fw_ohci *ohci = fw_ohci(card);
1677
1678 at_context_transmit(&ohci->at_request_ctx, packet);
1679 }
1680
1681 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1682 {
1683 struct fw_ohci *ohci = fw_ohci(card);
1684
1685 at_context_transmit(&ohci->at_response_ctx, packet);
1686 }
1687
1688 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1689 {
1690 struct fw_ohci *ohci = fw_ohci(card);
1691 struct context *ctx = &ohci->at_request_ctx;
1692 struct driver_data *driver_data = packet->driver_data;
1693 int retval = -ENOENT;
1694
1695 tasklet_disable(&ctx->tasklet);
1696
1697 if (packet->ack != 0)
1698 goto out;
1699
1700 log_ar_at_event('T', packet->speed, packet->header, 0x20);
1701 driver_data->packet = NULL;
1702 packet->ack = RCODE_CANCELLED;
1703 packet->callback(packet, &ohci->card, packet->ack);
1704 retval = 0;
1705
1706 out:
1707 tasklet_enable(&ctx->tasklet);
1708
1709 return retval;
1710 }
1711
1712 static int
1713 ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1714 {
1715 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1716 return 0;
1717 #else
1718 struct fw_ohci *ohci = fw_ohci(card);
1719 unsigned long flags;
1720 int n, retval = 0;
1721
1722 /*
1723 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1724 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1725 */
1726
1727 spin_lock_irqsave(&ohci->lock, flags);
1728
1729 if (ohci->generation != generation) {
1730 retval = -ESTALE;
1731 goto out;
1732 }
1733
1734 /*
1735 * Note, if the node ID contains a non-local bus ID, physical DMA is
1736 * enabled for _all_ nodes on remote buses.
1737 */
1738
1739 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1740 if (n < 32)
1741 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1742 else
1743 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1744
1745 flush_writes(ohci);
1746 out:
1747 spin_unlock_irqrestore(&ohci->lock, flags);
1748 return retval;
1749 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1750 }
1751
1752 static u64
1753 ohci_get_bus_time(struct fw_card *card)
1754 {
1755 struct fw_ohci *ohci = fw_ohci(card);
1756 u32 cycle_time;
1757 u64 bus_time;
1758
1759 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1760 bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
1761
1762 return bus_time;
1763 }
1764
1765 static int handle_ir_dualbuffer_packet(struct context *context,
1766 struct descriptor *d,
1767 struct descriptor *last)
1768 {
1769 struct iso_context *ctx =
1770 container_of(context, struct iso_context, context);
1771 struct db_descriptor *db = (struct db_descriptor *) d;
1772 __le32 *ir_header;
1773 size_t header_length;
1774 void *p, *end;
1775 int i;
1776
1777 if (db->first_res_count != 0 && db->second_res_count != 0) {
1778 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1779 /* This descriptor isn't done yet, stop iteration. */
1780 return 0;
1781 }
1782 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1783 }
1784
1785 header_length = le16_to_cpu(db->first_req_count) -
1786 le16_to_cpu(db->first_res_count);
1787
1788 i = ctx->header_length;
1789 p = db + 1;
1790 end = p + header_length;
1791 while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
1792 /*
1793 * The iso header is byteswapped to little endian by
1794 * the controller, but the remaining header quadlets
1795 * are big endian. We want to present all the headers
1796 * as big endian, so we have to swap the first
1797 * quadlet.
1798 */
1799 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1800 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1801 i += ctx->base.header_size;
1802 ctx->excess_bytes +=
1803 (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1804 p += ctx->base.header_size + 4;
1805 }
1806 ctx->header_length = i;
1807
1808 ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1809 le16_to_cpu(db->second_res_count);
1810
1811 if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1812 ir_header = (__le32 *) (db + 1);
1813 ctx->base.callback(&ctx->base,
1814 le32_to_cpu(ir_header[0]) & 0xffff,
1815 ctx->header_length, ctx->header,
1816 ctx->base.callback_data);
1817 ctx->header_length = 0;
1818 }
1819
1820 return 1;
1821 }
1822
1823 static int handle_ir_packet_per_buffer(struct context *context,
1824 struct descriptor *d,
1825 struct descriptor *last)
1826 {
1827 struct iso_context *ctx =
1828 container_of(context, struct iso_context, context);
1829 struct descriptor *pd;
1830 __le32 *ir_header;
1831 void *p;
1832 int i;
1833
1834 for (pd = d; pd <= last; pd++) {
1835 if (pd->transfer_status)
1836 break;
1837 }
1838 if (pd > last)
1839 /* Descriptor(s) not done yet, stop iteration */
1840 return 0;
1841
1842 i = ctx->header_length;
1843 p = last + 1;
1844
1845 if (ctx->base.header_size > 0 &&
1846 i + ctx->base.header_size <= PAGE_SIZE) {
1847 /*
1848 * The iso header is byteswapped to little endian by
1849 * the controller, but the remaining header quadlets
1850 * are big endian. We want to present all the headers
1851 * as big endian, so we have to swap the first quadlet.
1852 */
1853 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1854 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1855 ctx->header_length += ctx->base.header_size;
1856 }
1857
1858 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1859 ir_header = (__le32 *) p;
1860 ctx->base.callback(&ctx->base,
1861 le32_to_cpu(ir_header[0]) & 0xffff,
1862 ctx->header_length, ctx->header,
1863 ctx->base.callback_data);
1864 ctx->header_length = 0;
1865 }
1866
1867 return 1;
1868 }
1869
1870 static int handle_it_packet(struct context *context,
1871 struct descriptor *d,
1872 struct descriptor *last)
1873 {
1874 struct iso_context *ctx =
1875 container_of(context, struct iso_context, context);
1876
1877 if (last->transfer_status == 0)
1878 /* This descriptor isn't done yet, stop iteration. */
1879 return 0;
1880
1881 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
1882 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1883 0, NULL, ctx->base.callback_data);
1884
1885 return 1;
1886 }
1887
1888 static struct fw_iso_context *
1889 ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
1890 {
1891 struct fw_ohci *ohci = fw_ohci(card);
1892 struct iso_context *ctx, *list;
1893 descriptor_callback_t callback;
1894 u32 *mask, regs;
1895 unsigned long flags;
1896 int index, retval = -ENOMEM;
1897
1898 if (type == FW_ISO_CONTEXT_TRANSMIT) {
1899 mask = &ohci->it_context_mask;
1900 list = ohci->it_context_list;
1901 callback = handle_it_packet;
1902 } else {
1903 mask = &ohci->ir_context_mask;
1904 list = ohci->ir_context_list;
1905 if (ohci->use_dualbuffer)
1906 callback = handle_ir_dualbuffer_packet;
1907 else
1908 callback = handle_ir_packet_per_buffer;
1909 }
1910
1911 spin_lock_irqsave(&ohci->lock, flags);
1912 index = ffs(*mask) - 1;
1913 if (index >= 0)
1914 *mask &= ~(1 << index);
1915 spin_unlock_irqrestore(&ohci->lock, flags);
1916
1917 if (index < 0)
1918 return ERR_PTR(-EBUSY);
1919
1920 if (type == FW_ISO_CONTEXT_TRANSMIT)
1921 regs = OHCI1394_IsoXmitContextBase(index);
1922 else
1923 regs = OHCI1394_IsoRcvContextBase(index);
1924
1925 ctx = &list[index];
1926 memset(ctx, 0, sizeof(*ctx));
1927 ctx->header_length = 0;
1928 ctx->header = (void *) __get_free_page(GFP_KERNEL);
1929 if (ctx->header == NULL)
1930 goto out;
1931
1932 retval = context_init(&ctx->context, ohci, regs, callback);
1933 if (retval < 0)
1934 goto out_with_header;
1935
1936 return &ctx->base;
1937
1938 out_with_header:
1939 free_page((unsigned long)ctx->header);
1940 out:
1941 spin_lock_irqsave(&ohci->lock, flags);
1942 *mask |= 1 << index;
1943 spin_unlock_irqrestore(&ohci->lock, flags);
1944
1945 return ERR_PTR(retval);
1946 }
1947
1948 static int ohci_start_iso(struct fw_iso_context *base,
1949 s32 cycle, u32 sync, u32 tags)
1950 {
1951 struct iso_context *ctx = container_of(base, struct iso_context, base);
1952 struct fw_ohci *ohci = ctx->context.ohci;
1953 u32 control, match;
1954 int index;
1955
1956 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1957 index = ctx - ohci->it_context_list;
1958 match = 0;
1959 if (cycle >= 0)
1960 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1961 (cycle & 0x7fff) << 16;
1962
1963 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1964 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1965 context_run(&ctx->context, match);
1966 } else {
1967 index = ctx - ohci->ir_context_list;
1968 control = IR_CONTEXT_ISOCH_HEADER;
1969 if (ohci->use_dualbuffer)
1970 control |= IR_CONTEXT_DUAL_BUFFER_MODE;
1971 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1972 if (cycle >= 0) {
1973 match |= (cycle & 0x07fff) << 12;
1974 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1975 }
1976
1977 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1978 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
1979 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
1980 context_run(&ctx->context, control);
1981 }
1982
1983 return 0;
1984 }
1985
1986 static int ohci_stop_iso(struct fw_iso_context *base)
1987 {
1988 struct fw_ohci *ohci = fw_ohci(base->card);
1989 struct iso_context *ctx = container_of(base, struct iso_context, base);
1990 int index;
1991
1992 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1993 index = ctx - ohci->it_context_list;
1994 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1995 } else {
1996 index = ctx - ohci->ir_context_list;
1997 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1998 }
1999 flush_writes(ohci);
2000 context_stop(&ctx->context);
2001
2002 return 0;
2003 }
2004
2005 static void ohci_free_iso_context(struct fw_iso_context *base)
2006 {
2007 struct fw_ohci *ohci = fw_ohci(base->card);
2008 struct iso_context *ctx = container_of(base, struct iso_context, base);
2009 unsigned long flags;
2010 int index;
2011
2012 ohci_stop_iso(base);
2013 context_release(&ctx->context);
2014 free_page((unsigned long)ctx->header);
2015
2016 spin_lock_irqsave(&ohci->lock, flags);
2017
2018 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2019 index = ctx - ohci->it_context_list;
2020 ohci->it_context_mask |= 1 << index;
2021 } else {
2022 index = ctx - ohci->ir_context_list;
2023 ohci->ir_context_mask |= 1 << index;
2024 }
2025
2026 spin_unlock_irqrestore(&ohci->lock, flags);
2027 }
2028
2029 static int
2030 ohci_queue_iso_transmit(struct fw_iso_context *base,
2031 struct fw_iso_packet *packet,
2032 struct fw_iso_buffer *buffer,
2033 unsigned long payload)
2034 {
2035 struct iso_context *ctx = container_of(base, struct iso_context, base);
2036 struct descriptor *d, *last, *pd;
2037 struct fw_iso_packet *p;
2038 __le32 *header;
2039 dma_addr_t d_bus, page_bus;
2040 u32 z, header_z, payload_z, irq;
2041 u32 payload_index, payload_end_index, next_page_index;
2042 int page, end_page, i, length, offset;
2043
2044 /*
2045 * FIXME: Cycle lost behavior should be configurable: lose
2046 * packet, retransmit or terminate..
2047 */
2048
2049 p = packet;
2050 payload_index = payload;
2051
2052 if (p->skip)
2053 z = 1;
2054 else
2055 z = 2;
2056 if (p->header_length > 0)
2057 z++;
2058
2059 /* Determine the first page the payload isn't contained in. */
2060 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2061 if (p->payload_length > 0)
2062 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2063 else
2064 payload_z = 0;
2065
2066 z += payload_z;
2067
2068 /* Get header size in number of descriptors. */
2069 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2070
2071 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2072 if (d == NULL)
2073 return -ENOMEM;
2074
2075 if (!p->skip) {
2076 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2077 d[0].req_count = cpu_to_le16(8);
2078
2079 header = (__le32 *) &d[1];
2080 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2081 IT_HEADER_TAG(p->tag) |
2082 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2083 IT_HEADER_CHANNEL(ctx->base.channel) |
2084 IT_HEADER_SPEED(ctx->base.speed));
2085 header[1] =
2086 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2087 p->payload_length));
2088 }
2089
2090 if (p->header_length > 0) {
2091 d[2].req_count = cpu_to_le16(p->header_length);
2092 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2093 memcpy(&d[z], p->header, p->header_length);
2094 }
2095
2096 pd = d + z - payload_z;
2097 payload_end_index = payload_index + p->payload_length;
2098 for (i = 0; i < payload_z; i++) {
2099 page = payload_index >> PAGE_SHIFT;
2100 offset = payload_index & ~PAGE_MASK;
2101 next_page_index = (page + 1) << PAGE_SHIFT;
2102 length =
2103 min(next_page_index, payload_end_index) - payload_index;
2104 pd[i].req_count = cpu_to_le16(length);
2105
2106 page_bus = page_private(buffer->pages[page]);
2107 pd[i].data_address = cpu_to_le32(page_bus + offset);
2108
2109 payload_index += length;
2110 }
2111
2112 if (p->interrupt)
2113 irq = DESCRIPTOR_IRQ_ALWAYS;
2114 else
2115 irq = DESCRIPTOR_NO_IRQ;
2116
2117 last = z == 2 ? d : d + z - 1;
2118 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2119 DESCRIPTOR_STATUS |
2120 DESCRIPTOR_BRANCH_ALWAYS |
2121 irq);
2122
2123 context_append(&ctx->context, d, z, header_z);
2124
2125 return 0;
2126 }
2127
2128 static int
2129 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
2130 struct fw_iso_packet *packet,
2131 struct fw_iso_buffer *buffer,
2132 unsigned long payload)
2133 {
2134 struct iso_context *ctx = container_of(base, struct iso_context, base);
2135 struct db_descriptor *db = NULL;
2136 struct descriptor *d;
2137 struct fw_iso_packet *p;
2138 dma_addr_t d_bus, page_bus;
2139 u32 z, header_z, length, rest;
2140 int page, offset, packet_count, header_size;
2141
2142 /*
2143 * FIXME: Cycle lost behavior should be configurable: lose
2144 * packet, retransmit or terminate..
2145 */
2146
2147 p = packet;
2148 z = 2;
2149
2150 /*
2151 * The OHCI controller puts the status word in the header
2152 * buffer too, so we need 4 extra bytes per packet.
2153 */
2154 packet_count = p->header_length / ctx->base.header_size;
2155 header_size = packet_count * (ctx->base.header_size + 4);
2156
2157 /* Get header size in number of descriptors. */
2158 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2159 page = payload >> PAGE_SHIFT;
2160 offset = payload & ~PAGE_MASK;
2161 rest = p->payload_length;
2162
2163 /* FIXME: make packet-per-buffer/dual-buffer a context option */
2164 while (rest > 0) {
2165 d = context_get_descriptors(&ctx->context,
2166 z + header_z, &d_bus);
2167 if (d == NULL)
2168 return -ENOMEM;
2169
2170 db = (struct db_descriptor *) d;
2171 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
2172 DESCRIPTOR_BRANCH_ALWAYS);
2173 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
2174 if (p->skip && rest == p->payload_length) {
2175 db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2176 db->first_req_count = db->first_size;
2177 } else {
2178 db->first_req_count = cpu_to_le16(header_size);
2179 }
2180 db->first_res_count = db->first_req_count;
2181 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
2182
2183 if (p->skip && rest == p->payload_length)
2184 length = 4;
2185 else if (offset + rest < PAGE_SIZE)
2186 length = rest;
2187 else
2188 length = PAGE_SIZE - offset;
2189
2190 db->second_req_count = cpu_to_le16(length);
2191 db->second_res_count = db->second_req_count;
2192 page_bus = page_private(buffer->pages[page]);
2193 db->second_buffer = cpu_to_le32(page_bus + offset);
2194
2195 if (p->interrupt && length == rest)
2196 db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2197
2198 context_append(&ctx->context, d, z, header_z);
2199 offset = (offset + length) & ~PAGE_MASK;
2200 rest -= length;
2201 if (offset == 0)
2202 page++;
2203 }
2204
2205 return 0;
2206 }
2207
2208 static int
2209 ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2210 struct fw_iso_packet *packet,
2211 struct fw_iso_buffer *buffer,
2212 unsigned long payload)
2213 {
2214 struct iso_context *ctx = container_of(base, struct iso_context, base);
2215 struct descriptor *d = NULL, *pd = NULL;
2216 struct fw_iso_packet *p = packet;
2217 dma_addr_t d_bus, page_bus;
2218 u32 z, header_z, rest;
2219 int i, j, length;
2220 int page, offset, packet_count, header_size, payload_per_buffer;
2221
2222 /*
2223 * The OHCI controller puts the status word in the
2224 * buffer too, so we need 4 extra bytes per packet.
2225 */
2226 packet_count = p->header_length / ctx->base.header_size;
2227 header_size = ctx->base.header_size + 4;
2228
2229 /* Get header size in number of descriptors. */
2230 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2231 page = payload >> PAGE_SHIFT;
2232 offset = payload & ~PAGE_MASK;
2233 payload_per_buffer = p->payload_length / packet_count;
2234
2235 for (i = 0; i < packet_count; i++) {
2236 /* d points to the header descriptor */
2237 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2238 d = context_get_descriptors(&ctx->context,
2239 z + header_z, &d_bus);
2240 if (d == NULL)
2241 return -ENOMEM;
2242
2243 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2244 DESCRIPTOR_INPUT_MORE);
2245 if (p->skip && i == 0)
2246 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2247 d->req_count = cpu_to_le16(header_size);
2248 d->res_count = d->req_count;
2249 d->transfer_status = 0;
2250 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2251
2252 rest = payload_per_buffer;
2253 for (j = 1; j < z; j++) {
2254 pd = d + j;
2255 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2256 DESCRIPTOR_INPUT_MORE);
2257
2258 if (offset + rest < PAGE_SIZE)
2259 length = rest;
2260 else
2261 length = PAGE_SIZE - offset;
2262 pd->req_count = cpu_to_le16(length);
2263 pd->res_count = pd->req_count;
2264 pd->transfer_status = 0;
2265
2266 page_bus = page_private(buffer->pages[page]);
2267 pd->data_address = cpu_to_le32(page_bus + offset);
2268
2269 offset = (offset + length) & ~PAGE_MASK;
2270 rest -= length;
2271 if (offset == 0)
2272 page++;
2273 }
2274 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2275 DESCRIPTOR_INPUT_LAST |
2276 DESCRIPTOR_BRANCH_ALWAYS);
2277 if (p->interrupt && i == packet_count - 1)
2278 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2279
2280 context_append(&ctx->context, d, z, header_z);
2281 }
2282
2283 return 0;
2284 }
2285
2286 static int
2287 ohci_queue_iso(struct fw_iso_context *base,
2288 struct fw_iso_packet *packet,
2289 struct fw_iso_buffer *buffer,
2290 unsigned long payload)
2291 {
2292 struct iso_context *ctx = container_of(base, struct iso_context, base);
2293 unsigned long flags;
2294 int retval;
2295
2296 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2297 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2298 retval = ohci_queue_iso_transmit(base, packet, buffer, payload);
2299 else if (ctx->context.ohci->use_dualbuffer)
2300 retval = ohci_queue_iso_receive_dualbuffer(base, packet,
2301 buffer, payload);
2302 else
2303 retval = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2304 buffer,
2305 payload);
2306 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2307
2308 return retval;
2309 }
2310
2311 static const struct fw_card_driver ohci_driver = {
2312 .enable = ohci_enable,
2313 .update_phy_reg = ohci_update_phy_reg,
2314 .set_config_rom = ohci_set_config_rom,
2315 .send_request = ohci_send_request,
2316 .send_response = ohci_send_response,
2317 .cancel_packet = ohci_cancel_packet,
2318 .enable_phys_dma = ohci_enable_phys_dma,
2319 .get_bus_time = ohci_get_bus_time,
2320
2321 .allocate_iso_context = ohci_allocate_iso_context,
2322 .free_iso_context = ohci_free_iso_context,
2323 .queue_iso = ohci_queue_iso,
2324 .start_iso = ohci_start_iso,
2325 .stop_iso = ohci_stop_iso,
2326 };
2327
2328 #ifdef CONFIG_PPC_PMAC
2329 static void ohci_pmac_on(struct pci_dev *dev)
2330 {
2331 if (machine_is(powermac)) {
2332 struct device_node *ofn = pci_device_to_OF_node(dev);
2333
2334 if (ofn) {
2335 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2336 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2337 }
2338 }
2339 }
2340
2341 static void ohci_pmac_off(struct pci_dev *dev)
2342 {
2343 if (machine_is(powermac)) {
2344 struct device_node *ofn = pci_device_to_OF_node(dev);
2345
2346 if (ofn) {
2347 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2348 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2349 }
2350 }
2351 }
2352 #else
2353 #define ohci_pmac_on(dev)
2354 #define ohci_pmac_off(dev)
2355 #endif /* CONFIG_PPC_PMAC */
2356
2357 static int __devinit
2358 pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
2359 {
2360 struct fw_ohci *ohci;
2361 u32 bus_options, max_receive, link_speed, version;
2362 u64 guid;
2363 int err;
2364 size_t size;
2365
2366 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2367 if (ohci == NULL) {
2368 err = -ENOMEM;
2369 goto fail;
2370 }
2371
2372 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2373
2374 ohci_pmac_on(dev);
2375
2376 err = pci_enable_device(dev);
2377 if (err) {
2378 fw_error("Failed to enable OHCI hardware\n");
2379 goto fail_free;
2380 }
2381
2382 pci_set_master(dev);
2383 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2384 pci_set_drvdata(dev, ohci);
2385
2386 spin_lock_init(&ohci->lock);
2387
2388 tasklet_init(&ohci->bus_reset_tasklet,
2389 bus_reset_tasklet, (unsigned long)ohci);
2390
2391 err = pci_request_region(dev, 0, ohci_driver_name);
2392 if (err) {
2393 fw_error("MMIO resource unavailable\n");
2394 goto fail_disable;
2395 }
2396
2397 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2398 if (ohci->registers == NULL) {
2399 fw_error("Failed to remap registers\n");
2400 err = -ENXIO;
2401 goto fail_iomem;
2402 }
2403
2404 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2405 ohci->use_dualbuffer = version >= OHCI_VERSION_1_1;
2406
2407 /* x86-32 currently doesn't use highmem for dma_alloc_coherent */
2408 #if !defined(CONFIG_X86_32)
2409 /* dual-buffer mode is broken with descriptor addresses above 2G */
2410 if (dev->vendor == PCI_VENDOR_ID_TI &&
2411 dev->device == PCI_DEVICE_ID_TI_TSB43AB22)
2412 ohci->use_dualbuffer = false;
2413 #endif
2414
2415 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2416 ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2417 dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2418 #endif
2419 ohci->bus_reset_packet_quirk = dev->vendor == PCI_VENDOR_ID_TI;
2420
2421 ar_context_init(&ohci->ar_request_ctx, ohci,
2422 OHCI1394_AsReqRcvContextControlSet);
2423
2424 ar_context_init(&ohci->ar_response_ctx, ohci,
2425 OHCI1394_AsRspRcvContextControlSet);
2426
2427 context_init(&ohci->at_request_ctx, ohci,
2428 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2429
2430 context_init(&ohci->at_response_ctx, ohci,
2431 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2432
2433 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2434 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2435 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2436 size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2437 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2438
2439 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2440 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2441 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2442 size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2443 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2444
2445 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2446 err = -ENOMEM;
2447 goto fail_contexts;
2448 }
2449
2450 /* self-id dma buffer allocation */
2451 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2452 SELF_ID_BUF_SIZE,
2453 &ohci->self_id_bus,
2454 GFP_KERNEL);
2455 if (ohci->self_id_cpu == NULL) {
2456 err = -ENOMEM;
2457 goto fail_contexts;
2458 }
2459
2460 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2461 max_receive = (bus_options >> 12) & 0xf;
2462 link_speed = bus_options & 0x7;
2463 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2464 reg_read(ohci, OHCI1394_GUIDLo);
2465
2466 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2467 if (err < 0)
2468 goto fail_self_id;
2469
2470 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2471 dev->dev.bus_id, version >> 16, version & 0xff);
2472 return 0;
2473
2474 fail_self_id:
2475 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2476 ohci->self_id_cpu, ohci->self_id_bus);
2477 fail_contexts:
2478 kfree(ohci->ir_context_list);
2479 kfree(ohci->it_context_list);
2480 context_release(&ohci->at_response_ctx);
2481 context_release(&ohci->at_request_ctx);
2482 ar_context_release(&ohci->ar_response_ctx);
2483 ar_context_release(&ohci->ar_request_ctx);
2484 pci_iounmap(dev, ohci->registers);
2485 fail_iomem:
2486 pci_release_region(dev, 0);
2487 fail_disable:
2488 pci_disable_device(dev);
2489 fail_free:
2490 kfree(&ohci->card);
2491 ohci_pmac_off(dev);
2492 fail:
2493 if (err == -ENOMEM)
2494 fw_error("Out of memory\n");
2495
2496 return err;
2497 }
2498
2499 static void pci_remove(struct pci_dev *dev)
2500 {
2501 struct fw_ohci *ohci;
2502
2503 ohci = pci_get_drvdata(dev);
2504 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2505 flush_writes(ohci);
2506 fw_core_remove_card(&ohci->card);
2507
2508 /*
2509 * FIXME: Fail all pending packets here, now that the upper
2510 * layers can't queue any more.
2511 */
2512
2513 software_reset(ohci);
2514 free_irq(dev->irq, ohci);
2515
2516 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2517 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2518 ohci->next_config_rom, ohci->next_config_rom_bus);
2519 if (ohci->config_rom)
2520 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2521 ohci->config_rom, ohci->config_rom_bus);
2522 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2523 ohci->self_id_cpu, ohci->self_id_bus);
2524 ar_context_release(&ohci->ar_request_ctx);
2525 ar_context_release(&ohci->ar_response_ctx);
2526 context_release(&ohci->at_request_ctx);
2527 context_release(&ohci->at_response_ctx);
2528 kfree(ohci->it_context_list);
2529 kfree(ohci->ir_context_list);
2530 pci_iounmap(dev, ohci->registers);
2531 pci_release_region(dev, 0);
2532 pci_disable_device(dev);
2533 kfree(&ohci->card);
2534 ohci_pmac_off(dev);
2535
2536 fw_notify("Removed fw-ohci device.\n");
2537 }
2538
2539 #ifdef CONFIG_PM
2540 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2541 {
2542 struct fw_ohci *ohci = pci_get_drvdata(dev);
2543 int err;
2544
2545 software_reset(ohci);
2546 free_irq(dev->irq, ohci);
2547 err = pci_save_state(dev);
2548 if (err) {
2549 fw_error("pci_save_state failed\n");
2550 return err;
2551 }
2552 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2553 if (err)
2554 fw_error("pci_set_power_state failed with %d\n", err);
2555 ohci_pmac_off(dev);
2556
2557 return 0;
2558 }
2559
2560 static int pci_resume(struct pci_dev *dev)
2561 {
2562 struct fw_ohci *ohci = pci_get_drvdata(dev);
2563 int err;
2564
2565 ohci_pmac_on(dev);
2566 pci_set_power_state(dev, PCI_D0);
2567 pci_restore_state(dev);
2568 err = pci_enable_device(dev);
2569 if (err) {
2570 fw_error("pci_enable_device failed\n");
2571 return err;
2572 }
2573
2574 return ohci_enable(&ohci->card, NULL, 0);
2575 }
2576 #endif
2577
2578 static struct pci_device_id pci_table[] = {
2579 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2580 { }
2581 };
2582
2583 MODULE_DEVICE_TABLE(pci, pci_table);
2584
2585 static struct pci_driver fw_ohci_pci_driver = {
2586 .name = ohci_driver_name,
2587 .id_table = pci_table,
2588 .probe = pci_probe,
2589 .remove = pci_remove,
2590 #ifdef CONFIG_PM
2591 .resume = pci_resume,
2592 .suspend = pci_suspend,
2593 #endif
2594 };
2595
2596 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2597 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2598 MODULE_LICENSE("GPL");
2599
2600 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2601 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2602 MODULE_ALIAS("ohci1394");
2603 #endif
2604
2605 static int __init fw_ohci_init(void)
2606 {
2607 return pci_register_driver(&fw_ohci_pci_driver);
2608 }
2609
2610 static void __exit fw_ohci_cleanup(void)
2611 {
2612 pci_unregister_driver(&fw_ohci_pci_driver);
2613 }
2614
2615 module_init(fw_ohci_init);
2616 module_exit(fw_ohci_cleanup);
Linux kernel - Deliverables
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