2 * Driver for OHCI 1394 controllers
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/firewire.h>
26 #include <linux/firewire-constants.h>
27 #include <linux/gfp.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/pci.h>
37 #include <linux/pci_ids.h>
38 #include <linux/spinlock.h>
39 #include <linux/string.h>
41 #include <asm/atomic.h>
42 #include <asm/byteorder.h>
44 #include <asm/system.h>
46 #ifdef CONFIG_PPC_PMAC
47 #include <asm/pmac_feature.h>
53 #define DESCRIPTOR_OUTPUT_MORE 0
54 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
55 #define DESCRIPTOR_INPUT_MORE (2 << 12)
56 #define DESCRIPTOR_INPUT_LAST (3 << 12)
57 #define DESCRIPTOR_STATUS (1 << 11)
58 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
59 #define DESCRIPTOR_PING (1 << 7)
60 #define DESCRIPTOR_YY (1 << 6)
61 #define DESCRIPTOR_NO_IRQ (0 << 4)
62 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
63 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
64 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
65 #define DESCRIPTOR_WAIT (3 << 0)
71 __le32 branch_address
;
73 __le16 transfer_status
;
74 } __attribute__((aligned(16)));
76 struct db_descriptor
{
79 __le16 second_req_count
;
80 __le16 first_req_count
;
81 __le32 branch_address
;
82 __le16 second_res_count
;
83 __le16 first_res_count
;
88 } __attribute__((aligned(16)));
90 #define CONTROL_SET(regs) (regs)
91 #define CONTROL_CLEAR(regs) ((regs) + 4)
92 #define COMMAND_PTR(regs) ((regs) + 12)
93 #define CONTEXT_MATCH(regs) ((regs) + 16)
96 struct descriptor descriptor
;
97 struct ar_buffer
*next
;
102 struct fw_ohci
*ohci
;
103 struct ar_buffer
*current_buffer
;
104 struct ar_buffer
*last_buffer
;
107 struct tasklet_struct tasklet
;
112 typedef int (*descriptor_callback_t
)(struct context
*ctx
,
113 struct descriptor
*d
,
114 struct descriptor
*last
);
117 * A buffer that contains a block of DMA-able coherent memory used for
118 * storing a portion of a DMA descriptor program.
120 struct descriptor_buffer
{
121 struct list_head list
;
122 dma_addr_t buffer_bus
;
125 struct descriptor buffer
[0];
129 struct fw_ohci
*ohci
;
131 int total_allocation
;
134 * List of page-sized buffers for storing DMA descriptors.
135 * Head of list contains buffers in use and tail of list contains
138 struct list_head buffer_list
;
141 * Pointer to a buffer inside buffer_list that contains the tail
142 * end of the current DMA program.
144 struct descriptor_buffer
*buffer_tail
;
147 * The descriptor containing the branch address of the first
148 * descriptor that has not yet been filled by the device.
150 struct descriptor
*last
;
153 * The last descriptor in the DMA program. It contains the branch
154 * address that must be updated upon appending a new descriptor.
156 struct descriptor
*prev
;
158 descriptor_callback_t callback
;
160 struct tasklet_struct tasklet
;
163 #define IT_HEADER_SY(v) ((v) << 0)
164 #define IT_HEADER_TCODE(v) ((v) << 4)
165 #define IT_HEADER_CHANNEL(v) ((v) << 8)
166 #define IT_HEADER_TAG(v) ((v) << 14)
167 #define IT_HEADER_SPEED(v) ((v) << 16)
168 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
171 struct fw_iso_context base
;
172 struct context context
;
175 size_t header_length
;
178 #define CONFIG_ROM_SIZE 1024
183 __iomem
char *registers
;
184 dma_addr_t self_id_bus
;
186 struct tasklet_struct bus_reset_tasklet
;
189 int request_generation
; /* for timestamping incoming requests */
190 atomic_t bus_seconds
;
194 bool bus_reset_packet_quirk
;
197 * Spinlock for accessing fw_ohci data. Never call out of
198 * this driver with this lock held.
201 u32 self_id_buffer
[512];
203 /* Config rom buffers */
205 dma_addr_t config_rom_bus
;
206 __be32
*next_config_rom
;
207 dma_addr_t next_config_rom_bus
;
210 struct ar_context ar_request_ctx
;
211 struct ar_context ar_response_ctx
;
212 struct context at_request_ctx
;
213 struct context at_response_ctx
;
216 struct iso_context
*it_context_list
;
217 u64 ir_context_channels
;
219 struct iso_context
*ir_context_list
;
222 static inline struct fw_ohci
*fw_ohci(struct fw_card
*card
)
224 return container_of(card
, struct fw_ohci
, card
);
227 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
228 #define IR_CONTEXT_BUFFER_FILL 0x80000000
229 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
230 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
231 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
232 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
234 #define CONTEXT_RUN 0x8000
235 #define CONTEXT_WAKE 0x1000
236 #define CONTEXT_DEAD 0x0800
237 #define CONTEXT_ACTIVE 0x0400
239 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
240 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
241 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
243 #define OHCI1394_REGISTER_SIZE 0x800
244 #define OHCI_LOOP_COUNT 500
245 #define OHCI1394_PCI_HCI_Control 0x40
246 #define SELF_ID_BUF_SIZE 0x800
247 #define OHCI_TCODE_PHY_PACKET 0x0e
248 #define OHCI_VERSION_1_1 0x010010
250 static char ohci_driver_name
[] = KBUILD_MODNAME
;
252 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
254 #define OHCI_PARAM_DEBUG_AT_AR 1
255 #define OHCI_PARAM_DEBUG_SELFIDS 2
256 #define OHCI_PARAM_DEBUG_IRQS 4
257 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
259 static int param_debug
;
260 module_param_named(debug
, param_debug
, int, 0644);
261 MODULE_PARM_DESC(debug
, "Verbose logging (default = 0"
262 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR
)
263 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS
)
264 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS
)
265 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS
)
266 ", or a combination, or all = -1)");
268 static void log_irqs(u32 evt
)
270 if (likely(!(param_debug
&
271 (OHCI_PARAM_DEBUG_IRQS
| OHCI_PARAM_DEBUG_BUSRESETS
))))
274 if (!(param_debug
& OHCI_PARAM_DEBUG_IRQS
) &&
275 !(evt
& OHCI1394_busReset
))
278 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt
,
279 evt
& OHCI1394_selfIDComplete
? " selfID" : "",
280 evt
& OHCI1394_RQPkt
? " AR_req" : "",
281 evt
& OHCI1394_RSPkt
? " AR_resp" : "",
282 evt
& OHCI1394_reqTxComplete
? " AT_req" : "",
283 evt
& OHCI1394_respTxComplete
? " AT_resp" : "",
284 evt
& OHCI1394_isochRx
? " IR" : "",
285 evt
& OHCI1394_isochTx
? " IT" : "",
286 evt
& OHCI1394_postedWriteErr
? " postedWriteErr" : "",
287 evt
& OHCI1394_cycleTooLong
? " cycleTooLong" : "",
288 evt
& OHCI1394_cycle64Seconds
? " cycle64Seconds" : "",
289 evt
& OHCI1394_cycleInconsistent
? " cycleInconsistent" : "",
290 evt
& OHCI1394_regAccessFail
? " regAccessFail" : "",
291 evt
& OHCI1394_busReset
? " busReset" : "",
292 evt
& ~(OHCI1394_selfIDComplete
| OHCI1394_RQPkt
|
293 OHCI1394_RSPkt
| OHCI1394_reqTxComplete
|
294 OHCI1394_respTxComplete
| OHCI1394_isochRx
|
295 OHCI1394_isochTx
| OHCI1394_postedWriteErr
|
296 OHCI1394_cycleTooLong
| OHCI1394_cycle64Seconds
|
297 OHCI1394_cycleInconsistent
|
298 OHCI1394_regAccessFail
| OHCI1394_busReset
)
302 static const char *speed
[] = {
303 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
305 static const char *power
[] = {
306 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
307 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
309 static const char port
[] = { '.', '-', 'p', 'c', };
311 static char _p(u32
*s
, int shift
)
313 return port
[*s
>> shift
& 3];
316 static void log_selfids(int node_id
, int generation
, int self_id_count
, u32
*s
)
318 if (likely(!(param_debug
& OHCI_PARAM_DEBUG_SELFIDS
)))
321 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
322 self_id_count
, generation
, node_id
);
324 for (; self_id_count
--; ++s
)
325 if ((*s
& 1 << 23) == 0)
326 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
327 "%s gc=%d %s %s%s%s\n",
328 *s
, *s
>> 24 & 63, _p(s
, 6), _p(s
, 4), _p(s
, 2),
329 speed
[*s
>> 14 & 3], *s
>> 16 & 63,
330 power
[*s
>> 8 & 7], *s
>> 22 & 1 ? "L" : "",
331 *s
>> 11 & 1 ? "c" : "", *s
& 2 ? "i" : "");
333 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
335 _p(s
, 16), _p(s
, 14), _p(s
, 12), _p(s
, 10),
336 _p(s
, 8), _p(s
, 6), _p(s
, 4), _p(s
, 2));
339 static const char *evts
[] = {
340 [0x00] = "evt_no_status", [0x01] = "-reserved-",
341 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
342 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
343 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
344 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
345 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
346 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
347 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
348 [0x10] = "-reserved-", [0x11] = "ack_complete",
349 [0x12] = "ack_pending ", [0x13] = "-reserved-",
350 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
351 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
352 [0x18] = "-reserved-", [0x19] = "-reserved-",
353 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
354 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
355 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
356 [0x20] = "pending/cancelled",
358 static const char *tcodes
[] = {
359 [0x0] = "QW req", [0x1] = "BW req",
360 [0x2] = "W resp", [0x3] = "-reserved-",
361 [0x4] = "QR req", [0x5] = "BR req",
362 [0x6] = "QR resp", [0x7] = "BR resp",
363 [0x8] = "cycle start", [0x9] = "Lk req",
364 [0xa] = "async stream packet", [0xb] = "Lk resp",
365 [0xc] = "-reserved-", [0xd] = "-reserved-",
366 [0xe] = "link internal", [0xf] = "-reserved-",
368 static const char *phys
[] = {
369 [0x0] = "phy config packet", [0x1] = "link-on packet",
370 [0x2] = "self-id packet", [0x3] = "-reserved-",
373 static void log_ar_at_event(char dir
, int speed
, u32
*header
, int evt
)
375 int tcode
= header
[0] >> 4 & 0xf;
378 if (likely(!(param_debug
& OHCI_PARAM_DEBUG_AT_AR
)))
381 if (unlikely(evt
>= ARRAY_SIZE(evts
)))
384 if (evt
== OHCI1394_evt_bus_reset
) {
385 fw_notify("A%c evt_bus_reset, generation %d\n",
386 dir
, (header
[2] >> 16) & 0xff);
390 if (header
[0] == ~header
[1]) {
391 fw_notify("A%c %s, %s, %08x\n",
392 dir
, evts
[evt
], phys
[header
[0] >> 30 & 0x3], header
[0]);
397 case 0x0: case 0x6: case 0x8:
398 snprintf(specific
, sizeof(specific
), " = %08x",
399 be32_to_cpu((__force __be32
)header
[3]));
401 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
402 snprintf(specific
, sizeof(specific
), " %x,%x",
403 header
[3] >> 16, header
[3] & 0xffff);
411 fw_notify("A%c %s, %s\n", dir
, evts
[evt
], tcodes
[tcode
]);
413 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
414 fw_notify("A%c spd %x tl %02x, "
417 dir
, speed
, header
[0] >> 10 & 0x3f,
418 header
[1] >> 16, header
[0] >> 16, evts
[evt
],
419 tcodes
[tcode
], header
[1] & 0xffff, header
[2], specific
);
422 fw_notify("A%c spd %x tl %02x, "
425 dir
, speed
, header
[0] >> 10 & 0x3f,
426 header
[1] >> 16, header
[0] >> 16, evts
[evt
],
427 tcodes
[tcode
], specific
);
433 #define log_irqs(evt)
434 #define log_selfids(node_id, generation, self_id_count, sid)
435 #define log_ar_at_event(dir, speed, header, evt)
437 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
439 static inline void reg_write(const struct fw_ohci
*ohci
, int offset
, u32 data
)
441 writel(data
, ohci
->registers
+ offset
);
444 static inline u32
reg_read(const struct fw_ohci
*ohci
, int offset
)
446 return readl(ohci
->registers
+ offset
);
449 static inline void flush_writes(const struct fw_ohci
*ohci
)
451 /* Do a dummy read to flush writes. */
452 reg_read(ohci
, OHCI1394_Version
);
455 static int ohci_update_phy_reg(struct fw_card
*card
, int addr
,
456 int clear_bits
, int set_bits
)
458 struct fw_ohci
*ohci
= fw_ohci(card
);
461 reg_write(ohci
, OHCI1394_PhyControl
, OHCI1394_PhyControl_Read(addr
));
464 val
= reg_read(ohci
, OHCI1394_PhyControl
);
465 if ((val
& OHCI1394_PhyControl_ReadDone
) == 0) {
466 fw_error("failed to set phy reg bits.\n");
470 old
= OHCI1394_PhyControl_ReadData(val
);
471 old
= (old
& ~clear_bits
) | set_bits
;
472 reg_write(ohci
, OHCI1394_PhyControl
,
473 OHCI1394_PhyControl_Write(addr
, old
));
478 static int ar_context_add_page(struct ar_context
*ctx
)
480 struct device
*dev
= ctx
->ohci
->card
.device
;
481 struct ar_buffer
*ab
;
482 dma_addr_t
uninitialized_var(ab_bus
);
485 ab
= dma_alloc_coherent(dev
, PAGE_SIZE
, &ab_bus
, GFP_ATOMIC
);
490 memset(&ab
->descriptor
, 0, sizeof(ab
->descriptor
));
491 ab
->descriptor
.control
= cpu_to_le16(DESCRIPTOR_INPUT_MORE
|
493 DESCRIPTOR_BRANCH_ALWAYS
);
494 offset
= offsetof(struct ar_buffer
, data
);
495 ab
->descriptor
.req_count
= cpu_to_le16(PAGE_SIZE
- offset
);
496 ab
->descriptor
.data_address
= cpu_to_le32(ab_bus
+ offset
);
497 ab
->descriptor
.res_count
= cpu_to_le16(PAGE_SIZE
- offset
);
498 ab
->descriptor
.branch_address
= 0;
500 ctx
->last_buffer
->descriptor
.branch_address
= cpu_to_le32(ab_bus
| 1);
501 ctx
->last_buffer
->next
= ab
;
502 ctx
->last_buffer
= ab
;
504 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_WAKE
);
505 flush_writes(ctx
->ohci
);
510 static void ar_context_release(struct ar_context
*ctx
)
512 struct ar_buffer
*ab
, *ab_next
;
516 for (ab
= ctx
->current_buffer
; ab
; ab
= ab_next
) {
518 offset
= offsetof(struct ar_buffer
, data
);
519 ab_bus
= le32_to_cpu(ab
->descriptor
.data_address
) - offset
;
520 dma_free_coherent(ctx
->ohci
->card
.device
, PAGE_SIZE
,
525 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
526 #define cond_le32_to_cpu(v) \
527 (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
529 #define cond_le32_to_cpu(v) le32_to_cpu(v)
532 static __le32
*handle_ar_packet(struct ar_context
*ctx
, __le32
*buffer
)
534 struct fw_ohci
*ohci
= ctx
->ohci
;
536 u32 status
, length
, tcode
;
539 p
.header
[0] = cond_le32_to_cpu(buffer
[0]);
540 p
.header
[1] = cond_le32_to_cpu(buffer
[1]);
541 p
.header
[2] = cond_le32_to_cpu(buffer
[2]);
543 tcode
= (p
.header
[0] >> 4) & 0x0f;
545 case TCODE_WRITE_QUADLET_REQUEST
:
546 case TCODE_READ_QUADLET_RESPONSE
:
547 p
.header
[3] = (__force __u32
) buffer
[3];
548 p
.header_length
= 16;
549 p
.payload_length
= 0;
552 case TCODE_READ_BLOCK_REQUEST
:
553 p
.header
[3] = cond_le32_to_cpu(buffer
[3]);
554 p
.header_length
= 16;
555 p
.payload_length
= 0;
558 case TCODE_WRITE_BLOCK_REQUEST
:
559 case TCODE_READ_BLOCK_RESPONSE
:
560 case TCODE_LOCK_REQUEST
:
561 case TCODE_LOCK_RESPONSE
:
562 p
.header
[3] = cond_le32_to_cpu(buffer
[3]);
563 p
.header_length
= 16;
564 p
.payload_length
= p
.header
[3] >> 16;
567 case TCODE_WRITE_RESPONSE
:
568 case TCODE_READ_QUADLET_REQUEST
:
569 case OHCI_TCODE_PHY_PACKET
:
570 p
.header_length
= 12;
571 p
.payload_length
= 0;
575 /* FIXME: Stop context, discard everything, and restart? */
577 p
.payload_length
= 0;
580 p
.payload
= (void *) buffer
+ p
.header_length
;
582 /* FIXME: What to do about evt_* errors? */
583 length
= (p
.header_length
+ p
.payload_length
+ 3) / 4;
584 status
= cond_le32_to_cpu(buffer
[length
]);
585 evt
= (status
>> 16) & 0x1f;
588 p
.speed
= (status
>> 21) & 0x7;
589 p
.timestamp
= status
& 0xffff;
590 p
.generation
= ohci
->request_generation
;
592 log_ar_at_event('R', p
.speed
, p
.header
, evt
);
595 * The OHCI bus reset handler synthesizes a phy packet with
596 * the new generation number when a bus reset happens (see
597 * section 8.4.2.3). This helps us determine when a request
598 * was received and make sure we send the response in the same
599 * generation. We only need this for requests; for responses
600 * we use the unique tlabel for finding the matching
603 * Alas some chips sometimes emit bus reset packets with a
604 * wrong generation. We set the correct generation for these
605 * at a slightly incorrect time (in bus_reset_tasklet).
607 if (evt
== OHCI1394_evt_bus_reset
) {
608 if (!ohci
->bus_reset_packet_quirk
)
609 ohci
->request_generation
= (p
.header
[2] >> 16) & 0xff;
610 } else if (ctx
== &ohci
->ar_request_ctx
) {
611 fw_core_handle_request(&ohci
->card
, &p
);
613 fw_core_handle_response(&ohci
->card
, &p
);
616 return buffer
+ length
+ 1;
619 static void ar_context_tasklet(unsigned long data
)
621 struct ar_context
*ctx
= (struct ar_context
*)data
;
622 struct fw_ohci
*ohci
= ctx
->ohci
;
623 struct ar_buffer
*ab
;
624 struct descriptor
*d
;
627 ab
= ctx
->current_buffer
;
630 if (d
->res_count
== 0) {
631 size_t size
, rest
, offset
;
632 dma_addr_t start_bus
;
636 * This descriptor is finished and we may have a
637 * packet split across this and the next buffer. We
638 * reuse the page for reassembling the split packet.
641 offset
= offsetof(struct ar_buffer
, data
);
643 start_bus
= le32_to_cpu(ab
->descriptor
.data_address
) - offset
;
647 size
= buffer
+ PAGE_SIZE
- ctx
->pointer
;
648 rest
= le16_to_cpu(d
->req_count
) - le16_to_cpu(d
->res_count
);
649 memmove(buffer
, ctx
->pointer
, size
);
650 memcpy(buffer
+ size
, ab
->data
, rest
);
651 ctx
->current_buffer
= ab
;
652 ctx
->pointer
= (void *) ab
->data
+ rest
;
653 end
= buffer
+ size
+ rest
;
656 buffer
= handle_ar_packet(ctx
, buffer
);
658 dma_free_coherent(ohci
->card
.device
, PAGE_SIZE
,
660 ar_context_add_page(ctx
);
662 buffer
= ctx
->pointer
;
664 (void *) ab
+ PAGE_SIZE
- le16_to_cpu(d
->res_count
);
667 buffer
= handle_ar_packet(ctx
, buffer
);
671 static int ar_context_init(struct ar_context
*ctx
,
672 struct fw_ohci
*ohci
, u32 regs
)
678 ctx
->last_buffer
= &ab
;
679 tasklet_init(&ctx
->tasklet
, ar_context_tasklet
, (unsigned long)ctx
);
681 ar_context_add_page(ctx
);
682 ar_context_add_page(ctx
);
683 ctx
->current_buffer
= ab
.next
;
684 ctx
->pointer
= ctx
->current_buffer
->data
;
689 static void ar_context_run(struct ar_context
*ctx
)
691 struct ar_buffer
*ab
= ctx
->current_buffer
;
695 offset
= offsetof(struct ar_buffer
, data
);
696 ab_bus
= le32_to_cpu(ab
->descriptor
.data_address
) - offset
;
698 reg_write(ctx
->ohci
, COMMAND_PTR(ctx
->regs
), ab_bus
| 1);
699 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_RUN
);
700 flush_writes(ctx
->ohci
);
703 static struct descriptor
*find_branch_descriptor(struct descriptor
*d
, int z
)
707 b
= (le16_to_cpu(d
->control
) & DESCRIPTOR_BRANCH_ALWAYS
) >> 2;
708 key
= (le16_to_cpu(d
->control
) & DESCRIPTOR_KEY_IMMEDIATE
) >> 8;
710 /* figure out which descriptor the branch address goes in */
711 if (z
== 2 && (b
== 3 || key
== 2))
717 static void context_tasklet(unsigned long data
)
719 struct context
*ctx
= (struct context
*) data
;
720 struct descriptor
*d
, *last
;
723 struct descriptor_buffer
*desc
;
725 desc
= list_entry(ctx
->buffer_list
.next
,
726 struct descriptor_buffer
, list
);
728 while (last
->branch_address
!= 0) {
729 struct descriptor_buffer
*old_desc
= desc
;
730 address
= le32_to_cpu(last
->branch_address
);
734 /* If the branch address points to a buffer outside of the
735 * current buffer, advance to the next buffer. */
736 if (address
< desc
->buffer_bus
||
737 address
>= desc
->buffer_bus
+ desc
->used
)
738 desc
= list_entry(desc
->list
.next
,
739 struct descriptor_buffer
, list
);
740 d
= desc
->buffer
+ (address
- desc
->buffer_bus
) / sizeof(*d
);
741 last
= find_branch_descriptor(d
, z
);
743 if (!ctx
->callback(ctx
, d
, last
))
746 if (old_desc
!= desc
) {
747 /* If we've advanced to the next buffer, move the
748 * previous buffer to the free list. */
751 spin_lock_irqsave(&ctx
->ohci
->lock
, flags
);
752 list_move_tail(&old_desc
->list
, &ctx
->buffer_list
);
753 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
760 * Allocate a new buffer and add it to the list of free buffers for this
761 * context. Must be called with ohci->lock held.
763 static int context_add_buffer(struct context
*ctx
)
765 struct descriptor_buffer
*desc
;
766 dma_addr_t
uninitialized_var(bus_addr
);
770 * 16MB of descriptors should be far more than enough for any DMA
771 * program. This will catch run-away userspace or DoS attacks.
773 if (ctx
->total_allocation
>= 16*1024*1024)
776 desc
= dma_alloc_coherent(ctx
->ohci
->card
.device
, PAGE_SIZE
,
777 &bus_addr
, GFP_ATOMIC
);
781 offset
= (void *)&desc
->buffer
- (void *)desc
;
782 desc
->buffer_size
= PAGE_SIZE
- offset
;
783 desc
->buffer_bus
= bus_addr
+ offset
;
786 list_add_tail(&desc
->list
, &ctx
->buffer_list
);
787 ctx
->total_allocation
+= PAGE_SIZE
;
792 static int context_init(struct context
*ctx
, struct fw_ohci
*ohci
,
793 u32 regs
, descriptor_callback_t callback
)
797 ctx
->total_allocation
= 0;
799 INIT_LIST_HEAD(&ctx
->buffer_list
);
800 if (context_add_buffer(ctx
) < 0)
803 ctx
->buffer_tail
= list_entry(ctx
->buffer_list
.next
,
804 struct descriptor_buffer
, list
);
806 tasklet_init(&ctx
->tasklet
, context_tasklet
, (unsigned long)ctx
);
807 ctx
->callback
= callback
;
810 * We put a dummy descriptor in the buffer that has a NULL
811 * branch address and looks like it's been sent. That way we
812 * have a descriptor to append DMA programs to.
814 memset(ctx
->buffer_tail
->buffer
, 0, sizeof(*ctx
->buffer_tail
->buffer
));
815 ctx
->buffer_tail
->buffer
->control
= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
);
816 ctx
->buffer_tail
->buffer
->transfer_status
= cpu_to_le16(0x8011);
817 ctx
->buffer_tail
->used
+= sizeof(*ctx
->buffer_tail
->buffer
);
818 ctx
->last
= ctx
->buffer_tail
->buffer
;
819 ctx
->prev
= ctx
->buffer_tail
->buffer
;
824 static void context_release(struct context
*ctx
)
826 struct fw_card
*card
= &ctx
->ohci
->card
;
827 struct descriptor_buffer
*desc
, *tmp
;
829 list_for_each_entry_safe(desc
, tmp
, &ctx
->buffer_list
, list
)
830 dma_free_coherent(card
->device
, PAGE_SIZE
, desc
,
832 ((void *)&desc
->buffer
- (void *)desc
));
835 /* Must be called with ohci->lock held */
836 static struct descriptor
*context_get_descriptors(struct context
*ctx
,
837 int z
, dma_addr_t
*d_bus
)
839 struct descriptor
*d
= NULL
;
840 struct descriptor_buffer
*desc
= ctx
->buffer_tail
;
842 if (z
* sizeof(*d
) > desc
->buffer_size
)
845 if (z
* sizeof(*d
) > desc
->buffer_size
- desc
->used
) {
846 /* No room for the descriptor in this buffer, so advance to the
849 if (desc
->list
.next
== &ctx
->buffer_list
) {
850 /* If there is no free buffer next in the list,
852 if (context_add_buffer(ctx
) < 0)
855 desc
= list_entry(desc
->list
.next
,
856 struct descriptor_buffer
, list
);
857 ctx
->buffer_tail
= desc
;
860 d
= desc
->buffer
+ desc
->used
/ sizeof(*d
);
861 memset(d
, 0, z
* sizeof(*d
));
862 *d_bus
= desc
->buffer_bus
+ desc
->used
;
867 static void context_run(struct context
*ctx
, u32 extra
)
869 struct fw_ohci
*ohci
= ctx
->ohci
;
871 reg_write(ohci
, COMMAND_PTR(ctx
->regs
),
872 le32_to_cpu(ctx
->last
->branch_address
));
873 reg_write(ohci
, CONTROL_CLEAR(ctx
->regs
), ~0);
874 reg_write(ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_RUN
| extra
);
878 static void context_append(struct context
*ctx
,
879 struct descriptor
*d
, int z
, int extra
)
882 struct descriptor_buffer
*desc
= ctx
->buffer_tail
;
884 d_bus
= desc
->buffer_bus
+ (d
- desc
->buffer
) * sizeof(*d
);
886 desc
->used
+= (z
+ extra
) * sizeof(*d
);
887 ctx
->prev
->branch_address
= cpu_to_le32(d_bus
| z
);
888 ctx
->prev
= find_branch_descriptor(d
, z
);
890 reg_write(ctx
->ohci
, CONTROL_SET(ctx
->regs
), CONTEXT_WAKE
);
891 flush_writes(ctx
->ohci
);
894 static void context_stop(struct context
*ctx
)
899 reg_write(ctx
->ohci
, CONTROL_CLEAR(ctx
->regs
), CONTEXT_RUN
);
900 flush_writes(ctx
->ohci
);
902 for (i
= 0; i
< 10; i
++) {
903 reg
= reg_read(ctx
->ohci
, CONTROL_SET(ctx
->regs
));
904 if ((reg
& CONTEXT_ACTIVE
) == 0)
909 fw_error("Error: DMA context still active (0x%08x)\n", reg
);
913 struct fw_packet
*packet
;
917 * This function apppends a packet to the DMA queue for transmission.
918 * Must always be called with the ochi->lock held to ensure proper
919 * generation handling and locking around packet queue manipulation.
921 static int at_context_queue_packet(struct context
*ctx
,
922 struct fw_packet
*packet
)
924 struct fw_ohci
*ohci
= ctx
->ohci
;
925 dma_addr_t d_bus
, uninitialized_var(payload_bus
);
926 struct driver_data
*driver_data
;
927 struct descriptor
*d
, *last
;
932 d
= context_get_descriptors(ctx
, 4, &d_bus
);
934 packet
->ack
= RCODE_SEND_ERROR
;
938 d
[0].control
= cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE
);
939 d
[0].res_count
= cpu_to_le16(packet
->timestamp
);
942 * The DMA format for asyncronous link packets is different
943 * from the IEEE1394 layout, so shift the fields around
944 * accordingly. If header_length is 8, it's a PHY packet, to
945 * which we need to prepend an extra quadlet.
948 header
= (__le32
*) &d
[1];
949 switch (packet
->header_length
) {
952 header
[0] = cpu_to_le32((packet
->header
[0] & 0xffff) |
953 (packet
->speed
<< 16));
954 header
[1] = cpu_to_le32((packet
->header
[1] & 0xffff) |
955 (packet
->header
[0] & 0xffff0000));
956 header
[2] = cpu_to_le32(packet
->header
[2]);
958 tcode
= (packet
->header
[0] >> 4) & 0x0f;
959 if (TCODE_IS_BLOCK_PACKET(tcode
))
960 header
[3] = cpu_to_le32(packet
->header
[3]);
962 header
[3] = (__force __le32
) packet
->header
[3];
964 d
[0].req_count
= cpu_to_le16(packet
->header_length
);
968 header
[0] = cpu_to_le32((OHCI1394_phy_tcode
<< 4) |
969 (packet
->speed
<< 16));
970 header
[1] = cpu_to_le32(packet
->header
[0]);
971 header
[2] = cpu_to_le32(packet
->header
[1]);
972 d
[0].req_count
= cpu_to_le16(12);
976 header
[0] = cpu_to_le32((packet
->header
[0] & 0xffff) |
977 (packet
->speed
<< 16));
978 header
[1] = cpu_to_le32(packet
->header
[0] & 0xffff0000);
979 d
[0].req_count
= cpu_to_le16(8);
984 packet
->ack
= RCODE_SEND_ERROR
;
988 driver_data
= (struct driver_data
*) &d
[3];
989 driver_data
->packet
= packet
;
990 packet
->driver_data
= driver_data
;
992 if (packet
->payload_length
> 0) {
994 dma_map_single(ohci
->card
.device
, packet
->payload
,
995 packet
->payload_length
, DMA_TO_DEVICE
);
996 if (dma_mapping_error(ohci
->card
.device
, payload_bus
)) {
997 packet
->ack
= RCODE_SEND_ERROR
;
1000 packet
->payload_bus
= payload_bus
;
1001 packet
->payload_mapped
= true;
1003 d
[2].req_count
= cpu_to_le16(packet
->payload_length
);
1004 d
[2].data_address
= cpu_to_le32(payload_bus
);
1012 last
->control
|= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
|
1013 DESCRIPTOR_IRQ_ALWAYS
|
1014 DESCRIPTOR_BRANCH_ALWAYS
);
1017 * If the controller and packet generations don't match, we need to
1018 * bail out and try again. If IntEvent.busReset is set, the AT context
1019 * is halted, so appending to the context and trying to run it is
1020 * futile. Most controllers do the right thing and just flush the AT
1021 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1022 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1023 * up stalling out. So we just bail out in software and try again
1024 * later, and everyone is happy.
1025 * FIXME: Document how the locking works.
1027 if (ohci
->generation
!= packet
->generation
||
1028 reg_read(ohci
, OHCI1394_IntEventSet
) & OHCI1394_busReset
) {
1029 if (packet
->payload_mapped
)
1030 dma_unmap_single(ohci
->card
.device
, payload_bus
,
1031 packet
->payload_length
, DMA_TO_DEVICE
);
1032 packet
->ack
= RCODE_GENERATION
;
1036 context_append(ctx
, d
, z
, 4 - z
);
1038 /* If the context isn't already running, start it up. */
1039 reg
= reg_read(ctx
->ohci
, CONTROL_SET(ctx
->regs
));
1040 if ((reg
& CONTEXT_RUN
) == 0)
1041 context_run(ctx
, 0);
1046 static int handle_at_packet(struct context
*context
,
1047 struct descriptor
*d
,
1048 struct descriptor
*last
)
1050 struct driver_data
*driver_data
;
1051 struct fw_packet
*packet
;
1052 struct fw_ohci
*ohci
= context
->ohci
;
1055 if (last
->transfer_status
== 0)
1056 /* This descriptor isn't done yet, stop iteration. */
1059 driver_data
= (struct driver_data
*) &d
[3];
1060 packet
= driver_data
->packet
;
1062 /* This packet was cancelled, just continue. */
1065 if (packet
->payload_mapped
)
1066 dma_unmap_single(ohci
->card
.device
, packet
->payload_bus
,
1067 packet
->payload_length
, DMA_TO_DEVICE
);
1069 evt
= le16_to_cpu(last
->transfer_status
) & 0x1f;
1070 packet
->timestamp
= le16_to_cpu(last
->res_count
);
1072 log_ar_at_event('T', packet
->speed
, packet
->header
, evt
);
1075 case OHCI1394_evt_timeout
:
1076 /* Async response transmit timed out. */
1077 packet
->ack
= RCODE_CANCELLED
;
1080 case OHCI1394_evt_flushed
:
1082 * The packet was flushed should give same error as
1083 * when we try to use a stale generation count.
1085 packet
->ack
= RCODE_GENERATION
;
1088 case OHCI1394_evt_missing_ack
:
1090 * Using a valid (current) generation count, but the
1091 * node is not on the bus or not sending acks.
1093 packet
->ack
= RCODE_NO_ACK
;
1096 case ACK_COMPLETE
+ 0x10:
1097 case ACK_PENDING
+ 0x10:
1098 case ACK_BUSY_X
+ 0x10:
1099 case ACK_BUSY_A
+ 0x10:
1100 case ACK_BUSY_B
+ 0x10:
1101 case ACK_DATA_ERROR
+ 0x10:
1102 case ACK_TYPE_ERROR
+ 0x10:
1103 packet
->ack
= evt
- 0x10;
1107 packet
->ack
= RCODE_SEND_ERROR
;
1111 packet
->callback(packet
, &ohci
->card
, packet
->ack
);
1116 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1117 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1118 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1119 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1120 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1122 static void handle_local_rom(struct fw_ohci
*ohci
,
1123 struct fw_packet
*packet
, u32 csr
)
1125 struct fw_packet response
;
1126 int tcode
, length
, i
;
1128 tcode
= HEADER_GET_TCODE(packet
->header
[0]);
1129 if (TCODE_IS_BLOCK_PACKET(tcode
))
1130 length
= HEADER_GET_DATA_LENGTH(packet
->header
[3]);
1134 i
= csr
- CSR_CONFIG_ROM
;
1135 if (i
+ length
> CONFIG_ROM_SIZE
) {
1136 fw_fill_response(&response
, packet
->header
,
1137 RCODE_ADDRESS_ERROR
, NULL
, 0);
1138 } else if (!TCODE_IS_READ_REQUEST(tcode
)) {
1139 fw_fill_response(&response
, packet
->header
,
1140 RCODE_TYPE_ERROR
, NULL
, 0);
1142 fw_fill_response(&response
, packet
->header
, RCODE_COMPLETE
,
1143 (void *) ohci
->config_rom
+ i
, length
);
1146 fw_core_handle_response(&ohci
->card
, &response
);
1149 static void handle_local_lock(struct fw_ohci
*ohci
,
1150 struct fw_packet
*packet
, u32 csr
)
1152 struct fw_packet response
;
1153 int tcode
, length
, ext_tcode
, sel
;
1154 __be32
*payload
, lock_old
;
1155 u32 lock_arg
, lock_data
;
1157 tcode
= HEADER_GET_TCODE(packet
->header
[0]);
1158 length
= HEADER_GET_DATA_LENGTH(packet
->header
[3]);
1159 payload
= packet
->payload
;
1160 ext_tcode
= HEADER_GET_EXTENDED_TCODE(packet
->header
[3]);
1162 if (tcode
== TCODE_LOCK_REQUEST
&&
1163 ext_tcode
== EXTCODE_COMPARE_SWAP
&& length
== 8) {
1164 lock_arg
= be32_to_cpu(payload
[0]);
1165 lock_data
= be32_to_cpu(payload
[1]);
1166 } else if (tcode
== TCODE_READ_QUADLET_REQUEST
) {
1170 fw_fill_response(&response
, packet
->header
,
1171 RCODE_TYPE_ERROR
, NULL
, 0);
1175 sel
= (csr
- CSR_BUS_MANAGER_ID
) / 4;
1176 reg_write(ohci
, OHCI1394_CSRData
, lock_data
);
1177 reg_write(ohci
, OHCI1394_CSRCompareData
, lock_arg
);
1178 reg_write(ohci
, OHCI1394_CSRControl
, sel
);
1180 if (reg_read(ohci
, OHCI1394_CSRControl
) & 0x80000000)
1181 lock_old
= cpu_to_be32(reg_read(ohci
, OHCI1394_CSRData
));
1183 fw_notify("swap not done yet\n");
1185 fw_fill_response(&response
, packet
->header
,
1186 RCODE_COMPLETE
, &lock_old
, sizeof(lock_old
));
1188 fw_core_handle_response(&ohci
->card
, &response
);
1191 static void handle_local_request(struct context
*ctx
, struct fw_packet
*packet
)
1196 if (ctx
== &ctx
->ohci
->at_request_ctx
) {
1197 packet
->ack
= ACK_PENDING
;
1198 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
1202 ((unsigned long long)
1203 HEADER_GET_OFFSET_HIGH(packet
->header
[1]) << 32) |
1205 csr
= offset
- CSR_REGISTER_BASE
;
1207 /* Handle config rom reads. */
1208 if (csr
>= CSR_CONFIG_ROM
&& csr
< CSR_CONFIG_ROM_END
)
1209 handle_local_rom(ctx
->ohci
, packet
, csr
);
1211 case CSR_BUS_MANAGER_ID
:
1212 case CSR_BANDWIDTH_AVAILABLE
:
1213 case CSR_CHANNELS_AVAILABLE_HI
:
1214 case CSR_CHANNELS_AVAILABLE_LO
:
1215 handle_local_lock(ctx
->ohci
, packet
, csr
);
1218 if (ctx
== &ctx
->ohci
->at_request_ctx
)
1219 fw_core_handle_request(&ctx
->ohci
->card
, packet
);
1221 fw_core_handle_response(&ctx
->ohci
->card
, packet
);
1225 if (ctx
== &ctx
->ohci
->at_response_ctx
) {
1226 packet
->ack
= ACK_COMPLETE
;
1227 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
1231 static void at_context_transmit(struct context
*ctx
, struct fw_packet
*packet
)
1233 unsigned long flags
;
1236 spin_lock_irqsave(&ctx
->ohci
->lock
, flags
);
1238 if (HEADER_GET_DESTINATION(packet
->header
[0]) == ctx
->ohci
->node_id
&&
1239 ctx
->ohci
->generation
== packet
->generation
) {
1240 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
1241 handle_local_request(ctx
, packet
);
1245 ret
= at_context_queue_packet(ctx
, packet
);
1246 spin_unlock_irqrestore(&ctx
->ohci
->lock
, flags
);
1249 packet
->callback(packet
, &ctx
->ohci
->card
, packet
->ack
);
1253 static void bus_reset_tasklet(unsigned long data
)
1255 struct fw_ohci
*ohci
= (struct fw_ohci
*)data
;
1256 int self_id_count
, i
, j
, reg
;
1257 int generation
, new_generation
;
1258 unsigned long flags
;
1259 void *free_rom
= NULL
;
1260 dma_addr_t free_rom_bus
= 0;
1262 reg
= reg_read(ohci
, OHCI1394_NodeID
);
1263 if (!(reg
& OHCI1394_NodeID_idValid
)) {
1264 fw_notify("node ID not valid, new bus reset in progress\n");
1267 if ((reg
& OHCI1394_NodeID_nodeNumber
) == 63) {
1268 fw_notify("malconfigured bus\n");
1271 ohci
->node_id
= reg
& (OHCI1394_NodeID_busNumber
|
1272 OHCI1394_NodeID_nodeNumber
);
1274 reg
= reg_read(ohci
, OHCI1394_SelfIDCount
);
1275 if (reg
& OHCI1394_SelfIDCount_selfIDError
) {
1276 fw_notify("inconsistent self IDs\n");
1280 * The count in the SelfIDCount register is the number of
1281 * bytes in the self ID receive buffer. Since we also receive
1282 * the inverted quadlets and a header quadlet, we shift one
1283 * bit extra to get the actual number of self IDs.
1285 self_id_count
= (reg
>> 3) & 0xff;
1286 if (self_id_count
== 0 || self_id_count
> 252) {
1287 fw_notify("inconsistent self IDs\n");
1290 generation
= (cond_le32_to_cpu(ohci
->self_id_cpu
[0]) >> 16) & 0xff;
1293 for (i
= 1, j
= 0; j
< self_id_count
; i
+= 2, j
++) {
1294 if (ohci
->self_id_cpu
[i
] != ~ohci
->self_id_cpu
[i
+ 1]) {
1295 fw_notify("inconsistent self IDs\n");
1298 ohci
->self_id_buffer
[j
] =
1299 cond_le32_to_cpu(ohci
->self_id_cpu
[i
]);
1304 * Check the consistency of the self IDs we just read. The
1305 * problem we face is that a new bus reset can start while we
1306 * read out the self IDs from the DMA buffer. If this happens,
1307 * the DMA buffer will be overwritten with new self IDs and we
1308 * will read out inconsistent data. The OHCI specification
1309 * (section 11.2) recommends a technique similar to
1310 * linux/seqlock.h, where we remember the generation of the
1311 * self IDs in the buffer before reading them out and compare
1312 * it to the current generation after reading them out. If
1313 * the two generations match we know we have a consistent set
1317 new_generation
= (reg_read(ohci
, OHCI1394_SelfIDCount
) >> 16) & 0xff;
1318 if (new_generation
!= generation
) {
1319 fw_notify("recursive bus reset detected, "
1320 "discarding self ids\n");
1324 /* FIXME: Document how the locking works. */
1325 spin_lock_irqsave(&ohci
->lock
, flags
);
1327 ohci
->generation
= generation
;
1328 context_stop(&ohci
->at_request_ctx
);
1329 context_stop(&ohci
->at_response_ctx
);
1330 reg_write(ohci
, OHCI1394_IntEventClear
, OHCI1394_busReset
);
1332 if (ohci
->bus_reset_packet_quirk
)
1333 ohci
->request_generation
= generation
;
1336 * This next bit is unrelated to the AT context stuff but we
1337 * have to do it under the spinlock also. If a new config rom
1338 * was set up before this reset, the old one is now no longer
1339 * in use and we can free it. Update the config rom pointers
1340 * to point to the current config rom and clear the
1341 * next_config_rom pointer so a new udpate can take place.
1344 if (ohci
->next_config_rom
!= NULL
) {
1345 if (ohci
->next_config_rom
!= ohci
->config_rom
) {
1346 free_rom
= ohci
->config_rom
;
1347 free_rom_bus
= ohci
->config_rom_bus
;
1349 ohci
->config_rom
= ohci
->next_config_rom
;
1350 ohci
->config_rom_bus
= ohci
->next_config_rom_bus
;
1351 ohci
->next_config_rom
= NULL
;
1354 * Restore config_rom image and manually update
1355 * config_rom registers. Writing the header quadlet
1356 * will indicate that the config rom is ready, so we
1359 reg_write(ohci
, OHCI1394_BusOptions
,
1360 be32_to_cpu(ohci
->config_rom
[2]));
1361 ohci
->config_rom
[0] = ohci
->next_header
;
1362 reg_write(ohci
, OHCI1394_ConfigROMhdr
,
1363 be32_to_cpu(ohci
->next_header
));
1366 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1367 reg_write(ohci
, OHCI1394_PhyReqFilterHiSet
, ~0);
1368 reg_write(ohci
, OHCI1394_PhyReqFilterLoSet
, ~0);
1371 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1374 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1375 free_rom
, free_rom_bus
);
1377 log_selfids(ohci
->node_id
, generation
,
1378 self_id_count
, ohci
->self_id_buffer
);
1380 fw_core_handle_bus_reset(&ohci
->card
, ohci
->node_id
, generation
,
1381 self_id_count
, ohci
->self_id_buffer
);
1384 static irqreturn_t
irq_handler(int irq
, void *data
)
1386 struct fw_ohci
*ohci
= data
;
1387 u32 event
, iso_event
, cycle_time
;
1390 event
= reg_read(ohci
, OHCI1394_IntEventClear
);
1392 if (!event
|| !~event
)
1395 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1396 reg_write(ohci
, OHCI1394_IntEventClear
, event
& ~OHCI1394_busReset
);
1399 if (event
& OHCI1394_selfIDComplete
)
1400 tasklet_schedule(&ohci
->bus_reset_tasklet
);
1402 if (event
& OHCI1394_RQPkt
)
1403 tasklet_schedule(&ohci
->ar_request_ctx
.tasklet
);
1405 if (event
& OHCI1394_RSPkt
)
1406 tasklet_schedule(&ohci
->ar_response_ctx
.tasklet
);
1408 if (event
& OHCI1394_reqTxComplete
)
1409 tasklet_schedule(&ohci
->at_request_ctx
.tasklet
);
1411 if (event
& OHCI1394_respTxComplete
)
1412 tasklet_schedule(&ohci
->at_response_ctx
.tasklet
);
1414 iso_event
= reg_read(ohci
, OHCI1394_IsoRecvIntEventClear
);
1415 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, iso_event
);
1418 i
= ffs(iso_event
) - 1;
1419 tasklet_schedule(&ohci
->ir_context_list
[i
].context
.tasklet
);
1420 iso_event
&= ~(1 << i
);
1423 iso_event
= reg_read(ohci
, OHCI1394_IsoXmitIntEventClear
);
1424 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, iso_event
);
1427 i
= ffs(iso_event
) - 1;
1428 tasklet_schedule(&ohci
->it_context_list
[i
].context
.tasklet
);
1429 iso_event
&= ~(1 << i
);
1432 if (unlikely(event
& OHCI1394_regAccessFail
))
1433 fw_error("Register access failure - "
1434 "please notify linux1394-devel@lists.sf.net\n");
1436 if (unlikely(event
& OHCI1394_postedWriteErr
))
1437 fw_error("PCI posted write error\n");
1439 if (unlikely(event
& OHCI1394_cycleTooLong
)) {
1440 if (printk_ratelimit())
1441 fw_notify("isochronous cycle too long\n");
1442 reg_write(ohci
, OHCI1394_LinkControlSet
,
1443 OHCI1394_LinkControl_cycleMaster
);
1446 if (unlikely(event
& OHCI1394_cycleInconsistent
)) {
1448 * We need to clear this event bit in order to make
1449 * cycleMatch isochronous I/O work. In theory we should
1450 * stop active cycleMatch iso contexts now and restart
1451 * them at least two cycles later. (FIXME?)
1453 if (printk_ratelimit())
1454 fw_notify("isochronous cycle inconsistent\n");
1457 if (event
& OHCI1394_cycle64Seconds
) {
1458 cycle_time
= reg_read(ohci
, OHCI1394_IsochronousCycleTimer
);
1459 if ((cycle_time
& 0x80000000) == 0)
1460 atomic_inc(&ohci
->bus_seconds
);
1466 static int software_reset(struct fw_ohci
*ohci
)
1470 reg_write(ohci
, OHCI1394_HCControlSet
, OHCI1394_HCControl_softReset
);
1472 for (i
= 0; i
< OHCI_LOOP_COUNT
; i
++) {
1473 if ((reg_read(ohci
, OHCI1394_HCControlSet
) &
1474 OHCI1394_HCControl_softReset
) == 0)
1482 static void copy_config_rom(__be32
*dest
, const __be32
*src
, size_t length
)
1484 size_t size
= length
* 4;
1486 memcpy(dest
, src
, size
);
1487 if (size
< CONFIG_ROM_SIZE
)
1488 memset(&dest
[length
], 0, CONFIG_ROM_SIZE
- size
);
1491 static int ohci_enable(struct fw_card
*card
,
1492 const __be32
*config_rom
, size_t length
)
1494 struct fw_ohci
*ohci
= fw_ohci(card
);
1495 struct pci_dev
*dev
= to_pci_dev(card
->device
);
1499 if (software_reset(ohci
)) {
1500 fw_error("Failed to reset ohci card.\n");
1505 * Now enable LPS, which we need in order to start accessing
1506 * most of the registers. In fact, on some cards (ALI M5251),
1507 * accessing registers in the SClk domain without LPS enabled
1508 * will lock up the machine. Wait 50msec to make sure we have
1509 * full link enabled. However, with some cards (well, at least
1510 * a JMicron PCIe card), we have to try again sometimes.
1512 reg_write(ohci
, OHCI1394_HCControlSet
,
1513 OHCI1394_HCControl_LPS
|
1514 OHCI1394_HCControl_postedWriteEnable
);
1517 for (lps
= 0, i
= 0; !lps
&& i
< 3; i
++) {
1519 lps
= reg_read(ohci
, OHCI1394_HCControlSet
) &
1520 OHCI1394_HCControl_LPS
;
1524 fw_error("Failed to set Link Power Status\n");
1528 reg_write(ohci
, OHCI1394_HCControlClear
,
1529 OHCI1394_HCControl_noByteSwapData
);
1531 reg_write(ohci
, OHCI1394_SelfIDBuffer
, ohci
->self_id_bus
);
1532 reg_write(ohci
, OHCI1394_LinkControlClear
,
1533 OHCI1394_LinkControl_rcvPhyPkt
);
1534 reg_write(ohci
, OHCI1394_LinkControlSet
,
1535 OHCI1394_LinkControl_rcvSelfID
|
1536 OHCI1394_LinkControl_cycleTimerEnable
|
1537 OHCI1394_LinkControl_cycleMaster
);
1539 reg_write(ohci
, OHCI1394_ATRetries
,
1540 OHCI1394_MAX_AT_REQ_RETRIES
|
1541 (OHCI1394_MAX_AT_RESP_RETRIES
<< 4) |
1542 (OHCI1394_MAX_PHYS_RESP_RETRIES
<< 8));
1544 ar_context_run(&ohci
->ar_request_ctx
);
1545 ar_context_run(&ohci
->ar_response_ctx
);
1547 reg_write(ohci
, OHCI1394_PhyUpperBound
, 0x00010000);
1548 reg_write(ohci
, OHCI1394_IntEventClear
, ~0);
1549 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
1550 reg_write(ohci
, OHCI1394_IntMaskSet
,
1551 OHCI1394_selfIDComplete
|
1552 OHCI1394_RQPkt
| OHCI1394_RSPkt
|
1553 OHCI1394_reqTxComplete
| OHCI1394_respTxComplete
|
1554 OHCI1394_isochRx
| OHCI1394_isochTx
|
1555 OHCI1394_postedWriteErr
| OHCI1394_cycleTooLong
|
1556 OHCI1394_cycleInconsistent
|
1557 OHCI1394_cycle64Seconds
| OHCI1394_regAccessFail
|
1558 OHCI1394_masterIntEnable
);
1559 if (param_debug
& OHCI_PARAM_DEBUG_BUSRESETS
)
1560 reg_write(ohci
, OHCI1394_IntMaskSet
, OHCI1394_busReset
);
1562 /* Activate link_on bit and contender bit in our self ID packets.*/
1563 if (ohci_update_phy_reg(card
, 4, 0,
1564 PHY_LINK_ACTIVE
| PHY_CONTENDER
) < 0)
1568 * When the link is not yet enabled, the atomic config rom
1569 * update mechanism described below in ohci_set_config_rom()
1570 * is not active. We have to update ConfigRomHeader and
1571 * BusOptions manually, and the write to ConfigROMmap takes
1572 * effect immediately. We tie this to the enabling of the
1573 * link, so we have a valid config rom before enabling - the
1574 * OHCI requires that ConfigROMhdr and BusOptions have valid
1575 * values before enabling.
1577 * However, when the ConfigROMmap is written, some controllers
1578 * always read back quadlets 0 and 2 from the config rom to
1579 * the ConfigRomHeader and BusOptions registers on bus reset.
1580 * They shouldn't do that in this initial case where the link
1581 * isn't enabled. This means we have to use the same
1582 * workaround here, setting the bus header to 0 and then write
1583 * the right values in the bus reset tasklet.
1587 ohci
->next_config_rom
=
1588 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1589 &ohci
->next_config_rom_bus
,
1591 if (ohci
->next_config_rom
== NULL
)
1594 copy_config_rom(ohci
->next_config_rom
, config_rom
, length
);
1597 * In the suspend case, config_rom is NULL, which
1598 * means that we just reuse the old config rom.
1600 ohci
->next_config_rom
= ohci
->config_rom
;
1601 ohci
->next_config_rom_bus
= ohci
->config_rom_bus
;
1604 ohci
->next_header
= ohci
->next_config_rom
[0];
1605 ohci
->next_config_rom
[0] = 0;
1606 reg_write(ohci
, OHCI1394_ConfigROMhdr
, 0);
1607 reg_write(ohci
, OHCI1394_BusOptions
,
1608 be32_to_cpu(ohci
->next_config_rom
[2]));
1609 reg_write(ohci
, OHCI1394_ConfigROMmap
, ohci
->next_config_rom_bus
);
1611 reg_write(ohci
, OHCI1394_AsReqFilterHiSet
, 0x80000000);
1613 if (request_irq(dev
->irq
, irq_handler
,
1614 IRQF_SHARED
, ohci_driver_name
, ohci
)) {
1615 fw_error("Failed to allocate shared interrupt %d.\n",
1617 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1618 ohci
->config_rom
, ohci
->config_rom_bus
);
1622 reg_write(ohci
, OHCI1394_HCControlSet
,
1623 OHCI1394_HCControl_linkEnable
|
1624 OHCI1394_HCControl_BIBimageValid
);
1628 * We are ready to go, initiate bus reset to finish the
1632 fw_core_initiate_bus_reset(&ohci
->card
, 1);
1637 static int ohci_set_config_rom(struct fw_card
*card
,
1638 const __be32
*config_rom
, size_t length
)
1640 struct fw_ohci
*ohci
;
1641 unsigned long flags
;
1643 __be32
*next_config_rom
;
1644 dma_addr_t
uninitialized_var(next_config_rom_bus
);
1646 ohci
= fw_ohci(card
);
1649 * When the OHCI controller is enabled, the config rom update
1650 * mechanism is a bit tricky, but easy enough to use. See
1651 * section 5.5.6 in the OHCI specification.
1653 * The OHCI controller caches the new config rom address in a
1654 * shadow register (ConfigROMmapNext) and needs a bus reset
1655 * for the changes to take place. When the bus reset is
1656 * detected, the controller loads the new values for the
1657 * ConfigRomHeader and BusOptions registers from the specified
1658 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1659 * shadow register. All automatically and atomically.
1661 * Now, there's a twist to this story. The automatic load of
1662 * ConfigRomHeader and BusOptions doesn't honor the
1663 * noByteSwapData bit, so with a be32 config rom, the
1664 * controller will load be32 values in to these registers
1665 * during the atomic update, even on litte endian
1666 * architectures. The workaround we use is to put a 0 in the
1667 * header quadlet; 0 is endian agnostic and means that the
1668 * config rom isn't ready yet. In the bus reset tasklet we
1669 * then set up the real values for the two registers.
1671 * We use ohci->lock to avoid racing with the code that sets
1672 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1676 dma_alloc_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1677 &next_config_rom_bus
, GFP_KERNEL
);
1678 if (next_config_rom
== NULL
)
1681 spin_lock_irqsave(&ohci
->lock
, flags
);
1683 if (ohci
->next_config_rom
== NULL
) {
1684 ohci
->next_config_rom
= next_config_rom
;
1685 ohci
->next_config_rom_bus
= next_config_rom_bus
;
1687 copy_config_rom(ohci
->next_config_rom
, config_rom
, length
);
1689 ohci
->next_header
= config_rom
[0];
1690 ohci
->next_config_rom
[0] = 0;
1692 reg_write(ohci
, OHCI1394_ConfigROMmap
,
1693 ohci
->next_config_rom_bus
);
1697 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1700 * Now initiate a bus reset to have the changes take
1701 * effect. We clean up the old config rom memory and DMA
1702 * mappings in the bus reset tasklet, since the OHCI
1703 * controller could need to access it before the bus reset
1707 fw_core_initiate_bus_reset(&ohci
->card
, 1);
1709 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
1710 next_config_rom
, next_config_rom_bus
);
1715 static void ohci_send_request(struct fw_card
*card
, struct fw_packet
*packet
)
1717 struct fw_ohci
*ohci
= fw_ohci(card
);
1719 at_context_transmit(&ohci
->at_request_ctx
, packet
);
1722 static void ohci_send_response(struct fw_card
*card
, struct fw_packet
*packet
)
1724 struct fw_ohci
*ohci
= fw_ohci(card
);
1726 at_context_transmit(&ohci
->at_response_ctx
, packet
);
1729 static int ohci_cancel_packet(struct fw_card
*card
, struct fw_packet
*packet
)
1731 struct fw_ohci
*ohci
= fw_ohci(card
);
1732 struct context
*ctx
= &ohci
->at_request_ctx
;
1733 struct driver_data
*driver_data
= packet
->driver_data
;
1736 tasklet_disable(&ctx
->tasklet
);
1738 if (packet
->ack
!= 0)
1741 if (packet
->payload_mapped
)
1742 dma_unmap_single(ohci
->card
.device
, packet
->payload_bus
,
1743 packet
->payload_length
, DMA_TO_DEVICE
);
1745 log_ar_at_event('T', packet
->speed
, packet
->header
, 0x20);
1746 driver_data
->packet
= NULL
;
1747 packet
->ack
= RCODE_CANCELLED
;
1748 packet
->callback(packet
, &ohci
->card
, packet
->ack
);
1751 tasklet_enable(&ctx
->tasklet
);
1756 static int ohci_enable_phys_dma(struct fw_card
*card
,
1757 int node_id
, int generation
)
1759 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1762 struct fw_ohci
*ohci
= fw_ohci(card
);
1763 unsigned long flags
;
1767 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1768 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1771 spin_lock_irqsave(&ohci
->lock
, flags
);
1773 if (ohci
->generation
!= generation
) {
1779 * Note, if the node ID contains a non-local bus ID, physical DMA is
1780 * enabled for _all_ nodes on remote buses.
1783 n
= (node_id
& 0xffc0) == LOCAL_BUS
? node_id
& 0x3f : 63;
1785 reg_write(ohci
, OHCI1394_PhyReqFilterLoSet
, 1 << n
);
1787 reg_write(ohci
, OHCI1394_PhyReqFilterHiSet
, 1 << (n
- 32));
1791 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1794 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1797 static u64
ohci_get_bus_time(struct fw_card
*card
)
1799 struct fw_ohci
*ohci
= fw_ohci(card
);
1803 cycle_time
= reg_read(ohci
, OHCI1394_IsochronousCycleTimer
);
1804 bus_time
= ((u64
)atomic_read(&ohci
->bus_seconds
) << 32) | cycle_time
;
1809 static void copy_iso_headers(struct iso_context
*ctx
, void *p
)
1811 int i
= ctx
->header_length
;
1813 if (i
+ ctx
->base
.header_size
> PAGE_SIZE
)
1817 * The iso header is byteswapped to little endian by
1818 * the controller, but the remaining header quadlets
1819 * are big endian. We want to present all the headers
1820 * as big endian, so we have to swap the first quadlet.
1822 if (ctx
->base
.header_size
> 0)
1823 *(u32
*) (ctx
->header
+ i
) = __swab32(*(u32
*) (p
+ 4));
1824 if (ctx
->base
.header_size
> 4)
1825 *(u32
*) (ctx
->header
+ i
+ 4) = __swab32(*(u32
*) p
);
1826 if (ctx
->base
.header_size
> 8)
1827 memcpy(ctx
->header
+ i
+ 8, p
+ 8, ctx
->base
.header_size
- 8);
1828 ctx
->header_length
+= ctx
->base
.header_size
;
1831 static int handle_ir_dualbuffer_packet(struct context
*context
,
1832 struct descriptor
*d
,
1833 struct descriptor
*last
)
1835 struct iso_context
*ctx
=
1836 container_of(context
, struct iso_context
, context
);
1837 struct db_descriptor
*db
= (struct db_descriptor
*) d
;
1839 size_t header_length
;
1842 if (db
->first_res_count
!= 0 && db
->second_res_count
!= 0) {
1843 if (ctx
->excess_bytes
<= le16_to_cpu(db
->second_req_count
)) {
1844 /* This descriptor isn't done yet, stop iteration. */
1847 ctx
->excess_bytes
-= le16_to_cpu(db
->second_req_count
);
1850 header_length
= le16_to_cpu(db
->first_req_count
) -
1851 le16_to_cpu(db
->first_res_count
);
1854 end
= p
+ header_length
;
1856 copy_iso_headers(ctx
, p
);
1857 ctx
->excess_bytes
+=
1858 (le32_to_cpu(*(__le32
*)(p
+ 4)) >> 16) & 0xffff;
1859 p
+= max(ctx
->base
.header_size
, (size_t)8);
1862 ctx
->excess_bytes
-= le16_to_cpu(db
->second_req_count
) -
1863 le16_to_cpu(db
->second_res_count
);
1865 if (le16_to_cpu(db
->control
) & DESCRIPTOR_IRQ_ALWAYS
) {
1866 ir_header
= (__le32
*) (db
+ 1);
1867 ctx
->base
.callback(&ctx
->base
,
1868 le32_to_cpu(ir_header
[0]) & 0xffff,
1869 ctx
->header_length
, ctx
->header
,
1870 ctx
->base
.callback_data
);
1871 ctx
->header_length
= 0;
1877 static int handle_ir_packet_per_buffer(struct context
*context
,
1878 struct descriptor
*d
,
1879 struct descriptor
*last
)
1881 struct iso_context
*ctx
=
1882 container_of(context
, struct iso_context
, context
);
1883 struct descriptor
*pd
;
1887 for (pd
= d
; pd
<= last
; pd
++) {
1888 if (pd
->transfer_status
)
1892 /* Descriptor(s) not done yet, stop iteration */
1896 copy_iso_headers(ctx
, p
);
1898 if (le16_to_cpu(last
->control
) & DESCRIPTOR_IRQ_ALWAYS
) {
1899 ir_header
= (__le32
*) p
;
1900 ctx
->base
.callback(&ctx
->base
,
1901 le32_to_cpu(ir_header
[0]) & 0xffff,
1902 ctx
->header_length
, ctx
->header
,
1903 ctx
->base
.callback_data
);
1904 ctx
->header_length
= 0;
1910 static int handle_it_packet(struct context
*context
,
1911 struct descriptor
*d
,
1912 struct descriptor
*last
)
1914 struct iso_context
*ctx
=
1915 container_of(context
, struct iso_context
, context
);
1917 struct descriptor
*pd
;
1919 for (pd
= d
; pd
<= last
; pd
++)
1920 if (pd
->transfer_status
)
1923 /* Descriptor(s) not done yet, stop iteration */
1926 i
= ctx
->header_length
;
1927 if (i
+ 4 < PAGE_SIZE
) {
1928 /* Present this value as big-endian to match the receive code */
1929 *(__be32
*)(ctx
->header
+ i
) = cpu_to_be32(
1930 ((u32
)le16_to_cpu(pd
->transfer_status
) << 16) |
1931 le16_to_cpu(pd
->res_count
));
1932 ctx
->header_length
+= 4;
1934 if (le16_to_cpu(last
->control
) & DESCRIPTOR_IRQ_ALWAYS
) {
1935 ctx
->base
.callback(&ctx
->base
, le16_to_cpu(last
->res_count
),
1936 ctx
->header_length
, ctx
->header
,
1937 ctx
->base
.callback_data
);
1938 ctx
->header_length
= 0;
1943 static struct fw_iso_context
*ohci_allocate_iso_context(struct fw_card
*card
,
1944 int type
, int channel
, size_t header_size
)
1946 struct fw_ohci
*ohci
= fw_ohci(card
);
1947 struct iso_context
*ctx
, *list
;
1948 descriptor_callback_t callback
;
1949 u64
*channels
, dont_care
= ~0ULL;
1951 unsigned long flags
;
1952 int index
, ret
= -ENOMEM
;
1954 if (type
== FW_ISO_CONTEXT_TRANSMIT
) {
1955 channels
= &dont_care
;
1956 mask
= &ohci
->it_context_mask
;
1957 list
= ohci
->it_context_list
;
1958 callback
= handle_it_packet
;
1960 channels
= &ohci
->ir_context_channels
;
1961 mask
= &ohci
->ir_context_mask
;
1962 list
= ohci
->ir_context_list
;
1963 if (ohci
->use_dualbuffer
)
1964 callback
= handle_ir_dualbuffer_packet
;
1966 callback
= handle_ir_packet_per_buffer
;
1969 spin_lock_irqsave(&ohci
->lock
, flags
);
1970 index
= *channels
& 1ULL << channel
? ffs(*mask
) - 1 : -1;
1972 *channels
&= ~(1ULL << channel
);
1973 *mask
&= ~(1 << index
);
1975 spin_unlock_irqrestore(&ohci
->lock
, flags
);
1978 return ERR_PTR(-EBUSY
);
1980 if (type
== FW_ISO_CONTEXT_TRANSMIT
)
1981 regs
= OHCI1394_IsoXmitContextBase(index
);
1983 regs
= OHCI1394_IsoRcvContextBase(index
);
1986 memset(ctx
, 0, sizeof(*ctx
));
1987 ctx
->header_length
= 0;
1988 ctx
->header
= (void *) __get_free_page(GFP_KERNEL
);
1989 if (ctx
->header
== NULL
)
1992 ret
= context_init(&ctx
->context
, ohci
, regs
, callback
);
1994 goto out_with_header
;
1999 free_page((unsigned long)ctx
->header
);
2001 spin_lock_irqsave(&ohci
->lock
, flags
);
2002 *mask
|= 1 << index
;
2003 spin_unlock_irqrestore(&ohci
->lock
, flags
);
2005 return ERR_PTR(ret
);
2008 static int ohci_start_iso(struct fw_iso_context
*base
,
2009 s32 cycle
, u32 sync
, u32 tags
)
2011 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2012 struct fw_ohci
*ohci
= ctx
->context
.ohci
;
2016 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
2017 index
= ctx
- ohci
->it_context_list
;
2020 match
= IT_CONTEXT_CYCLE_MATCH_ENABLE
|
2021 (cycle
& 0x7fff) << 16;
2023 reg_write(ohci
, OHCI1394_IsoXmitIntEventClear
, 1 << index
);
2024 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, 1 << index
);
2025 context_run(&ctx
->context
, match
);
2027 index
= ctx
- ohci
->ir_context_list
;
2028 control
= IR_CONTEXT_ISOCH_HEADER
;
2029 if (ohci
->use_dualbuffer
)
2030 control
|= IR_CONTEXT_DUAL_BUFFER_MODE
;
2031 match
= (tags
<< 28) | (sync
<< 8) | ctx
->base
.channel
;
2033 match
|= (cycle
& 0x07fff) << 12;
2034 control
|= IR_CONTEXT_CYCLE_MATCH_ENABLE
;
2037 reg_write(ohci
, OHCI1394_IsoRecvIntEventClear
, 1 << index
);
2038 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, 1 << index
);
2039 reg_write(ohci
, CONTEXT_MATCH(ctx
->context
.regs
), match
);
2040 context_run(&ctx
->context
, control
);
2046 static int ohci_stop_iso(struct fw_iso_context
*base
)
2048 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
2049 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2052 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
2053 index
= ctx
- ohci
->it_context_list
;
2054 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, 1 << index
);
2056 index
= ctx
- ohci
->ir_context_list
;
2057 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, 1 << index
);
2060 context_stop(&ctx
->context
);
2065 static void ohci_free_iso_context(struct fw_iso_context
*base
)
2067 struct fw_ohci
*ohci
= fw_ohci(base
->card
);
2068 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2069 unsigned long flags
;
2072 ohci_stop_iso(base
);
2073 context_release(&ctx
->context
);
2074 free_page((unsigned long)ctx
->header
);
2076 spin_lock_irqsave(&ohci
->lock
, flags
);
2078 if (ctx
->base
.type
== FW_ISO_CONTEXT_TRANSMIT
) {
2079 index
= ctx
- ohci
->it_context_list
;
2080 ohci
->it_context_mask
|= 1 << index
;
2082 index
= ctx
- ohci
->ir_context_list
;
2083 ohci
->ir_context_mask
|= 1 << index
;
2084 ohci
->ir_context_channels
|= 1ULL << base
->channel
;
2087 spin_unlock_irqrestore(&ohci
->lock
, flags
);
2090 static int ohci_queue_iso_transmit(struct fw_iso_context
*base
,
2091 struct fw_iso_packet
*packet
,
2092 struct fw_iso_buffer
*buffer
,
2093 unsigned long payload
)
2095 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2096 struct descriptor
*d
, *last
, *pd
;
2097 struct fw_iso_packet
*p
;
2099 dma_addr_t d_bus
, page_bus
;
2100 u32 z
, header_z
, payload_z
, irq
;
2101 u32 payload_index
, payload_end_index
, next_page_index
;
2102 int page
, end_page
, i
, length
, offset
;
2105 payload_index
= payload
;
2111 if (p
->header_length
> 0)
2114 /* Determine the first page the payload isn't contained in. */
2115 end_page
= PAGE_ALIGN(payload_index
+ p
->payload_length
) >> PAGE_SHIFT
;
2116 if (p
->payload_length
> 0)
2117 payload_z
= end_page
- (payload_index
>> PAGE_SHIFT
);
2123 /* Get header size in number of descriptors. */
2124 header_z
= DIV_ROUND_UP(p
->header_length
, sizeof(*d
));
2126 d
= context_get_descriptors(&ctx
->context
, z
+ header_z
, &d_bus
);
2131 d
[0].control
= cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE
);
2132 d
[0].req_count
= cpu_to_le16(8);
2134 * Link the skip address to this descriptor itself. This causes
2135 * a context to skip a cycle whenever lost cycles or FIFO
2136 * overruns occur, without dropping the data. The application
2137 * should then decide whether this is an error condition or not.
2138 * FIXME: Make the context's cycle-lost behaviour configurable?
2140 d
[0].branch_address
= cpu_to_le32(d_bus
| z
);
2142 header
= (__le32
*) &d
[1];
2143 header
[0] = cpu_to_le32(IT_HEADER_SY(p
->sy
) |
2144 IT_HEADER_TAG(p
->tag
) |
2145 IT_HEADER_TCODE(TCODE_STREAM_DATA
) |
2146 IT_HEADER_CHANNEL(ctx
->base
.channel
) |
2147 IT_HEADER_SPEED(ctx
->base
.speed
));
2149 cpu_to_le32(IT_HEADER_DATA_LENGTH(p
->header_length
+
2150 p
->payload_length
));
2153 if (p
->header_length
> 0) {
2154 d
[2].req_count
= cpu_to_le16(p
->header_length
);
2155 d
[2].data_address
= cpu_to_le32(d_bus
+ z
* sizeof(*d
));
2156 memcpy(&d
[z
], p
->header
, p
->header_length
);
2159 pd
= d
+ z
- payload_z
;
2160 payload_end_index
= payload_index
+ p
->payload_length
;
2161 for (i
= 0; i
< payload_z
; i
++) {
2162 page
= payload_index
>> PAGE_SHIFT
;
2163 offset
= payload_index
& ~PAGE_MASK
;
2164 next_page_index
= (page
+ 1) << PAGE_SHIFT
;
2166 min(next_page_index
, payload_end_index
) - payload_index
;
2167 pd
[i
].req_count
= cpu_to_le16(length
);
2169 page_bus
= page_private(buffer
->pages
[page
]);
2170 pd
[i
].data_address
= cpu_to_le32(page_bus
+ offset
);
2172 payload_index
+= length
;
2176 irq
= DESCRIPTOR_IRQ_ALWAYS
;
2178 irq
= DESCRIPTOR_NO_IRQ
;
2180 last
= z
== 2 ? d
: d
+ z
- 1;
2181 last
->control
|= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST
|
2183 DESCRIPTOR_BRANCH_ALWAYS
|
2186 context_append(&ctx
->context
, d
, z
, header_z
);
2191 static int ohci_queue_iso_receive_dualbuffer(struct fw_iso_context
*base
,
2192 struct fw_iso_packet
*packet
,
2193 struct fw_iso_buffer
*buffer
,
2194 unsigned long payload
)
2196 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2197 struct db_descriptor
*db
= NULL
;
2198 struct descriptor
*d
;
2199 struct fw_iso_packet
*p
;
2200 dma_addr_t d_bus
, page_bus
;
2201 u32 z
, header_z
, length
, rest
;
2202 int page
, offset
, packet_count
, header_size
;
2205 * FIXME: Cycle lost behavior should be configurable: lose
2206 * packet, retransmit or terminate..
2213 * The OHCI controller puts the isochronous header and trailer in the
2214 * buffer, so we need at least 8 bytes.
2216 packet_count
= p
->header_length
/ ctx
->base
.header_size
;
2217 header_size
= packet_count
* max(ctx
->base
.header_size
, (size_t)8);
2219 /* Get header size in number of descriptors. */
2220 header_z
= DIV_ROUND_UP(header_size
, sizeof(*d
));
2221 page
= payload
>> PAGE_SHIFT
;
2222 offset
= payload
& ~PAGE_MASK
;
2223 rest
= p
->payload_length
;
2225 * The controllers I've tested have not worked correctly when
2226 * second_req_count is zero. Rather than do something we know won't
2227 * work, return an error
2233 d
= context_get_descriptors(&ctx
->context
,
2234 z
+ header_z
, &d_bus
);
2238 db
= (struct db_descriptor
*) d
;
2239 db
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
2240 DESCRIPTOR_BRANCH_ALWAYS
);
2242 cpu_to_le16(max(ctx
->base
.header_size
, (size_t)8));
2243 if (p
->skip
&& rest
== p
->payload_length
) {
2244 db
->control
|= cpu_to_le16(DESCRIPTOR_WAIT
);
2245 db
->first_req_count
= db
->first_size
;
2247 db
->first_req_count
= cpu_to_le16(header_size
);
2249 db
->first_res_count
= db
->first_req_count
;
2250 db
->first_buffer
= cpu_to_le32(d_bus
+ sizeof(*db
));
2252 if (p
->skip
&& rest
== p
->payload_length
)
2254 else if (offset
+ rest
< PAGE_SIZE
)
2257 length
= PAGE_SIZE
- offset
;
2259 db
->second_req_count
= cpu_to_le16(length
);
2260 db
->second_res_count
= db
->second_req_count
;
2261 page_bus
= page_private(buffer
->pages
[page
]);
2262 db
->second_buffer
= cpu_to_le32(page_bus
+ offset
);
2264 if (p
->interrupt
&& length
== rest
)
2265 db
->control
|= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS
);
2267 context_append(&ctx
->context
, d
, z
, header_z
);
2268 offset
= (offset
+ length
) & ~PAGE_MASK
;
2277 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context
*base
,
2278 struct fw_iso_packet
*packet
,
2279 struct fw_iso_buffer
*buffer
,
2280 unsigned long payload
)
2282 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2283 struct descriptor
*d
, *pd
;
2284 struct fw_iso_packet
*p
= packet
;
2285 dma_addr_t d_bus
, page_bus
;
2286 u32 z
, header_z
, rest
;
2288 int page
, offset
, packet_count
, header_size
, payload_per_buffer
;
2291 * The OHCI controller puts the isochronous header and trailer in the
2292 * buffer, so we need at least 8 bytes.
2294 packet_count
= p
->header_length
/ ctx
->base
.header_size
;
2295 header_size
= max(ctx
->base
.header_size
, (size_t)8);
2297 /* Get header size in number of descriptors. */
2298 header_z
= DIV_ROUND_UP(header_size
, sizeof(*d
));
2299 page
= payload
>> PAGE_SHIFT
;
2300 offset
= payload
& ~PAGE_MASK
;
2301 payload_per_buffer
= p
->payload_length
/ packet_count
;
2303 for (i
= 0; i
< packet_count
; i
++) {
2304 /* d points to the header descriptor */
2305 z
= DIV_ROUND_UP(payload_per_buffer
+ offset
, PAGE_SIZE
) + 1;
2306 d
= context_get_descriptors(&ctx
->context
,
2307 z
+ header_z
, &d_bus
);
2311 d
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
2312 DESCRIPTOR_INPUT_MORE
);
2313 if (p
->skip
&& i
== 0)
2314 d
->control
|= cpu_to_le16(DESCRIPTOR_WAIT
);
2315 d
->req_count
= cpu_to_le16(header_size
);
2316 d
->res_count
= d
->req_count
;
2317 d
->transfer_status
= 0;
2318 d
->data_address
= cpu_to_le32(d_bus
+ (z
* sizeof(*d
)));
2320 rest
= payload_per_buffer
;
2322 for (j
= 1; j
< z
; j
++) {
2324 pd
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
2325 DESCRIPTOR_INPUT_MORE
);
2327 if (offset
+ rest
< PAGE_SIZE
)
2330 length
= PAGE_SIZE
- offset
;
2331 pd
->req_count
= cpu_to_le16(length
);
2332 pd
->res_count
= pd
->req_count
;
2333 pd
->transfer_status
= 0;
2335 page_bus
= page_private(buffer
->pages
[page
]);
2336 pd
->data_address
= cpu_to_le32(page_bus
+ offset
);
2338 offset
= (offset
+ length
) & ~PAGE_MASK
;
2343 pd
->control
= cpu_to_le16(DESCRIPTOR_STATUS
|
2344 DESCRIPTOR_INPUT_LAST
|
2345 DESCRIPTOR_BRANCH_ALWAYS
);
2346 if (p
->interrupt
&& i
== packet_count
- 1)
2347 pd
->control
|= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS
);
2349 context_append(&ctx
->context
, d
, z
, header_z
);
2355 static int ohci_queue_iso(struct fw_iso_context
*base
,
2356 struct fw_iso_packet
*packet
,
2357 struct fw_iso_buffer
*buffer
,
2358 unsigned long payload
)
2360 struct iso_context
*ctx
= container_of(base
, struct iso_context
, base
);
2361 unsigned long flags
;
2364 spin_lock_irqsave(&ctx
->context
.ohci
->lock
, flags
);
2365 if (base
->type
== FW_ISO_CONTEXT_TRANSMIT
)
2366 ret
= ohci_queue_iso_transmit(base
, packet
, buffer
, payload
);
2367 else if (ctx
->context
.ohci
->use_dualbuffer
)
2368 ret
= ohci_queue_iso_receive_dualbuffer(base
, packet
,
2371 ret
= ohci_queue_iso_receive_packet_per_buffer(base
, packet
,
2373 spin_unlock_irqrestore(&ctx
->context
.ohci
->lock
, flags
);
2378 static const struct fw_card_driver ohci_driver
= {
2379 .enable
= ohci_enable
,
2380 .update_phy_reg
= ohci_update_phy_reg
,
2381 .set_config_rom
= ohci_set_config_rom
,
2382 .send_request
= ohci_send_request
,
2383 .send_response
= ohci_send_response
,
2384 .cancel_packet
= ohci_cancel_packet
,
2385 .enable_phys_dma
= ohci_enable_phys_dma
,
2386 .get_bus_time
= ohci_get_bus_time
,
2388 .allocate_iso_context
= ohci_allocate_iso_context
,
2389 .free_iso_context
= ohci_free_iso_context
,
2390 .queue_iso
= ohci_queue_iso
,
2391 .start_iso
= ohci_start_iso
,
2392 .stop_iso
= ohci_stop_iso
,
2395 #ifdef CONFIG_PPC_PMAC
2396 static void ohci_pmac_on(struct pci_dev
*dev
)
2398 if (machine_is(powermac
)) {
2399 struct device_node
*ofn
= pci_device_to_OF_node(dev
);
2402 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER
, ofn
, 0, 1);
2403 pmac_call_feature(PMAC_FTR_1394_ENABLE
, ofn
, 0, 1);
2408 static void ohci_pmac_off(struct pci_dev
*dev
)
2410 if (machine_is(powermac
)) {
2411 struct device_node
*ofn
= pci_device_to_OF_node(dev
);
2414 pmac_call_feature(PMAC_FTR_1394_ENABLE
, ofn
, 0, 0);
2415 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER
, ofn
, 0, 0);
2420 #define ohci_pmac_on(dev)
2421 #define ohci_pmac_off(dev)
2422 #endif /* CONFIG_PPC_PMAC */
2424 #define PCI_VENDOR_ID_AGERE PCI_VENDOR_ID_ATT
2425 #define PCI_DEVICE_ID_AGERE_FW643 0x5901
2426 #define PCI_DEVICE_ID_TI_TSB43AB23 0x8024
2428 static int __devinit
pci_probe(struct pci_dev
*dev
,
2429 const struct pci_device_id
*ent
)
2431 struct fw_ohci
*ohci
;
2432 u32 bus_options
, max_receive
, link_speed
, version
;
2437 ohci
= kzalloc(sizeof(*ohci
), GFP_KERNEL
);
2443 fw_card_initialize(&ohci
->card
, &ohci_driver
, &dev
->dev
);
2447 err
= pci_enable_device(dev
);
2449 fw_error("Failed to enable OHCI hardware\n");
2453 pci_set_master(dev
);
2454 pci_write_config_dword(dev
, OHCI1394_PCI_HCI_Control
, 0);
2455 pci_set_drvdata(dev
, ohci
);
2457 spin_lock_init(&ohci
->lock
);
2459 tasklet_init(&ohci
->bus_reset_tasklet
,
2460 bus_reset_tasklet
, (unsigned long)ohci
);
2462 err
= pci_request_region(dev
, 0, ohci_driver_name
);
2464 fw_error("MMIO resource unavailable\n");
2468 ohci
->registers
= pci_iomap(dev
, 0, OHCI1394_REGISTER_SIZE
);
2469 if (ohci
->registers
== NULL
) {
2470 fw_error("Failed to remap registers\n");
2475 version
= reg_read(ohci
, OHCI1394_Version
) & 0x00ff00ff;
2477 /* FIXME: make it a context option or remove dual-buffer mode */
2478 ohci
->use_dualbuffer
= version
>= OHCI_VERSION_1_1
;
2481 /* dual-buffer mode is broken if more than one IR context is active */
2482 if (dev
->vendor
== PCI_VENDOR_ID_AGERE
&&
2483 dev
->device
== PCI_DEVICE_ID_AGERE_FW643
)
2484 ohci
->use_dualbuffer
= false;
2486 /* dual-buffer mode is broken */
2487 if (dev
->vendor
== PCI_VENDOR_ID_RICOH
&&
2488 dev
->device
== PCI_DEVICE_ID_RICOH_R5C832
)
2489 ohci
->use_dualbuffer
= false;
2491 /* x86-32 currently doesn't use highmem for dma_alloc_coherent */
2492 #if !defined(CONFIG_X86_32)
2493 /* dual-buffer mode is broken with descriptor addresses above 2G */
2494 if (dev
->vendor
== PCI_VENDOR_ID_TI
&&
2495 (dev
->device
== PCI_DEVICE_ID_TI_TSB43AB22
||
2496 dev
->device
== PCI_DEVICE_ID_TI_TSB43AB23
))
2497 ohci
->use_dualbuffer
= false;
2500 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2501 ohci
->old_uninorth
= dev
->vendor
== PCI_VENDOR_ID_APPLE
&&
2502 dev
->device
== PCI_DEVICE_ID_APPLE_UNI_N_FW
;
2504 ohci
->bus_reset_packet_quirk
= dev
->vendor
== PCI_VENDOR_ID_TI
;
2506 ar_context_init(&ohci
->ar_request_ctx
, ohci
,
2507 OHCI1394_AsReqRcvContextControlSet
);
2509 ar_context_init(&ohci
->ar_response_ctx
, ohci
,
2510 OHCI1394_AsRspRcvContextControlSet
);
2512 context_init(&ohci
->at_request_ctx
, ohci
,
2513 OHCI1394_AsReqTrContextControlSet
, handle_at_packet
);
2515 context_init(&ohci
->at_response_ctx
, ohci
,
2516 OHCI1394_AsRspTrContextControlSet
, handle_at_packet
);
2518 reg_write(ohci
, OHCI1394_IsoRecvIntMaskSet
, ~0);
2519 ohci
->it_context_mask
= reg_read(ohci
, OHCI1394_IsoRecvIntMaskSet
);
2520 reg_write(ohci
, OHCI1394_IsoRecvIntMaskClear
, ~0);
2521 size
= sizeof(struct iso_context
) * hweight32(ohci
->it_context_mask
);
2522 ohci
->it_context_list
= kzalloc(size
, GFP_KERNEL
);
2524 reg_write(ohci
, OHCI1394_IsoXmitIntMaskSet
, ~0);
2525 ohci
->ir_context_channels
= ~0ULL;
2526 ohci
->ir_context_mask
= reg_read(ohci
, OHCI1394_IsoXmitIntMaskSet
);
2527 reg_write(ohci
, OHCI1394_IsoXmitIntMaskClear
, ~0);
2528 size
= sizeof(struct iso_context
) * hweight32(ohci
->ir_context_mask
);
2529 ohci
->ir_context_list
= kzalloc(size
, GFP_KERNEL
);
2531 if (ohci
->it_context_list
== NULL
|| ohci
->ir_context_list
== NULL
) {
2536 /* self-id dma buffer allocation */
2537 ohci
->self_id_cpu
= dma_alloc_coherent(ohci
->card
.device
,
2541 if (ohci
->self_id_cpu
== NULL
) {
2546 bus_options
= reg_read(ohci
, OHCI1394_BusOptions
);
2547 max_receive
= (bus_options
>> 12) & 0xf;
2548 link_speed
= bus_options
& 0x7;
2549 guid
= ((u64
) reg_read(ohci
, OHCI1394_GUIDHi
) << 32) |
2550 reg_read(ohci
, OHCI1394_GUIDLo
);
2552 err
= fw_card_add(&ohci
->card
, max_receive
, link_speed
, guid
);
2556 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2557 dev_name(&dev
->dev
), version
>> 16, version
& 0xff);
2562 dma_free_coherent(ohci
->card
.device
, SELF_ID_BUF_SIZE
,
2563 ohci
->self_id_cpu
, ohci
->self_id_bus
);
2565 kfree(ohci
->ir_context_list
);
2566 kfree(ohci
->it_context_list
);
2567 context_release(&ohci
->at_response_ctx
);
2568 context_release(&ohci
->at_request_ctx
);
2569 ar_context_release(&ohci
->ar_response_ctx
);
2570 ar_context_release(&ohci
->ar_request_ctx
);
2571 pci_iounmap(dev
, ohci
->registers
);
2573 pci_release_region(dev
, 0);
2575 pci_disable_device(dev
);
2581 fw_error("Out of memory\n");
2586 static void pci_remove(struct pci_dev
*dev
)
2588 struct fw_ohci
*ohci
;
2590 ohci
= pci_get_drvdata(dev
);
2591 reg_write(ohci
, OHCI1394_IntMaskClear
, ~0);
2593 fw_core_remove_card(&ohci
->card
);
2596 * FIXME: Fail all pending packets here, now that the upper
2597 * layers can't queue any more.
2600 software_reset(ohci
);
2601 free_irq(dev
->irq
, ohci
);
2603 if (ohci
->next_config_rom
&& ohci
->next_config_rom
!= ohci
->config_rom
)
2604 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
2605 ohci
->next_config_rom
, ohci
->next_config_rom_bus
);
2606 if (ohci
->config_rom
)
2607 dma_free_coherent(ohci
->card
.device
, CONFIG_ROM_SIZE
,
2608 ohci
->config_rom
, ohci
->config_rom_bus
);
2609 dma_free_coherent(ohci
->card
.device
, SELF_ID_BUF_SIZE
,
2610 ohci
->self_id_cpu
, ohci
->self_id_bus
);
2611 ar_context_release(&ohci
->ar_request_ctx
);
2612 ar_context_release(&ohci
->ar_response_ctx
);
2613 context_release(&ohci
->at_request_ctx
);
2614 context_release(&ohci
->at_response_ctx
);
2615 kfree(ohci
->it_context_list
);
2616 kfree(ohci
->ir_context_list
);
2617 pci_iounmap(dev
, ohci
->registers
);
2618 pci_release_region(dev
, 0);
2619 pci_disable_device(dev
);
2623 fw_notify("Removed fw-ohci device.\n");
2627 static int pci_suspend(struct pci_dev
*dev
, pm_message_t state
)
2629 struct fw_ohci
*ohci
= pci_get_drvdata(dev
);
2632 software_reset(ohci
);
2633 free_irq(dev
->irq
, ohci
);
2634 err
= pci_save_state(dev
);
2636 fw_error("pci_save_state failed\n");
2639 err
= pci_set_power_state(dev
, pci_choose_state(dev
, state
));
2641 fw_error("pci_set_power_state failed with %d\n", err
);
2647 static int pci_resume(struct pci_dev
*dev
)
2649 struct fw_ohci
*ohci
= pci_get_drvdata(dev
);
2653 pci_set_power_state(dev
, PCI_D0
);
2654 pci_restore_state(dev
);
2655 err
= pci_enable_device(dev
);
2657 fw_error("pci_enable_device failed\n");
2661 return ohci_enable(&ohci
->card
, NULL
, 0);
2665 static struct pci_device_id pci_table
[] = {
2666 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI
, ~0) },
2670 MODULE_DEVICE_TABLE(pci
, pci_table
);
2672 static struct pci_driver fw_ohci_pci_driver
= {
2673 .name
= ohci_driver_name
,
2674 .id_table
= pci_table
,
2676 .remove
= pci_remove
,
2678 .resume
= pci_resume
,
2679 .suspend
= pci_suspend
,
2683 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2684 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2685 MODULE_LICENSE("GPL");
2687 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2688 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2689 MODULE_ALIAS("ohci1394");
2692 static int __init
fw_ohci_init(void)
2694 return pci_register_driver(&fw_ohci_pci_driver
);
2697 static void __exit
fw_ohci_cleanup(void)
2699 pci_unregister_driver(&fw_ohci_pci_driver
);
2702 module_init(fw_ohci_init
);
2703 module_exit(fw_ohci_cleanup
);