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Merge tag 'v2.6.39-rc7'
[deliverable/linux.git] / drivers / firewire / ohci.c
1 /*
2 * Driver for OHCI 1394 controllers
3 *
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include <linux/bitops.h>
22 #include <linux/bug.h>
23 #include <linux/compiler.h>
24 #include <linux/delay.h>
25 #include <linux/device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/firewire.h>
28 #include <linux/firewire-constants.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/io.h>
32 #include <linux/kernel.h>
33 #include <linux/list.h>
34 #include <linux/mm.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mutex.h>
38 #include <linux/pci.h>
39 #include <linux/pci_ids.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/string.h>
43 #include <linux/time.h>
44 #include <linux/vmalloc.h>
45
46 #include <asm/byteorder.h>
47 #include <asm/page.h>
48 #include <asm/system.h>
49
50 #ifdef CONFIG_PPC_PMAC
51 #include <asm/pmac_feature.h>
52 #endif
53
54 #include "core.h"
55 #include "ohci.h"
56
57 #define DESCRIPTOR_OUTPUT_MORE 0
58 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
59 #define DESCRIPTOR_INPUT_MORE (2 << 12)
60 #define DESCRIPTOR_INPUT_LAST (3 << 12)
61 #define DESCRIPTOR_STATUS (1 << 11)
62 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
63 #define DESCRIPTOR_PING (1 << 7)
64 #define DESCRIPTOR_YY (1 << 6)
65 #define DESCRIPTOR_NO_IRQ (0 << 4)
66 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
67 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
68 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
69 #define DESCRIPTOR_WAIT (3 << 0)
70
71 struct descriptor {
72 __le16 req_count;
73 __le16 control;
74 __le32 data_address;
75 __le32 branch_address;
76 __le16 res_count;
77 __le16 transfer_status;
78 } __attribute__((aligned(16)));
79
80 #define CONTROL_SET(regs) (regs)
81 #define CONTROL_CLEAR(regs) ((regs) + 4)
82 #define COMMAND_PTR(regs) ((regs) + 12)
83 #define CONTEXT_MATCH(regs) ((regs) + 16)
84
85 #define AR_BUFFER_SIZE (32*1024)
86 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
87 /* we need at least two pages for proper list management */
88 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
89
90 #define MAX_ASYNC_PAYLOAD 4096
91 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
92 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
93
94 struct ar_context {
95 struct fw_ohci *ohci;
96 struct page *pages[AR_BUFFERS];
97 void *buffer;
98 struct descriptor *descriptors;
99 dma_addr_t descriptors_bus;
100 void *pointer;
101 unsigned int last_buffer_index;
102 u32 regs;
103 struct tasklet_struct tasklet;
104 };
105
106 struct context;
107
108 typedef int (*descriptor_callback_t)(struct context *ctx,
109 struct descriptor *d,
110 struct descriptor *last);
111
112 /*
113 * A buffer that contains a block of DMA-able coherent memory used for
114 * storing a portion of a DMA descriptor program.
115 */
116 struct descriptor_buffer {
117 struct list_head list;
118 dma_addr_t buffer_bus;
119 size_t buffer_size;
120 size_t used;
121 struct descriptor buffer[0];
122 };
123
124 struct context {
125 struct fw_ohci *ohci;
126 u32 regs;
127 int total_allocation;
128 bool running;
129 bool flushing;
130
131 /*
132 * List of page-sized buffers for storing DMA descriptors.
133 * Head of list contains buffers in use and tail of list contains
134 * free buffers.
135 */
136 struct list_head buffer_list;
137
138 /*
139 * Pointer to a buffer inside buffer_list that contains the tail
140 * end of the current DMA program.
141 */
142 struct descriptor_buffer *buffer_tail;
143
144 /*
145 * The descriptor containing the branch address of the first
146 * descriptor that has not yet been filled by the device.
147 */
148 struct descriptor *last;
149
150 /*
151 * The last descriptor in the DMA program. It contains the branch
152 * address that must be updated upon appending a new descriptor.
153 */
154 struct descriptor *prev;
155
156 descriptor_callback_t callback;
157
158 struct tasklet_struct tasklet;
159 };
160
161 #define IT_HEADER_SY(v) ((v) << 0)
162 #define IT_HEADER_TCODE(v) ((v) << 4)
163 #define IT_HEADER_CHANNEL(v) ((v) << 8)
164 #define IT_HEADER_TAG(v) ((v) << 14)
165 #define IT_HEADER_SPEED(v) ((v) << 16)
166 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
167
168 struct iso_context {
169 struct fw_iso_context base;
170 struct context context;
171 int excess_bytes;
172 void *header;
173 size_t header_length;
174
175 u8 sync;
176 u8 tags;
177 };
178
179 #define CONFIG_ROM_SIZE 1024
180
181 struct fw_ohci {
182 struct fw_card card;
183
184 __iomem char *registers;
185 int node_id;
186 int generation;
187 int request_generation; /* for timestamping incoming requests */
188 unsigned quirks;
189 unsigned int pri_req_max;
190 u32 bus_time;
191 bool is_root;
192 bool csr_state_setclear_abdicate;
193 int n_ir;
194 int n_it;
195 /*
196 * Spinlock for accessing fw_ohci data. Never call out of
197 * this driver with this lock held.
198 */
199 spinlock_t lock;
200
201 struct mutex phy_reg_mutex;
202
203 void *misc_buffer;
204 dma_addr_t misc_buffer_bus;
205
206 struct ar_context ar_request_ctx;
207 struct ar_context ar_response_ctx;
208 struct context at_request_ctx;
209 struct context at_response_ctx;
210
211 u32 it_context_support;
212 u32 it_context_mask; /* unoccupied IT contexts */
213 struct iso_context *it_context_list;
214 u64 ir_context_channels; /* unoccupied channels */
215 u32 ir_context_support;
216 u32 ir_context_mask; /* unoccupied IR contexts */
217 struct iso_context *ir_context_list;
218 u64 mc_channels; /* channels in use by the multichannel IR context */
219 bool mc_allocated;
220
221 __be32 *config_rom;
222 dma_addr_t config_rom_bus;
223 __be32 *next_config_rom;
224 dma_addr_t next_config_rom_bus;
225 __be32 next_header;
226
227 __le32 *self_id_cpu;
228 dma_addr_t self_id_bus;
229 struct tasklet_struct bus_reset_tasklet;
230
231 u32 self_id_buffer[512];
232 };
233
234 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
235 {
236 return container_of(card, struct fw_ohci, card);
237 }
238
239 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
240 #define IR_CONTEXT_BUFFER_FILL 0x80000000
241 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
242 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
243 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
244 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
245
246 #define CONTEXT_RUN 0x8000
247 #define CONTEXT_WAKE 0x1000
248 #define CONTEXT_DEAD 0x0800
249 #define CONTEXT_ACTIVE 0x0400
250
251 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
252 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
253 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
254
255 #define OHCI1394_REGISTER_SIZE 0x800
256 #define OHCI_LOOP_COUNT 500
257 #define OHCI1394_PCI_HCI_Control 0x40
258 #define SELF_ID_BUF_SIZE 0x800
259 #define OHCI_TCODE_PHY_PACKET 0x0e
260 #define OHCI_VERSION_1_1 0x010010
261
262 static char ohci_driver_name[] = KBUILD_MODNAME;
263
264 #define PCI_DEVICE_ID_AGERE_FW643 0x5901
265 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
266 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
267
268 #define QUIRK_CYCLE_TIMER 1
269 #define QUIRK_RESET_PACKET 2
270 #define QUIRK_BE_HEADERS 4
271 #define QUIRK_NO_1394A 8
272 #define QUIRK_NO_MSI 16
273
274 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
275 static const struct {
276 unsigned short vendor, device, revision, flags;
277 } ohci_quirks[] = {
278 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
279 QUIRK_CYCLE_TIMER},
280
281 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
282 QUIRK_BE_HEADERS},
283
284 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
285 QUIRK_NO_MSI},
286
287 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
288 QUIRK_NO_MSI},
289
290 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
291 QUIRK_CYCLE_TIMER},
292
293 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
294 QUIRK_CYCLE_TIMER},
295
296 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
297 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
298
299 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
300 QUIRK_RESET_PACKET},
301
302 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
303 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
304 };
305
306 /* This overrides anything that was found in ohci_quirks[]. */
307 static int param_quirks;
308 module_param_named(quirks, param_quirks, int, 0644);
309 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
310 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
311 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
312 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
313 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
314 ", disable MSI = " __stringify(QUIRK_NO_MSI)
315 ")");
316
317 #define OHCI_PARAM_DEBUG_AT_AR 1
318 #define OHCI_PARAM_DEBUG_SELFIDS 2
319 #define OHCI_PARAM_DEBUG_IRQS 4
320 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
321
322 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
323
324 static int param_debug;
325 module_param_named(debug, param_debug, int, 0644);
326 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
327 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
328 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
329 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
330 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
331 ", or a combination, or all = -1)");
332
333 static void log_irqs(u32 evt)
334 {
335 if (likely(!(param_debug &
336 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
337 return;
338
339 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
340 !(evt & OHCI1394_busReset))
341 return;
342
343 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
344 evt & OHCI1394_selfIDComplete ? " selfID" : "",
345 evt & OHCI1394_RQPkt ? " AR_req" : "",
346 evt & OHCI1394_RSPkt ? " AR_resp" : "",
347 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
348 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
349 evt & OHCI1394_isochRx ? " IR" : "",
350 evt & OHCI1394_isochTx ? " IT" : "",
351 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
352 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
353 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
354 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
355 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
356 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
357 evt & OHCI1394_busReset ? " busReset" : "",
358 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
359 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
360 OHCI1394_respTxComplete | OHCI1394_isochRx |
361 OHCI1394_isochTx | OHCI1394_postedWriteErr |
362 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
363 OHCI1394_cycleInconsistent |
364 OHCI1394_regAccessFail | OHCI1394_busReset)
365 ? " ?" : "");
366 }
367
368 static const char *speed[] = {
369 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
370 };
371 static const char *power[] = {
372 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
373 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
374 };
375 static const char port[] = { '.', '-', 'p', 'c', };
376
377 static char _p(u32 *s, int shift)
378 {
379 return port[*s >> shift & 3];
380 }
381
382 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
383 {
384 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
385 return;
386
387 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
388 self_id_count, generation, node_id);
389
390 for (; self_id_count--; ++s)
391 if ((*s & 1 << 23) == 0)
392 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
393 "%s gc=%d %s %s%s%s\n",
394 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
395 speed[*s >> 14 & 3], *s >> 16 & 63,
396 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
397 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
398 else
399 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
400 *s, *s >> 24 & 63,
401 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
402 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
403 }
404
405 static const char *evts[] = {
406 [0x00] = "evt_no_status", [0x01] = "-reserved-",
407 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
408 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
409 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
410 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
411 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
412 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
413 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
414 [0x10] = "-reserved-", [0x11] = "ack_complete",
415 [0x12] = "ack_pending ", [0x13] = "-reserved-",
416 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
417 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
418 [0x18] = "-reserved-", [0x19] = "-reserved-",
419 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
420 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
421 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
422 [0x20] = "pending/cancelled",
423 };
424 static const char *tcodes[] = {
425 [0x0] = "QW req", [0x1] = "BW req",
426 [0x2] = "W resp", [0x3] = "-reserved-",
427 [0x4] = "QR req", [0x5] = "BR req",
428 [0x6] = "QR resp", [0x7] = "BR resp",
429 [0x8] = "cycle start", [0x9] = "Lk req",
430 [0xa] = "async stream packet", [0xb] = "Lk resp",
431 [0xc] = "-reserved-", [0xd] = "-reserved-",
432 [0xe] = "link internal", [0xf] = "-reserved-",
433 };
434
435 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
436 {
437 int tcode = header[0] >> 4 & 0xf;
438 char specific[12];
439
440 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
441 return;
442
443 if (unlikely(evt >= ARRAY_SIZE(evts)))
444 evt = 0x1f;
445
446 if (evt == OHCI1394_evt_bus_reset) {
447 fw_notify("A%c evt_bus_reset, generation %d\n",
448 dir, (header[2] >> 16) & 0xff);
449 return;
450 }
451
452 switch (tcode) {
453 case 0x0: case 0x6: case 0x8:
454 snprintf(specific, sizeof(specific), " = %08x",
455 be32_to_cpu((__force __be32)header[3]));
456 break;
457 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
458 snprintf(specific, sizeof(specific), " %x,%x",
459 header[3] >> 16, header[3] & 0xffff);
460 break;
461 default:
462 specific[0] = '\0';
463 }
464
465 switch (tcode) {
466 case 0xa:
467 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
468 break;
469 case 0xe:
470 fw_notify("A%c %s, PHY %08x %08x\n",
471 dir, evts[evt], header[1], header[2]);
472 break;
473 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
474 fw_notify("A%c spd %x tl %02x, "
475 "%04x -> %04x, %s, "
476 "%s, %04x%08x%s\n",
477 dir, speed, header[0] >> 10 & 0x3f,
478 header[1] >> 16, header[0] >> 16, evts[evt],
479 tcodes[tcode], header[1] & 0xffff, header[2], specific);
480 break;
481 default:
482 fw_notify("A%c spd %x tl %02x, "
483 "%04x -> %04x, %s, "
484 "%s%s\n",
485 dir, speed, header[0] >> 10 & 0x3f,
486 header[1] >> 16, header[0] >> 16, evts[evt],
487 tcodes[tcode], specific);
488 }
489 }
490
491 #else
492
493 #define param_debug 0
494 static inline void log_irqs(u32 evt) {}
495 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
496 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
497
498 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
499
500 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
501 {
502 writel(data, ohci->registers + offset);
503 }
504
505 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
506 {
507 return readl(ohci->registers + offset);
508 }
509
510 static inline void flush_writes(const struct fw_ohci *ohci)
511 {
512 /* Do a dummy read to flush writes. */
513 reg_read(ohci, OHCI1394_Version);
514 }
515
516 static int read_phy_reg(struct fw_ohci *ohci, int addr)
517 {
518 u32 val;
519 int i;
520
521 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
522 for (i = 0; i < 3 + 100; i++) {
523 val = reg_read(ohci, OHCI1394_PhyControl);
524 if (val & OHCI1394_PhyControl_ReadDone)
525 return OHCI1394_PhyControl_ReadData(val);
526
527 /*
528 * Try a few times without waiting. Sleeping is necessary
529 * only when the link/PHY interface is busy.
530 */
531 if (i >= 3)
532 msleep(1);
533 }
534 fw_error("failed to read phy reg\n");
535
536 return -EBUSY;
537 }
538
539 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
540 {
541 int i;
542
543 reg_write(ohci, OHCI1394_PhyControl,
544 OHCI1394_PhyControl_Write(addr, val));
545 for (i = 0; i < 3 + 100; i++) {
546 val = reg_read(ohci, OHCI1394_PhyControl);
547 if (!(val & OHCI1394_PhyControl_WritePending))
548 return 0;
549
550 if (i >= 3)
551 msleep(1);
552 }
553 fw_error("failed to write phy reg\n");
554
555 return -EBUSY;
556 }
557
558 static int update_phy_reg(struct fw_ohci *ohci, int addr,
559 int clear_bits, int set_bits)
560 {
561 int ret = read_phy_reg(ohci, addr);
562 if (ret < 0)
563 return ret;
564
565 /*
566 * The interrupt status bits are cleared by writing a one bit.
567 * Avoid clearing them unless explicitly requested in set_bits.
568 */
569 if (addr == 5)
570 clear_bits |= PHY_INT_STATUS_BITS;
571
572 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
573 }
574
575 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
576 {
577 int ret;
578
579 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
580 if (ret < 0)
581 return ret;
582
583 return read_phy_reg(ohci, addr);
584 }
585
586 static int ohci_read_phy_reg(struct fw_card *card, int addr)
587 {
588 struct fw_ohci *ohci = fw_ohci(card);
589 int ret;
590
591 mutex_lock(&ohci->phy_reg_mutex);
592 ret = read_phy_reg(ohci, addr);
593 mutex_unlock(&ohci->phy_reg_mutex);
594
595 return ret;
596 }
597
598 static int ohci_update_phy_reg(struct fw_card *card, int addr,
599 int clear_bits, int set_bits)
600 {
601 struct fw_ohci *ohci = fw_ohci(card);
602 int ret;
603
604 mutex_lock(&ohci->phy_reg_mutex);
605 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
606 mutex_unlock(&ohci->phy_reg_mutex);
607
608 return ret;
609 }
610
611 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
612 {
613 return page_private(ctx->pages[i]);
614 }
615
616 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
617 {
618 struct descriptor *d;
619
620 d = &ctx->descriptors[index];
621 d->branch_address &= cpu_to_le32(~0xf);
622 d->res_count = cpu_to_le16(PAGE_SIZE);
623 d->transfer_status = 0;
624
625 wmb(); /* finish init of new descriptors before branch_address update */
626 d = &ctx->descriptors[ctx->last_buffer_index];
627 d->branch_address |= cpu_to_le32(1);
628
629 ctx->last_buffer_index = index;
630
631 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
632 flush_writes(ctx->ohci);
633 }
634
635 static void ar_context_release(struct ar_context *ctx)
636 {
637 unsigned int i;
638
639 if (ctx->buffer)
640 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
641
642 for (i = 0; i < AR_BUFFERS; i++)
643 if (ctx->pages[i]) {
644 dma_unmap_page(ctx->ohci->card.device,
645 ar_buffer_bus(ctx, i),
646 PAGE_SIZE, DMA_FROM_DEVICE);
647 __free_page(ctx->pages[i]);
648 }
649 }
650
651 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
652 {
653 if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
654 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
655 flush_writes(ctx->ohci);
656
657 fw_error("AR error: %s; DMA stopped\n", error_msg);
658 }
659 /* FIXME: restart? */
660 }
661
662 static inline unsigned int ar_next_buffer_index(unsigned int index)
663 {
664 return (index + 1) % AR_BUFFERS;
665 }
666
667 static inline unsigned int ar_prev_buffer_index(unsigned int index)
668 {
669 return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
670 }
671
672 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
673 {
674 return ar_next_buffer_index(ctx->last_buffer_index);
675 }
676
677 /*
678 * We search for the buffer that contains the last AR packet DMA data written
679 * by the controller.
680 */
681 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
682 unsigned int *buffer_offset)
683 {
684 unsigned int i, next_i, last = ctx->last_buffer_index;
685 __le16 res_count, next_res_count;
686
687 i = ar_first_buffer_index(ctx);
688 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
689
690 /* A buffer that is not yet completely filled must be the last one. */
691 while (i != last && res_count == 0) {
692
693 /* Peek at the next descriptor. */
694 next_i = ar_next_buffer_index(i);
695 rmb(); /* read descriptors in order */
696 next_res_count = ACCESS_ONCE(
697 ctx->descriptors[next_i].res_count);
698 /*
699 * If the next descriptor is still empty, we must stop at this
700 * descriptor.
701 */
702 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
703 /*
704 * The exception is when the DMA data for one packet is
705 * split over three buffers; in this case, the middle
706 * buffer's descriptor might be never updated by the
707 * controller and look still empty, and we have to peek
708 * at the third one.
709 */
710 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
711 next_i = ar_next_buffer_index(next_i);
712 rmb();
713 next_res_count = ACCESS_ONCE(
714 ctx->descriptors[next_i].res_count);
715 if (next_res_count != cpu_to_le16(PAGE_SIZE))
716 goto next_buffer_is_active;
717 }
718
719 break;
720 }
721
722 next_buffer_is_active:
723 i = next_i;
724 res_count = next_res_count;
725 }
726
727 rmb(); /* read res_count before the DMA data */
728
729 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
730 if (*buffer_offset > PAGE_SIZE) {
731 *buffer_offset = 0;
732 ar_context_abort(ctx, "corrupted descriptor");
733 }
734
735 return i;
736 }
737
738 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
739 unsigned int end_buffer_index,
740 unsigned int end_buffer_offset)
741 {
742 unsigned int i;
743
744 i = ar_first_buffer_index(ctx);
745 while (i != end_buffer_index) {
746 dma_sync_single_for_cpu(ctx->ohci->card.device,
747 ar_buffer_bus(ctx, i),
748 PAGE_SIZE, DMA_FROM_DEVICE);
749 i = ar_next_buffer_index(i);
750 }
751 if (end_buffer_offset > 0)
752 dma_sync_single_for_cpu(ctx->ohci->card.device,
753 ar_buffer_bus(ctx, i),
754 end_buffer_offset, DMA_FROM_DEVICE);
755 }
756
757 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
758 #define cond_le32_to_cpu(v) \
759 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
760 #else
761 #define cond_le32_to_cpu(v) le32_to_cpu(v)
762 #endif
763
764 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
765 {
766 struct fw_ohci *ohci = ctx->ohci;
767 struct fw_packet p;
768 u32 status, length, tcode;
769 int evt;
770
771 p.header[0] = cond_le32_to_cpu(buffer[0]);
772 p.header[1] = cond_le32_to_cpu(buffer[1]);
773 p.header[2] = cond_le32_to_cpu(buffer[2]);
774
775 tcode = (p.header[0] >> 4) & 0x0f;
776 switch (tcode) {
777 case TCODE_WRITE_QUADLET_REQUEST:
778 case TCODE_READ_QUADLET_RESPONSE:
779 p.header[3] = (__force __u32) buffer[3];
780 p.header_length = 16;
781 p.payload_length = 0;
782 break;
783
784 case TCODE_READ_BLOCK_REQUEST :
785 p.header[3] = cond_le32_to_cpu(buffer[3]);
786 p.header_length = 16;
787 p.payload_length = 0;
788 break;
789
790 case TCODE_WRITE_BLOCK_REQUEST:
791 case TCODE_READ_BLOCK_RESPONSE:
792 case TCODE_LOCK_REQUEST:
793 case TCODE_LOCK_RESPONSE:
794 p.header[3] = cond_le32_to_cpu(buffer[3]);
795 p.header_length = 16;
796 p.payload_length = p.header[3] >> 16;
797 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
798 ar_context_abort(ctx, "invalid packet length");
799 return NULL;
800 }
801 break;
802
803 case TCODE_WRITE_RESPONSE:
804 case TCODE_READ_QUADLET_REQUEST:
805 case OHCI_TCODE_PHY_PACKET:
806 p.header_length = 12;
807 p.payload_length = 0;
808 break;
809
810 default:
811 ar_context_abort(ctx, "invalid tcode");
812 return NULL;
813 }
814
815 p.payload = (void *) buffer + p.header_length;
816
817 /* FIXME: What to do about evt_* errors? */
818 length = (p.header_length + p.payload_length + 3) / 4;
819 status = cond_le32_to_cpu(buffer[length]);
820 evt = (status >> 16) & 0x1f;
821
822 p.ack = evt - 16;
823 p.speed = (status >> 21) & 0x7;
824 p.timestamp = status & 0xffff;
825 p.generation = ohci->request_generation;
826
827 log_ar_at_event('R', p.speed, p.header, evt);
828
829 /*
830 * Several controllers, notably from NEC and VIA, forget to
831 * write ack_complete status at PHY packet reception.
832 */
833 if (evt == OHCI1394_evt_no_status &&
834 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
835 p.ack = ACK_COMPLETE;
836
837 /*
838 * The OHCI bus reset handler synthesizes a PHY packet with
839 * the new generation number when a bus reset happens (see
840 * section 8.4.2.3). This helps us determine when a request
841 * was received and make sure we send the response in the same
842 * generation. We only need this for requests; for responses
843 * we use the unique tlabel for finding the matching
844 * request.
845 *
846 * Alas some chips sometimes emit bus reset packets with a
847 * wrong generation. We set the correct generation for these
848 * at a slightly incorrect time (in bus_reset_tasklet).
849 */
850 if (evt == OHCI1394_evt_bus_reset) {
851 if (!(ohci->quirks & QUIRK_RESET_PACKET))
852 ohci->request_generation = (p.header[2] >> 16) & 0xff;
853 } else if (ctx == &ohci->ar_request_ctx) {
854 fw_core_handle_request(&ohci->card, &p);
855 } else {
856 fw_core_handle_response(&ohci->card, &p);
857 }
858
859 return buffer + length + 1;
860 }
861
862 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
863 {
864 void *next;
865
866 while (p < end) {
867 next = handle_ar_packet(ctx, p);
868 if (!next)
869 return p;
870 p = next;
871 }
872
873 return p;
874 }
875
876 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
877 {
878 unsigned int i;
879
880 i = ar_first_buffer_index(ctx);
881 while (i != end_buffer) {
882 dma_sync_single_for_device(ctx->ohci->card.device,
883 ar_buffer_bus(ctx, i),
884 PAGE_SIZE, DMA_FROM_DEVICE);
885 ar_context_link_page(ctx, i);
886 i = ar_next_buffer_index(i);
887 }
888 }
889
890 static void ar_context_tasklet(unsigned long data)
891 {
892 struct ar_context *ctx = (struct ar_context *)data;
893 unsigned int end_buffer_index, end_buffer_offset;
894 void *p, *end;
895
896 p = ctx->pointer;
897 if (!p)
898 return;
899
900 end_buffer_index = ar_search_last_active_buffer(ctx,
901 &end_buffer_offset);
902 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
903 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
904
905 if (end_buffer_index < ar_first_buffer_index(ctx)) {
906 /*
907 * The filled part of the overall buffer wraps around; handle
908 * all packets up to the buffer end here. If the last packet
909 * wraps around, its tail will be visible after the buffer end
910 * because the buffer start pages are mapped there again.
911 */
912 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
913 p = handle_ar_packets(ctx, p, buffer_end);
914 if (p < buffer_end)
915 goto error;
916 /* adjust p to point back into the actual buffer */
917 p -= AR_BUFFERS * PAGE_SIZE;
918 }
919
920 p = handle_ar_packets(ctx, p, end);
921 if (p != end) {
922 if (p > end)
923 ar_context_abort(ctx, "inconsistent descriptor");
924 goto error;
925 }
926
927 ctx->pointer = p;
928 ar_recycle_buffers(ctx, end_buffer_index);
929
930 return;
931
932 error:
933 ctx->pointer = NULL;
934 }
935
936 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
937 unsigned int descriptors_offset, u32 regs)
938 {
939 unsigned int i;
940 dma_addr_t dma_addr;
941 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
942 struct descriptor *d;
943
944 ctx->regs = regs;
945 ctx->ohci = ohci;
946 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
947
948 for (i = 0; i < AR_BUFFERS; i++) {
949 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
950 if (!ctx->pages[i])
951 goto out_of_memory;
952 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
953 0, PAGE_SIZE, DMA_FROM_DEVICE);
954 if (dma_mapping_error(ohci->card.device, dma_addr)) {
955 __free_page(ctx->pages[i]);
956 ctx->pages[i] = NULL;
957 goto out_of_memory;
958 }
959 set_page_private(ctx->pages[i], dma_addr);
960 }
961
962 for (i = 0; i < AR_BUFFERS; i++)
963 pages[i] = ctx->pages[i];
964 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
965 pages[AR_BUFFERS + i] = ctx->pages[i];
966 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
967 -1, PAGE_KERNEL);
968 if (!ctx->buffer)
969 goto out_of_memory;
970
971 ctx->descriptors = ohci->misc_buffer + descriptors_offset;
972 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
973
974 for (i = 0; i < AR_BUFFERS; i++) {
975 d = &ctx->descriptors[i];
976 d->req_count = cpu_to_le16(PAGE_SIZE);
977 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
978 DESCRIPTOR_STATUS |
979 DESCRIPTOR_BRANCH_ALWAYS);
980 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
981 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
982 ar_next_buffer_index(i) * sizeof(struct descriptor));
983 }
984
985 return 0;
986
987 out_of_memory:
988 ar_context_release(ctx);
989
990 return -ENOMEM;
991 }
992
993 static void ar_context_run(struct ar_context *ctx)
994 {
995 unsigned int i;
996
997 for (i = 0; i < AR_BUFFERS; i++)
998 ar_context_link_page(ctx, i);
999
1000 ctx->pointer = ctx->buffer;
1001
1002 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1003 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1004 flush_writes(ctx->ohci);
1005 }
1006
1007 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1008 {
1009 __le16 branch;
1010
1011 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1012
1013 /* figure out which descriptor the branch address goes in */
1014 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1015 return d;
1016 else
1017 return d + z - 1;
1018 }
1019
1020 static void context_tasklet(unsigned long data)
1021 {
1022 struct context *ctx = (struct context *) data;
1023 struct descriptor *d, *last;
1024 u32 address;
1025 int z;
1026 struct descriptor_buffer *desc;
1027
1028 desc = list_entry(ctx->buffer_list.next,
1029 struct descriptor_buffer, list);
1030 last = ctx->last;
1031 while (last->branch_address != 0) {
1032 struct descriptor_buffer *old_desc = desc;
1033 address = le32_to_cpu(last->branch_address);
1034 z = address & 0xf;
1035 address &= ~0xf;
1036
1037 /* If the branch address points to a buffer outside of the
1038 * current buffer, advance to the next buffer. */
1039 if (address < desc->buffer_bus ||
1040 address >= desc->buffer_bus + desc->used)
1041 desc = list_entry(desc->list.next,
1042 struct descriptor_buffer, list);
1043 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1044 last = find_branch_descriptor(d, z);
1045
1046 if (!ctx->callback(ctx, d, last))
1047 break;
1048
1049 if (old_desc != desc) {
1050 /* If we've advanced to the next buffer, move the
1051 * previous buffer to the free list. */
1052 unsigned long flags;
1053 old_desc->used = 0;
1054 spin_lock_irqsave(&ctx->ohci->lock, flags);
1055 list_move_tail(&old_desc->list, &ctx->buffer_list);
1056 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1057 }
1058 ctx->last = last;
1059 }
1060 }
1061
1062 /*
1063 * Allocate a new buffer and add it to the list of free buffers for this
1064 * context. Must be called with ohci->lock held.
1065 */
1066 static int context_add_buffer(struct context *ctx)
1067 {
1068 struct descriptor_buffer *desc;
1069 dma_addr_t uninitialized_var(bus_addr);
1070 int offset;
1071
1072 /*
1073 * 16MB of descriptors should be far more than enough for any DMA
1074 * program. This will catch run-away userspace or DoS attacks.
1075 */
1076 if (ctx->total_allocation >= 16*1024*1024)
1077 return -ENOMEM;
1078
1079 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1080 &bus_addr, GFP_ATOMIC);
1081 if (!desc)
1082 return -ENOMEM;
1083
1084 offset = (void *)&desc->buffer - (void *)desc;
1085 desc->buffer_size = PAGE_SIZE - offset;
1086 desc->buffer_bus = bus_addr + offset;
1087 desc->used = 0;
1088
1089 list_add_tail(&desc->list, &ctx->buffer_list);
1090 ctx->total_allocation += PAGE_SIZE;
1091
1092 return 0;
1093 }
1094
1095 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1096 u32 regs, descriptor_callback_t callback)
1097 {
1098 ctx->ohci = ohci;
1099 ctx->regs = regs;
1100 ctx->total_allocation = 0;
1101
1102 INIT_LIST_HEAD(&ctx->buffer_list);
1103 if (context_add_buffer(ctx) < 0)
1104 return -ENOMEM;
1105
1106 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1107 struct descriptor_buffer, list);
1108
1109 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1110 ctx->callback = callback;
1111
1112 /*
1113 * We put a dummy descriptor in the buffer that has a NULL
1114 * branch address and looks like it's been sent. That way we
1115 * have a descriptor to append DMA programs to.
1116 */
1117 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1118 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1119 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1120 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1121 ctx->last = ctx->buffer_tail->buffer;
1122 ctx->prev = ctx->buffer_tail->buffer;
1123
1124 return 0;
1125 }
1126
1127 static void context_release(struct context *ctx)
1128 {
1129 struct fw_card *card = &ctx->ohci->card;
1130 struct descriptor_buffer *desc, *tmp;
1131
1132 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1133 dma_free_coherent(card->device, PAGE_SIZE, desc,
1134 desc->buffer_bus -
1135 ((void *)&desc->buffer - (void *)desc));
1136 }
1137
1138 /* Must be called with ohci->lock held */
1139 static struct descriptor *context_get_descriptors(struct context *ctx,
1140 int z, dma_addr_t *d_bus)
1141 {
1142 struct descriptor *d = NULL;
1143 struct descriptor_buffer *desc = ctx->buffer_tail;
1144
1145 if (z * sizeof(*d) > desc->buffer_size)
1146 return NULL;
1147
1148 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1149 /* No room for the descriptor in this buffer, so advance to the
1150 * next one. */
1151
1152 if (desc->list.next == &ctx->buffer_list) {
1153 /* If there is no free buffer next in the list,
1154 * allocate one. */
1155 if (context_add_buffer(ctx) < 0)
1156 return NULL;
1157 }
1158 desc = list_entry(desc->list.next,
1159 struct descriptor_buffer, list);
1160 ctx->buffer_tail = desc;
1161 }
1162
1163 d = desc->buffer + desc->used / sizeof(*d);
1164 memset(d, 0, z * sizeof(*d));
1165 *d_bus = desc->buffer_bus + desc->used;
1166
1167 return d;
1168 }
1169
1170 static void context_run(struct context *ctx, u32 extra)
1171 {
1172 struct fw_ohci *ohci = ctx->ohci;
1173
1174 reg_write(ohci, COMMAND_PTR(ctx->regs),
1175 le32_to_cpu(ctx->last->branch_address));
1176 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1177 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1178 ctx->running = true;
1179 flush_writes(ohci);
1180 }
1181
1182 static void context_append(struct context *ctx,
1183 struct descriptor *d, int z, int extra)
1184 {
1185 dma_addr_t d_bus;
1186 struct descriptor_buffer *desc = ctx->buffer_tail;
1187
1188 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1189
1190 desc->used += (z + extra) * sizeof(*d);
1191
1192 wmb(); /* finish init of new descriptors before branch_address update */
1193 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1194 ctx->prev = find_branch_descriptor(d, z);
1195
1196 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1197 flush_writes(ctx->ohci);
1198 }
1199
1200 static void context_stop(struct context *ctx)
1201 {
1202 u32 reg;
1203 int i;
1204
1205 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1206 ctx->running = false;
1207 flush_writes(ctx->ohci);
1208
1209 for (i = 0; i < 10; i++) {
1210 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1211 if ((reg & CONTEXT_ACTIVE) == 0)
1212 return;
1213
1214 mdelay(1);
1215 }
1216 fw_error("Error: DMA context still active (0x%08x)\n", reg);
1217 }
1218
1219 struct driver_data {
1220 u8 inline_data[8];
1221 struct fw_packet *packet;
1222 };
1223
1224 /*
1225 * This function apppends a packet to the DMA queue for transmission.
1226 * Must always be called with the ochi->lock held to ensure proper
1227 * generation handling and locking around packet queue manipulation.
1228 */
1229 static int at_context_queue_packet(struct context *ctx,
1230 struct fw_packet *packet)
1231 {
1232 struct fw_ohci *ohci = ctx->ohci;
1233 dma_addr_t d_bus, uninitialized_var(payload_bus);
1234 struct driver_data *driver_data;
1235 struct descriptor *d, *last;
1236 __le32 *header;
1237 int z, tcode;
1238
1239 d = context_get_descriptors(ctx, 4, &d_bus);
1240 if (d == NULL) {
1241 packet->ack = RCODE_SEND_ERROR;
1242 return -1;
1243 }
1244
1245 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1246 d[0].res_count = cpu_to_le16(packet->timestamp);
1247
1248 /*
1249 * The DMA format for asyncronous link packets is different
1250 * from the IEEE1394 layout, so shift the fields around
1251 * accordingly.
1252 */
1253
1254 tcode = (packet->header[0] >> 4) & 0x0f;
1255 header = (__le32 *) &d[1];
1256 switch (tcode) {
1257 case TCODE_WRITE_QUADLET_REQUEST:
1258 case TCODE_WRITE_BLOCK_REQUEST:
1259 case TCODE_WRITE_RESPONSE:
1260 case TCODE_READ_QUADLET_REQUEST:
1261 case TCODE_READ_BLOCK_REQUEST:
1262 case TCODE_READ_QUADLET_RESPONSE:
1263 case TCODE_READ_BLOCK_RESPONSE:
1264 case TCODE_LOCK_REQUEST:
1265 case TCODE_LOCK_RESPONSE:
1266 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1267 (packet->speed << 16));
1268 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1269 (packet->header[0] & 0xffff0000));
1270 header[2] = cpu_to_le32(packet->header[2]);
1271
1272 if (TCODE_IS_BLOCK_PACKET(tcode))
1273 header[3] = cpu_to_le32(packet->header[3]);
1274 else
1275 header[3] = (__force __le32) packet->header[3];
1276
1277 d[0].req_count = cpu_to_le16(packet->header_length);
1278 break;
1279
1280 case TCODE_LINK_INTERNAL:
1281 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1282 (packet->speed << 16));
1283 header[1] = cpu_to_le32(packet->header[1]);
1284 header[2] = cpu_to_le32(packet->header[2]);
1285 d[0].req_count = cpu_to_le16(12);
1286
1287 if (is_ping_packet(&packet->header[1]))
1288 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1289 break;
1290
1291 case TCODE_STREAM_DATA:
1292 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1293 (packet->speed << 16));
1294 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1295 d[0].req_count = cpu_to_le16(8);
1296 break;
1297
1298 default:
1299 /* BUG(); */
1300 packet->ack = RCODE_SEND_ERROR;
1301 return -1;
1302 }
1303
1304 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1305 driver_data = (struct driver_data *) &d[3];
1306 driver_data->packet = packet;
1307 packet->driver_data = driver_data;
1308
1309 if (packet->payload_length > 0) {
1310 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1311 payload_bus = dma_map_single(ohci->card.device,
1312 packet->payload,
1313 packet->payload_length,
1314 DMA_TO_DEVICE);
1315 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1316 packet->ack = RCODE_SEND_ERROR;
1317 return -1;
1318 }
1319 packet->payload_bus = payload_bus;
1320 packet->payload_mapped = true;
1321 } else {
1322 memcpy(driver_data->inline_data, packet->payload,
1323 packet->payload_length);
1324 payload_bus = d_bus + 3 * sizeof(*d);
1325 }
1326
1327 d[2].req_count = cpu_to_le16(packet->payload_length);
1328 d[2].data_address = cpu_to_le32(payload_bus);
1329 last = &d[2];
1330 z = 3;
1331 } else {
1332 last = &d[0];
1333 z = 2;
1334 }
1335
1336 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1337 DESCRIPTOR_IRQ_ALWAYS |
1338 DESCRIPTOR_BRANCH_ALWAYS);
1339
1340 /* FIXME: Document how the locking works. */
1341 if (ohci->generation != packet->generation) {
1342 if (packet->payload_mapped)
1343 dma_unmap_single(ohci->card.device, payload_bus,
1344 packet->payload_length, DMA_TO_DEVICE);
1345 packet->ack = RCODE_GENERATION;
1346 return -1;
1347 }
1348
1349 context_append(ctx, d, z, 4 - z);
1350
1351 if (!ctx->running)
1352 context_run(ctx, 0);
1353
1354 return 0;
1355 }
1356
1357 static void at_context_flush(struct context *ctx)
1358 {
1359 tasklet_disable(&ctx->tasklet);
1360
1361 ctx->flushing = true;
1362 context_tasklet((unsigned long)ctx);
1363 ctx->flushing = false;
1364
1365 tasklet_enable(&ctx->tasklet);
1366 }
1367
1368 static int handle_at_packet(struct context *context,
1369 struct descriptor *d,
1370 struct descriptor *last)
1371 {
1372 struct driver_data *driver_data;
1373 struct fw_packet *packet;
1374 struct fw_ohci *ohci = context->ohci;
1375 int evt;
1376
1377 if (last->transfer_status == 0 && !context->flushing)
1378 /* This descriptor isn't done yet, stop iteration. */
1379 return 0;
1380
1381 driver_data = (struct driver_data *) &d[3];
1382 packet = driver_data->packet;
1383 if (packet == NULL)
1384 /* This packet was cancelled, just continue. */
1385 return 1;
1386
1387 if (packet->payload_mapped)
1388 dma_unmap_single(ohci->card.device, packet->payload_bus,
1389 packet->payload_length, DMA_TO_DEVICE);
1390
1391 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1392 packet->timestamp = le16_to_cpu(last->res_count);
1393
1394 log_ar_at_event('T', packet->speed, packet->header, evt);
1395
1396 switch (evt) {
1397 case OHCI1394_evt_timeout:
1398 /* Async response transmit timed out. */
1399 packet->ack = RCODE_CANCELLED;
1400 break;
1401
1402 case OHCI1394_evt_flushed:
1403 /*
1404 * The packet was flushed should give same error as
1405 * when we try to use a stale generation count.
1406 */
1407 packet->ack = RCODE_GENERATION;
1408 break;
1409
1410 case OHCI1394_evt_missing_ack:
1411 if (context->flushing)
1412 packet->ack = RCODE_GENERATION;
1413 else {
1414 /*
1415 * Using a valid (current) generation count, but the
1416 * node is not on the bus or not sending acks.
1417 */
1418 packet->ack = RCODE_NO_ACK;
1419 }
1420 break;
1421
1422 case ACK_COMPLETE + 0x10:
1423 case ACK_PENDING + 0x10:
1424 case ACK_BUSY_X + 0x10:
1425 case ACK_BUSY_A + 0x10:
1426 case ACK_BUSY_B + 0x10:
1427 case ACK_DATA_ERROR + 0x10:
1428 case ACK_TYPE_ERROR + 0x10:
1429 packet->ack = evt - 0x10;
1430 break;
1431
1432 case OHCI1394_evt_no_status:
1433 if (context->flushing) {
1434 packet->ack = RCODE_GENERATION;
1435 break;
1436 }
1437 /* fall through */
1438
1439 default:
1440 packet->ack = RCODE_SEND_ERROR;
1441 break;
1442 }
1443
1444 packet->callback(packet, &ohci->card, packet->ack);
1445
1446 return 1;
1447 }
1448
1449 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1450 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1451 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1452 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1453 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1454
1455 static void handle_local_rom(struct fw_ohci *ohci,
1456 struct fw_packet *packet, u32 csr)
1457 {
1458 struct fw_packet response;
1459 int tcode, length, i;
1460
1461 tcode = HEADER_GET_TCODE(packet->header[0]);
1462 if (TCODE_IS_BLOCK_PACKET(tcode))
1463 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1464 else
1465 length = 4;
1466
1467 i = csr - CSR_CONFIG_ROM;
1468 if (i + length > CONFIG_ROM_SIZE) {
1469 fw_fill_response(&response, packet->header,
1470 RCODE_ADDRESS_ERROR, NULL, 0);
1471 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1472 fw_fill_response(&response, packet->header,
1473 RCODE_TYPE_ERROR, NULL, 0);
1474 } else {
1475 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1476 (void *) ohci->config_rom + i, length);
1477 }
1478
1479 fw_core_handle_response(&ohci->card, &response);
1480 }
1481
1482 static void handle_local_lock(struct fw_ohci *ohci,
1483 struct fw_packet *packet, u32 csr)
1484 {
1485 struct fw_packet response;
1486 int tcode, length, ext_tcode, sel, try;
1487 __be32 *payload, lock_old;
1488 u32 lock_arg, lock_data;
1489
1490 tcode = HEADER_GET_TCODE(packet->header[0]);
1491 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1492 payload = packet->payload;
1493 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1494
1495 if (tcode == TCODE_LOCK_REQUEST &&
1496 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1497 lock_arg = be32_to_cpu(payload[0]);
1498 lock_data = be32_to_cpu(payload[1]);
1499 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1500 lock_arg = 0;
1501 lock_data = 0;
1502 } else {
1503 fw_fill_response(&response, packet->header,
1504 RCODE_TYPE_ERROR, NULL, 0);
1505 goto out;
1506 }
1507
1508 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1509 reg_write(ohci, OHCI1394_CSRData, lock_data);
1510 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1511 reg_write(ohci, OHCI1394_CSRControl, sel);
1512
1513 for (try = 0; try < 20; try++)
1514 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1515 lock_old = cpu_to_be32(reg_read(ohci,
1516 OHCI1394_CSRData));
1517 fw_fill_response(&response, packet->header,
1518 RCODE_COMPLETE,
1519 &lock_old, sizeof(lock_old));
1520 goto out;
1521 }
1522
1523 fw_error("swap not done (CSR lock timeout)\n");
1524 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1525
1526 out:
1527 fw_core_handle_response(&ohci->card, &response);
1528 }
1529
1530 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1531 {
1532 u64 offset, csr;
1533
1534 if (ctx == &ctx->ohci->at_request_ctx) {
1535 packet->ack = ACK_PENDING;
1536 packet->callback(packet, &ctx->ohci->card, packet->ack);
1537 }
1538
1539 offset =
1540 ((unsigned long long)
1541 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1542 packet->header[2];
1543 csr = offset - CSR_REGISTER_BASE;
1544
1545 /* Handle config rom reads. */
1546 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1547 handle_local_rom(ctx->ohci, packet, csr);
1548 else switch (csr) {
1549 case CSR_BUS_MANAGER_ID:
1550 case CSR_BANDWIDTH_AVAILABLE:
1551 case CSR_CHANNELS_AVAILABLE_HI:
1552 case CSR_CHANNELS_AVAILABLE_LO:
1553 handle_local_lock(ctx->ohci, packet, csr);
1554 break;
1555 default:
1556 if (ctx == &ctx->ohci->at_request_ctx)
1557 fw_core_handle_request(&ctx->ohci->card, packet);
1558 else
1559 fw_core_handle_response(&ctx->ohci->card, packet);
1560 break;
1561 }
1562
1563 if (ctx == &ctx->ohci->at_response_ctx) {
1564 packet->ack = ACK_COMPLETE;
1565 packet->callback(packet, &ctx->ohci->card, packet->ack);
1566 }
1567 }
1568
1569 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1570 {
1571 unsigned long flags;
1572 int ret;
1573
1574 spin_lock_irqsave(&ctx->ohci->lock, flags);
1575
1576 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1577 ctx->ohci->generation == packet->generation) {
1578 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1579 handle_local_request(ctx, packet);
1580 return;
1581 }
1582
1583 ret = at_context_queue_packet(ctx, packet);
1584 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1585
1586 if (ret < 0)
1587 packet->callback(packet, &ctx->ohci->card, packet->ack);
1588
1589 }
1590
1591 static void detect_dead_context(struct fw_ohci *ohci,
1592 const char *name, unsigned int regs)
1593 {
1594 u32 ctl;
1595
1596 ctl = reg_read(ohci, CONTROL_SET(regs));
1597 if (ctl & CONTEXT_DEAD) {
1598 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
1599 fw_error("DMA context %s has stopped, error code: %s\n",
1600 name, evts[ctl & 0x1f]);
1601 #else
1602 fw_error("DMA context %s has stopped, error code: %#x\n",
1603 name, ctl & 0x1f);
1604 #endif
1605 }
1606 }
1607
1608 static void handle_dead_contexts(struct fw_ohci *ohci)
1609 {
1610 unsigned int i;
1611 char name[8];
1612
1613 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1614 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1615 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1616 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1617 for (i = 0; i < 32; ++i) {
1618 if (!(ohci->it_context_support & (1 << i)))
1619 continue;
1620 sprintf(name, "IT%u", i);
1621 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1622 }
1623 for (i = 0; i < 32; ++i) {
1624 if (!(ohci->ir_context_support & (1 << i)))
1625 continue;
1626 sprintf(name, "IR%u", i);
1627 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1628 }
1629 /* TODO: maybe try to flush and restart the dead contexts */
1630 }
1631
1632 static u32 cycle_timer_ticks(u32 cycle_timer)
1633 {
1634 u32 ticks;
1635
1636 ticks = cycle_timer & 0xfff;
1637 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1638 ticks += (3072 * 8000) * (cycle_timer >> 25);
1639
1640 return ticks;
1641 }
1642
1643 /*
1644 * Some controllers exhibit one or more of the following bugs when updating the
1645 * iso cycle timer register:
1646 * - When the lowest six bits are wrapping around to zero, a read that happens
1647 * at the same time will return garbage in the lowest ten bits.
1648 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1649 * not incremented for about 60 ns.
1650 * - Occasionally, the entire register reads zero.
1651 *
1652 * To catch these, we read the register three times and ensure that the
1653 * difference between each two consecutive reads is approximately the same, i.e.
1654 * less than twice the other. Furthermore, any negative difference indicates an
1655 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1656 * execute, so we have enough precision to compute the ratio of the differences.)
1657 */
1658 static u32 get_cycle_time(struct fw_ohci *ohci)
1659 {
1660 u32 c0, c1, c2;
1661 u32 t0, t1, t2;
1662 s32 diff01, diff12;
1663 int i;
1664
1665 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1666
1667 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1668 i = 0;
1669 c1 = c2;
1670 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1671 do {
1672 c0 = c1;
1673 c1 = c2;
1674 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1675 t0 = cycle_timer_ticks(c0);
1676 t1 = cycle_timer_ticks(c1);
1677 t2 = cycle_timer_ticks(c2);
1678 diff01 = t1 - t0;
1679 diff12 = t2 - t1;
1680 } while ((diff01 <= 0 || diff12 <= 0 ||
1681 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1682 && i++ < 20);
1683 }
1684
1685 return c2;
1686 }
1687
1688 /*
1689 * This function has to be called at least every 64 seconds. The bus_time
1690 * field stores not only the upper 25 bits of the BUS_TIME register but also
1691 * the most significant bit of the cycle timer in bit 6 so that we can detect
1692 * changes in this bit.
1693 */
1694 static u32 update_bus_time(struct fw_ohci *ohci)
1695 {
1696 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1697
1698 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1699 ohci->bus_time += 0x40;
1700
1701 return ohci->bus_time | cycle_time_seconds;
1702 }
1703
1704 static void bus_reset_tasklet(unsigned long data)
1705 {
1706 struct fw_ohci *ohci = (struct fw_ohci *)data;
1707 int self_id_count, i, j, reg;
1708 int generation, new_generation;
1709 unsigned long flags;
1710 void *free_rom = NULL;
1711 dma_addr_t free_rom_bus = 0;
1712 bool is_new_root;
1713
1714 reg = reg_read(ohci, OHCI1394_NodeID);
1715 if (!(reg & OHCI1394_NodeID_idValid)) {
1716 fw_notify("node ID not valid, new bus reset in progress\n");
1717 return;
1718 }
1719 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1720 fw_notify("malconfigured bus\n");
1721 return;
1722 }
1723 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1724 OHCI1394_NodeID_nodeNumber);
1725
1726 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1727 if (!(ohci->is_root && is_new_root))
1728 reg_write(ohci, OHCI1394_LinkControlSet,
1729 OHCI1394_LinkControl_cycleMaster);
1730 ohci->is_root = is_new_root;
1731
1732 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1733 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1734 fw_notify("inconsistent self IDs\n");
1735 return;
1736 }
1737 /*
1738 * The count in the SelfIDCount register is the number of
1739 * bytes in the self ID receive buffer. Since we also receive
1740 * the inverted quadlets and a header quadlet, we shift one
1741 * bit extra to get the actual number of self IDs.
1742 */
1743 self_id_count = (reg >> 3) & 0xff;
1744 if (self_id_count == 0 || self_id_count > 252) {
1745 fw_notify("inconsistent self IDs\n");
1746 return;
1747 }
1748 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1749 rmb();
1750
1751 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1752 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1753 fw_notify("inconsistent self IDs\n");
1754 return;
1755 }
1756 ohci->self_id_buffer[j] =
1757 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1758 }
1759 rmb();
1760
1761 /*
1762 * Check the consistency of the self IDs we just read. The
1763 * problem we face is that a new bus reset can start while we
1764 * read out the self IDs from the DMA buffer. If this happens,
1765 * the DMA buffer will be overwritten with new self IDs and we
1766 * will read out inconsistent data. The OHCI specification
1767 * (section 11.2) recommends a technique similar to
1768 * linux/seqlock.h, where we remember the generation of the
1769 * self IDs in the buffer before reading them out and compare
1770 * it to the current generation after reading them out. If
1771 * the two generations match we know we have a consistent set
1772 * of self IDs.
1773 */
1774
1775 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1776 if (new_generation != generation) {
1777 fw_notify("recursive bus reset detected, "
1778 "discarding self ids\n");
1779 return;
1780 }
1781
1782 /* FIXME: Document how the locking works. */
1783 spin_lock_irqsave(&ohci->lock, flags);
1784
1785 ohci->generation = -1; /* prevent AT packet queueing */
1786 context_stop(&ohci->at_request_ctx);
1787 context_stop(&ohci->at_response_ctx);
1788
1789 spin_unlock_irqrestore(&ohci->lock, flags);
1790
1791 /*
1792 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1793 * packets in the AT queues and software needs to drain them.
1794 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1795 */
1796 at_context_flush(&ohci->at_request_ctx);
1797 at_context_flush(&ohci->at_response_ctx);
1798
1799 spin_lock_irqsave(&ohci->lock, flags);
1800
1801 ohci->generation = generation;
1802 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1803
1804 if (ohci->quirks & QUIRK_RESET_PACKET)
1805 ohci->request_generation = generation;
1806
1807 /*
1808 * This next bit is unrelated to the AT context stuff but we
1809 * have to do it under the spinlock also. If a new config rom
1810 * was set up before this reset, the old one is now no longer
1811 * in use and we can free it. Update the config rom pointers
1812 * to point to the current config rom and clear the
1813 * next_config_rom pointer so a new update can take place.
1814 */
1815
1816 if (ohci->next_config_rom != NULL) {
1817 if (ohci->next_config_rom != ohci->config_rom) {
1818 free_rom = ohci->config_rom;
1819 free_rom_bus = ohci->config_rom_bus;
1820 }
1821 ohci->config_rom = ohci->next_config_rom;
1822 ohci->config_rom_bus = ohci->next_config_rom_bus;
1823 ohci->next_config_rom = NULL;
1824
1825 /*
1826 * Restore config_rom image and manually update
1827 * config_rom registers. Writing the header quadlet
1828 * will indicate that the config rom is ready, so we
1829 * do that last.
1830 */
1831 reg_write(ohci, OHCI1394_BusOptions,
1832 be32_to_cpu(ohci->config_rom[2]));
1833 ohci->config_rom[0] = ohci->next_header;
1834 reg_write(ohci, OHCI1394_ConfigROMhdr,
1835 be32_to_cpu(ohci->next_header));
1836 }
1837
1838 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1839 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1840 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1841 #endif
1842
1843 spin_unlock_irqrestore(&ohci->lock, flags);
1844
1845 if (free_rom)
1846 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1847 free_rom, free_rom_bus);
1848
1849 log_selfids(ohci->node_id, generation,
1850 self_id_count, ohci->self_id_buffer);
1851
1852 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1853 self_id_count, ohci->self_id_buffer,
1854 ohci->csr_state_setclear_abdicate);
1855 ohci->csr_state_setclear_abdicate = false;
1856 }
1857
1858 static irqreturn_t irq_handler(int irq, void *data)
1859 {
1860 struct fw_ohci *ohci = data;
1861 u32 event, iso_event;
1862 int i;
1863
1864 event = reg_read(ohci, OHCI1394_IntEventClear);
1865
1866 if (!event || !~event)
1867 return IRQ_NONE;
1868
1869 /*
1870 * busReset and postedWriteErr must not be cleared yet
1871 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
1872 */
1873 reg_write(ohci, OHCI1394_IntEventClear,
1874 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
1875 log_irqs(event);
1876
1877 if (event & OHCI1394_selfIDComplete)
1878 tasklet_schedule(&ohci->bus_reset_tasklet);
1879
1880 if (event & OHCI1394_RQPkt)
1881 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1882
1883 if (event & OHCI1394_RSPkt)
1884 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1885
1886 if (event & OHCI1394_reqTxComplete)
1887 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1888
1889 if (event & OHCI1394_respTxComplete)
1890 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1891
1892 if (event & OHCI1394_isochRx) {
1893 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1894 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1895
1896 while (iso_event) {
1897 i = ffs(iso_event) - 1;
1898 tasklet_schedule(
1899 &ohci->ir_context_list[i].context.tasklet);
1900 iso_event &= ~(1 << i);
1901 }
1902 }
1903
1904 if (event & OHCI1394_isochTx) {
1905 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1906 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1907
1908 while (iso_event) {
1909 i = ffs(iso_event) - 1;
1910 tasklet_schedule(
1911 &ohci->it_context_list[i].context.tasklet);
1912 iso_event &= ~(1 << i);
1913 }
1914 }
1915
1916 if (unlikely(event & OHCI1394_regAccessFail))
1917 fw_error("Register access failure - "
1918 "please notify linux1394-devel@lists.sf.net\n");
1919
1920 if (unlikely(event & OHCI1394_postedWriteErr)) {
1921 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
1922 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
1923 reg_write(ohci, OHCI1394_IntEventClear,
1924 OHCI1394_postedWriteErr);
1925 fw_error("PCI posted write error\n");
1926 }
1927
1928 if (unlikely(event & OHCI1394_cycleTooLong)) {
1929 if (printk_ratelimit())
1930 fw_notify("isochronous cycle too long\n");
1931 reg_write(ohci, OHCI1394_LinkControlSet,
1932 OHCI1394_LinkControl_cycleMaster);
1933 }
1934
1935 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1936 /*
1937 * We need to clear this event bit in order to make
1938 * cycleMatch isochronous I/O work. In theory we should
1939 * stop active cycleMatch iso contexts now and restart
1940 * them at least two cycles later. (FIXME?)
1941 */
1942 if (printk_ratelimit())
1943 fw_notify("isochronous cycle inconsistent\n");
1944 }
1945
1946 if (unlikely(event & OHCI1394_unrecoverableError))
1947 handle_dead_contexts(ohci);
1948
1949 if (event & OHCI1394_cycle64Seconds) {
1950 spin_lock(&ohci->lock);
1951 update_bus_time(ohci);
1952 spin_unlock(&ohci->lock);
1953 } else
1954 flush_writes(ohci);
1955
1956 return IRQ_HANDLED;
1957 }
1958
1959 static int software_reset(struct fw_ohci *ohci)
1960 {
1961 int i;
1962
1963 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1964
1965 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1966 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1967 OHCI1394_HCControl_softReset) == 0)
1968 return 0;
1969 msleep(1);
1970 }
1971
1972 return -EBUSY;
1973 }
1974
1975 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1976 {
1977 size_t size = length * 4;
1978
1979 memcpy(dest, src, size);
1980 if (size < CONFIG_ROM_SIZE)
1981 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1982 }
1983
1984 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1985 {
1986 bool enable_1394a;
1987 int ret, clear, set, offset;
1988
1989 /* Check if the driver should configure link and PHY. */
1990 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1991 OHCI1394_HCControl_programPhyEnable))
1992 return 0;
1993
1994 /* Paranoia: check whether the PHY supports 1394a, too. */
1995 enable_1394a = false;
1996 ret = read_phy_reg(ohci, 2);
1997 if (ret < 0)
1998 return ret;
1999 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2000 ret = read_paged_phy_reg(ohci, 1, 8);
2001 if (ret < 0)
2002 return ret;
2003 if (ret >= 1)
2004 enable_1394a = true;
2005 }
2006
2007 if (ohci->quirks & QUIRK_NO_1394A)
2008 enable_1394a = false;
2009
2010 /* Configure PHY and link consistently. */
2011 if (enable_1394a) {
2012 clear = 0;
2013 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2014 } else {
2015 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2016 set = 0;
2017 }
2018 ret = update_phy_reg(ohci, 5, clear, set);
2019 if (ret < 0)
2020 return ret;
2021
2022 if (enable_1394a)
2023 offset = OHCI1394_HCControlSet;
2024 else
2025 offset = OHCI1394_HCControlClear;
2026 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2027
2028 /* Clean up: configuration has been taken care of. */
2029 reg_write(ohci, OHCI1394_HCControlClear,
2030 OHCI1394_HCControl_programPhyEnable);
2031
2032 return 0;
2033 }
2034
2035 static int ohci_enable(struct fw_card *card,
2036 const __be32 *config_rom, size_t length)
2037 {
2038 struct fw_ohci *ohci = fw_ohci(card);
2039 struct pci_dev *dev = to_pci_dev(card->device);
2040 u32 lps, seconds, version, irqs;
2041 int i, ret;
2042
2043 if (software_reset(ohci)) {
2044 fw_error("Failed to reset ohci card.\n");
2045 return -EBUSY;
2046 }
2047
2048 /*
2049 * Now enable LPS, which we need in order to start accessing
2050 * most of the registers. In fact, on some cards (ALI M5251),
2051 * accessing registers in the SClk domain without LPS enabled
2052 * will lock up the machine. Wait 50msec to make sure we have
2053 * full link enabled. However, with some cards (well, at least
2054 * a JMicron PCIe card), we have to try again sometimes.
2055 */
2056 reg_write(ohci, OHCI1394_HCControlSet,
2057 OHCI1394_HCControl_LPS |
2058 OHCI1394_HCControl_postedWriteEnable);
2059 flush_writes(ohci);
2060
2061 for (lps = 0, i = 0; !lps && i < 3; i++) {
2062 msleep(50);
2063 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2064 OHCI1394_HCControl_LPS;
2065 }
2066
2067 if (!lps) {
2068 fw_error("Failed to set Link Power Status\n");
2069 return -EIO;
2070 }
2071
2072 reg_write(ohci, OHCI1394_HCControlClear,
2073 OHCI1394_HCControl_noByteSwapData);
2074
2075 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2076 reg_write(ohci, OHCI1394_LinkControlSet,
2077 OHCI1394_LinkControl_cycleTimerEnable |
2078 OHCI1394_LinkControl_cycleMaster);
2079
2080 reg_write(ohci, OHCI1394_ATRetries,
2081 OHCI1394_MAX_AT_REQ_RETRIES |
2082 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2083 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2084 (200 << 16));
2085
2086 seconds = lower_32_bits(get_seconds());
2087 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2088 ohci->bus_time = seconds & ~0x3f;
2089
2090 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2091 if (version >= OHCI_VERSION_1_1) {
2092 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2093 0xfffffffe);
2094 card->broadcast_channel_auto_allocated = true;
2095 }
2096
2097 /* Get implemented bits of the priority arbitration request counter. */
2098 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2099 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2100 reg_write(ohci, OHCI1394_FairnessControl, 0);
2101 card->priority_budget_implemented = ohci->pri_req_max != 0;
2102
2103 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2104 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2105 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2106
2107 ret = configure_1394a_enhancements(ohci);
2108 if (ret < 0)
2109 return ret;
2110
2111 /* Activate link_on bit and contender bit in our self ID packets.*/
2112 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2113 if (ret < 0)
2114 return ret;
2115
2116 /*
2117 * When the link is not yet enabled, the atomic config rom
2118 * update mechanism described below in ohci_set_config_rom()
2119 * is not active. We have to update ConfigRomHeader and
2120 * BusOptions manually, and the write to ConfigROMmap takes
2121 * effect immediately. We tie this to the enabling of the
2122 * link, so we have a valid config rom before enabling - the
2123 * OHCI requires that ConfigROMhdr and BusOptions have valid
2124 * values before enabling.
2125 *
2126 * However, when the ConfigROMmap is written, some controllers
2127 * always read back quadlets 0 and 2 from the config rom to
2128 * the ConfigRomHeader and BusOptions registers on bus reset.
2129 * They shouldn't do that in this initial case where the link
2130 * isn't enabled. This means we have to use the same
2131 * workaround here, setting the bus header to 0 and then write
2132 * the right values in the bus reset tasklet.
2133 */
2134
2135 if (config_rom) {
2136 ohci->next_config_rom =
2137 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2138 &ohci->next_config_rom_bus,
2139 GFP_KERNEL);
2140 if (ohci->next_config_rom == NULL)
2141 return -ENOMEM;
2142
2143 copy_config_rom(ohci->next_config_rom, config_rom, length);
2144 } else {
2145 /*
2146 * In the suspend case, config_rom is NULL, which
2147 * means that we just reuse the old config rom.
2148 */
2149 ohci->next_config_rom = ohci->config_rom;
2150 ohci->next_config_rom_bus = ohci->config_rom_bus;
2151 }
2152
2153 ohci->next_header = ohci->next_config_rom[0];
2154 ohci->next_config_rom[0] = 0;
2155 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2156 reg_write(ohci, OHCI1394_BusOptions,
2157 be32_to_cpu(ohci->next_config_rom[2]));
2158 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2159
2160 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2161
2162 if (!(ohci->quirks & QUIRK_NO_MSI))
2163 pci_enable_msi(dev);
2164 if (request_irq(dev->irq, irq_handler,
2165 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2166 ohci_driver_name, ohci)) {
2167 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
2168 pci_disable_msi(dev);
2169 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2170 ohci->config_rom, ohci->config_rom_bus);
2171 return -EIO;
2172 }
2173
2174 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2175 OHCI1394_RQPkt | OHCI1394_RSPkt |
2176 OHCI1394_isochTx | OHCI1394_isochRx |
2177 OHCI1394_postedWriteErr |
2178 OHCI1394_selfIDComplete |
2179 OHCI1394_regAccessFail |
2180 OHCI1394_cycle64Seconds |
2181 OHCI1394_cycleInconsistent |
2182 OHCI1394_unrecoverableError |
2183 OHCI1394_cycleTooLong |
2184 OHCI1394_masterIntEnable;
2185 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2186 irqs |= OHCI1394_busReset;
2187 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2188
2189 reg_write(ohci, OHCI1394_HCControlSet,
2190 OHCI1394_HCControl_linkEnable |
2191 OHCI1394_HCControl_BIBimageValid);
2192
2193 reg_write(ohci, OHCI1394_LinkControlSet,
2194 OHCI1394_LinkControl_rcvSelfID |
2195 OHCI1394_LinkControl_rcvPhyPkt);
2196
2197 ar_context_run(&ohci->ar_request_ctx);
2198 ar_context_run(&ohci->ar_response_ctx); /* also flushes writes */
2199
2200 /* We are ready to go, reset bus to finish initialization. */
2201 fw_schedule_bus_reset(&ohci->card, false, true);
2202
2203 return 0;
2204 }
2205
2206 static int ohci_set_config_rom(struct fw_card *card,
2207 const __be32 *config_rom, size_t length)
2208 {
2209 struct fw_ohci *ohci;
2210 unsigned long flags;
2211 __be32 *next_config_rom;
2212 dma_addr_t uninitialized_var(next_config_rom_bus);
2213
2214 ohci = fw_ohci(card);
2215
2216 /*
2217 * When the OHCI controller is enabled, the config rom update
2218 * mechanism is a bit tricky, but easy enough to use. See
2219 * section 5.5.6 in the OHCI specification.
2220 *
2221 * The OHCI controller caches the new config rom address in a
2222 * shadow register (ConfigROMmapNext) and needs a bus reset
2223 * for the changes to take place. When the bus reset is
2224 * detected, the controller loads the new values for the
2225 * ConfigRomHeader and BusOptions registers from the specified
2226 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2227 * shadow register. All automatically and atomically.
2228 *
2229 * Now, there's a twist to this story. The automatic load of
2230 * ConfigRomHeader and BusOptions doesn't honor the
2231 * noByteSwapData bit, so with a be32 config rom, the
2232 * controller will load be32 values in to these registers
2233 * during the atomic update, even on litte endian
2234 * architectures. The workaround we use is to put a 0 in the
2235 * header quadlet; 0 is endian agnostic and means that the
2236 * config rom isn't ready yet. In the bus reset tasklet we
2237 * then set up the real values for the two registers.
2238 *
2239 * We use ohci->lock to avoid racing with the code that sets
2240 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
2241 */
2242
2243 next_config_rom =
2244 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2245 &next_config_rom_bus, GFP_KERNEL);
2246 if (next_config_rom == NULL)
2247 return -ENOMEM;
2248
2249 spin_lock_irqsave(&ohci->lock, flags);
2250
2251 /*
2252 * If there is not an already pending config_rom update,
2253 * push our new allocation into the ohci->next_config_rom
2254 * and then mark the local variable as null so that we
2255 * won't deallocate the new buffer.
2256 *
2257 * OTOH, if there is a pending config_rom update, just
2258 * use that buffer with the new config_rom data, and
2259 * let this routine free the unused DMA allocation.
2260 */
2261
2262 if (ohci->next_config_rom == NULL) {
2263 ohci->next_config_rom = next_config_rom;
2264 ohci->next_config_rom_bus = next_config_rom_bus;
2265 next_config_rom = NULL;
2266 }
2267
2268 copy_config_rom(ohci->next_config_rom, config_rom, length);
2269
2270 ohci->next_header = config_rom[0];
2271 ohci->next_config_rom[0] = 0;
2272
2273 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2274
2275 spin_unlock_irqrestore(&ohci->lock, flags);
2276
2277 /* If we didn't use the DMA allocation, delete it. */
2278 if (next_config_rom != NULL)
2279 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2280 next_config_rom, next_config_rom_bus);
2281
2282 /*
2283 * Now initiate a bus reset to have the changes take
2284 * effect. We clean up the old config rom memory and DMA
2285 * mappings in the bus reset tasklet, since the OHCI
2286 * controller could need to access it before the bus reset
2287 * takes effect.
2288 */
2289
2290 fw_schedule_bus_reset(&ohci->card, true, true);
2291
2292 return 0;
2293 }
2294
2295 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2296 {
2297 struct fw_ohci *ohci = fw_ohci(card);
2298
2299 at_context_transmit(&ohci->at_request_ctx, packet);
2300 }
2301
2302 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2303 {
2304 struct fw_ohci *ohci = fw_ohci(card);
2305
2306 at_context_transmit(&ohci->at_response_ctx, packet);
2307 }
2308
2309 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2310 {
2311 struct fw_ohci *ohci = fw_ohci(card);
2312 struct context *ctx = &ohci->at_request_ctx;
2313 struct driver_data *driver_data = packet->driver_data;
2314 int ret = -ENOENT;
2315
2316 tasklet_disable(&ctx->tasklet);
2317
2318 if (packet->ack != 0)
2319 goto out;
2320
2321 if (packet->payload_mapped)
2322 dma_unmap_single(ohci->card.device, packet->payload_bus,
2323 packet->payload_length, DMA_TO_DEVICE);
2324
2325 log_ar_at_event('T', packet->speed, packet->header, 0x20);
2326 driver_data->packet = NULL;
2327 packet->ack = RCODE_CANCELLED;
2328 packet->callback(packet, &ohci->card, packet->ack);
2329 ret = 0;
2330 out:
2331 tasklet_enable(&ctx->tasklet);
2332
2333 return ret;
2334 }
2335
2336 static int ohci_enable_phys_dma(struct fw_card *card,
2337 int node_id, int generation)
2338 {
2339 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2340 return 0;
2341 #else
2342 struct fw_ohci *ohci = fw_ohci(card);
2343 unsigned long flags;
2344 int n, ret = 0;
2345
2346 /*
2347 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2348 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2349 */
2350
2351 spin_lock_irqsave(&ohci->lock, flags);
2352
2353 if (ohci->generation != generation) {
2354 ret = -ESTALE;
2355 goto out;
2356 }
2357
2358 /*
2359 * Note, if the node ID contains a non-local bus ID, physical DMA is
2360 * enabled for _all_ nodes on remote buses.
2361 */
2362
2363 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2364 if (n < 32)
2365 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2366 else
2367 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2368
2369 flush_writes(ohci);
2370 out:
2371 spin_unlock_irqrestore(&ohci->lock, flags);
2372
2373 return ret;
2374 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2375 }
2376
2377 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2378 {
2379 struct fw_ohci *ohci = fw_ohci(card);
2380 unsigned long flags;
2381 u32 value;
2382
2383 switch (csr_offset) {
2384 case CSR_STATE_CLEAR:
2385 case CSR_STATE_SET:
2386 if (ohci->is_root &&
2387 (reg_read(ohci, OHCI1394_LinkControlSet) &
2388 OHCI1394_LinkControl_cycleMaster))
2389 value = CSR_STATE_BIT_CMSTR;
2390 else
2391 value = 0;
2392 if (ohci->csr_state_setclear_abdicate)
2393 value |= CSR_STATE_BIT_ABDICATE;
2394
2395 return value;
2396
2397 case CSR_NODE_IDS:
2398 return reg_read(ohci, OHCI1394_NodeID) << 16;
2399
2400 case CSR_CYCLE_TIME:
2401 return get_cycle_time(ohci);
2402
2403 case CSR_BUS_TIME:
2404 /*
2405 * We might be called just after the cycle timer has wrapped
2406 * around but just before the cycle64Seconds handler, so we
2407 * better check here, too, if the bus time needs to be updated.
2408 */
2409 spin_lock_irqsave(&ohci->lock, flags);
2410 value = update_bus_time(ohci);
2411 spin_unlock_irqrestore(&ohci->lock, flags);
2412 return value;
2413
2414 case CSR_BUSY_TIMEOUT:
2415 value = reg_read(ohci, OHCI1394_ATRetries);
2416 return (value >> 4) & 0x0ffff00f;
2417
2418 case CSR_PRIORITY_BUDGET:
2419 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2420 (ohci->pri_req_max << 8);
2421
2422 default:
2423 WARN_ON(1);
2424 return 0;
2425 }
2426 }
2427
2428 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2429 {
2430 struct fw_ohci *ohci = fw_ohci(card);
2431 unsigned long flags;
2432
2433 switch (csr_offset) {
2434 case CSR_STATE_CLEAR:
2435 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2436 reg_write(ohci, OHCI1394_LinkControlClear,
2437 OHCI1394_LinkControl_cycleMaster);
2438 flush_writes(ohci);
2439 }
2440 if (value & CSR_STATE_BIT_ABDICATE)
2441 ohci->csr_state_setclear_abdicate = false;
2442 break;
2443
2444 case CSR_STATE_SET:
2445 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2446 reg_write(ohci, OHCI1394_LinkControlSet,
2447 OHCI1394_LinkControl_cycleMaster);
2448 flush_writes(ohci);
2449 }
2450 if (value & CSR_STATE_BIT_ABDICATE)
2451 ohci->csr_state_setclear_abdicate = true;
2452 break;
2453
2454 case CSR_NODE_IDS:
2455 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2456 flush_writes(ohci);
2457 break;
2458
2459 case CSR_CYCLE_TIME:
2460 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2461 reg_write(ohci, OHCI1394_IntEventSet,
2462 OHCI1394_cycleInconsistent);
2463 flush_writes(ohci);
2464 break;
2465
2466 case CSR_BUS_TIME:
2467 spin_lock_irqsave(&ohci->lock, flags);
2468 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2469 spin_unlock_irqrestore(&ohci->lock, flags);
2470 break;
2471
2472 case CSR_BUSY_TIMEOUT:
2473 value = (value & 0xf) | ((value & 0xf) << 4) |
2474 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2475 reg_write(ohci, OHCI1394_ATRetries, value);
2476 flush_writes(ohci);
2477 break;
2478
2479 case CSR_PRIORITY_BUDGET:
2480 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2481 flush_writes(ohci);
2482 break;
2483
2484 default:
2485 WARN_ON(1);
2486 break;
2487 }
2488 }
2489
2490 static void copy_iso_headers(struct iso_context *ctx, void *p)
2491 {
2492 int i = ctx->header_length;
2493
2494 if (i + ctx->base.header_size > PAGE_SIZE)
2495 return;
2496
2497 /*
2498 * The iso header is byteswapped to little endian by
2499 * the controller, but the remaining header quadlets
2500 * are big endian. We want to present all the headers
2501 * as big endian, so we have to swap the first quadlet.
2502 */
2503 if (ctx->base.header_size > 0)
2504 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2505 if (ctx->base.header_size > 4)
2506 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2507 if (ctx->base.header_size > 8)
2508 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2509 ctx->header_length += ctx->base.header_size;
2510 }
2511
2512 static int handle_ir_packet_per_buffer(struct context *context,
2513 struct descriptor *d,
2514 struct descriptor *last)
2515 {
2516 struct iso_context *ctx =
2517 container_of(context, struct iso_context, context);
2518 struct descriptor *pd;
2519 __le32 *ir_header;
2520 void *p;
2521
2522 for (pd = d; pd <= last; pd++)
2523 if (pd->transfer_status)
2524 break;
2525 if (pd > last)
2526 /* Descriptor(s) not done yet, stop iteration */
2527 return 0;
2528
2529 p = last + 1;
2530 copy_iso_headers(ctx, p);
2531
2532 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2533 ir_header = (__le32 *) p;
2534 ctx->base.callback.sc(&ctx->base,
2535 le32_to_cpu(ir_header[0]) & 0xffff,
2536 ctx->header_length, ctx->header,
2537 ctx->base.callback_data);
2538 ctx->header_length = 0;
2539 }
2540
2541 return 1;
2542 }
2543
2544 /* d == last because each descriptor block is only a single descriptor. */
2545 static int handle_ir_buffer_fill(struct context *context,
2546 struct descriptor *d,
2547 struct descriptor *last)
2548 {
2549 struct iso_context *ctx =
2550 container_of(context, struct iso_context, context);
2551
2552 if (!last->transfer_status)
2553 /* Descriptor(s) not done yet, stop iteration */
2554 return 0;
2555
2556 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2557 ctx->base.callback.mc(&ctx->base,
2558 le32_to_cpu(last->data_address) +
2559 le16_to_cpu(last->req_count) -
2560 le16_to_cpu(last->res_count),
2561 ctx->base.callback_data);
2562
2563 return 1;
2564 }
2565
2566 static int handle_it_packet(struct context *context,
2567 struct descriptor *d,
2568 struct descriptor *last)
2569 {
2570 struct iso_context *ctx =
2571 container_of(context, struct iso_context, context);
2572 int i;
2573 struct descriptor *pd;
2574
2575 for (pd = d; pd <= last; pd++)
2576 if (pd->transfer_status)
2577 break;
2578 if (pd > last)
2579 /* Descriptor(s) not done yet, stop iteration */
2580 return 0;
2581
2582 i = ctx->header_length;
2583 if (i + 4 < PAGE_SIZE) {
2584 /* Present this value as big-endian to match the receive code */
2585 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2586 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2587 le16_to_cpu(pd->res_count));
2588 ctx->header_length += 4;
2589 }
2590 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2591 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2592 ctx->header_length, ctx->header,
2593 ctx->base.callback_data);
2594 ctx->header_length = 0;
2595 }
2596 return 1;
2597 }
2598
2599 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2600 {
2601 u32 hi = channels >> 32, lo = channels;
2602
2603 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2604 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2605 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2606 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2607 mmiowb();
2608 ohci->mc_channels = channels;
2609 }
2610
2611 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2612 int type, int channel, size_t header_size)
2613 {
2614 struct fw_ohci *ohci = fw_ohci(card);
2615 struct iso_context *uninitialized_var(ctx);
2616 descriptor_callback_t uninitialized_var(callback);
2617 u64 *uninitialized_var(channels);
2618 u32 *uninitialized_var(mask), uninitialized_var(regs);
2619 unsigned long flags;
2620 int index, ret = -EBUSY;
2621
2622 spin_lock_irqsave(&ohci->lock, flags);
2623
2624 switch (type) {
2625 case FW_ISO_CONTEXT_TRANSMIT:
2626 mask = &ohci->it_context_mask;
2627 callback = handle_it_packet;
2628 index = ffs(*mask) - 1;
2629 if (index >= 0) {
2630 *mask &= ~(1 << index);
2631 regs = OHCI1394_IsoXmitContextBase(index);
2632 ctx = &ohci->it_context_list[index];
2633 }
2634 break;
2635
2636 case FW_ISO_CONTEXT_RECEIVE:
2637 channels = &ohci->ir_context_channels;
2638 mask = &ohci->ir_context_mask;
2639 callback = handle_ir_packet_per_buffer;
2640 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2641 if (index >= 0) {
2642 *channels &= ~(1ULL << channel);
2643 *mask &= ~(1 << index);
2644 regs = OHCI1394_IsoRcvContextBase(index);
2645 ctx = &ohci->ir_context_list[index];
2646 }
2647 break;
2648
2649 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2650 mask = &ohci->ir_context_mask;
2651 callback = handle_ir_buffer_fill;
2652 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2653 if (index >= 0) {
2654 ohci->mc_allocated = true;
2655 *mask &= ~(1 << index);
2656 regs = OHCI1394_IsoRcvContextBase(index);
2657 ctx = &ohci->ir_context_list[index];
2658 }
2659 break;
2660
2661 default:
2662 index = -1;
2663 ret = -ENOSYS;
2664 }
2665
2666 spin_unlock_irqrestore(&ohci->lock, flags);
2667
2668 if (index < 0)
2669 return ERR_PTR(ret);
2670
2671 memset(ctx, 0, sizeof(*ctx));
2672 ctx->header_length = 0;
2673 ctx->header = (void *) __get_free_page(GFP_KERNEL);
2674 if (ctx->header == NULL) {
2675 ret = -ENOMEM;
2676 goto out;
2677 }
2678 ret = context_init(&ctx->context, ohci, regs, callback);
2679 if (ret < 0)
2680 goto out_with_header;
2681
2682 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2683 set_multichannel_mask(ohci, 0);
2684
2685 return &ctx->base;
2686
2687 out_with_header:
2688 free_page((unsigned long)ctx->header);
2689 out:
2690 spin_lock_irqsave(&ohci->lock, flags);
2691
2692 switch (type) {
2693 case FW_ISO_CONTEXT_RECEIVE:
2694 *channels |= 1ULL << channel;
2695 break;
2696
2697 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2698 ohci->mc_allocated = false;
2699 break;
2700 }
2701 *mask |= 1 << index;
2702
2703 spin_unlock_irqrestore(&ohci->lock, flags);
2704
2705 return ERR_PTR(ret);
2706 }
2707
2708 static int ohci_start_iso(struct fw_iso_context *base,
2709 s32 cycle, u32 sync, u32 tags)
2710 {
2711 struct iso_context *ctx = container_of(base, struct iso_context, base);
2712 struct fw_ohci *ohci = ctx->context.ohci;
2713 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2714 int index;
2715
2716 /* the controller cannot start without any queued packets */
2717 if (ctx->context.last->branch_address == 0)
2718 return -ENODATA;
2719
2720 switch (ctx->base.type) {
2721 case FW_ISO_CONTEXT_TRANSMIT:
2722 index = ctx - ohci->it_context_list;
2723 match = 0;
2724 if (cycle >= 0)
2725 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2726 (cycle & 0x7fff) << 16;
2727
2728 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2729 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2730 context_run(&ctx->context, match);
2731 break;
2732
2733 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2734 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2735 /* fall through */
2736 case FW_ISO_CONTEXT_RECEIVE:
2737 index = ctx - ohci->ir_context_list;
2738 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2739 if (cycle >= 0) {
2740 match |= (cycle & 0x07fff) << 12;
2741 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2742 }
2743
2744 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2745 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2746 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2747 context_run(&ctx->context, control);
2748
2749 ctx->sync = sync;
2750 ctx->tags = tags;
2751
2752 break;
2753 }
2754
2755 return 0;
2756 }
2757
2758 static int ohci_stop_iso(struct fw_iso_context *base)
2759 {
2760 struct fw_ohci *ohci = fw_ohci(base->card);
2761 struct iso_context *ctx = container_of(base, struct iso_context, base);
2762 int index;
2763
2764 switch (ctx->base.type) {
2765 case FW_ISO_CONTEXT_TRANSMIT:
2766 index = ctx - ohci->it_context_list;
2767 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2768 break;
2769
2770 case FW_ISO_CONTEXT_RECEIVE:
2771 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2772 index = ctx - ohci->ir_context_list;
2773 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2774 break;
2775 }
2776 flush_writes(ohci);
2777 context_stop(&ctx->context);
2778 tasklet_kill(&ctx->context.tasklet);
2779
2780 return 0;
2781 }
2782
2783 static void ohci_free_iso_context(struct fw_iso_context *base)
2784 {
2785 struct fw_ohci *ohci = fw_ohci(base->card);
2786 struct iso_context *ctx = container_of(base, struct iso_context, base);
2787 unsigned long flags;
2788 int index;
2789
2790 ohci_stop_iso(base);
2791 context_release(&ctx->context);
2792 free_page((unsigned long)ctx->header);
2793
2794 spin_lock_irqsave(&ohci->lock, flags);
2795
2796 switch (base->type) {
2797 case FW_ISO_CONTEXT_TRANSMIT:
2798 index = ctx - ohci->it_context_list;
2799 ohci->it_context_mask |= 1 << index;
2800 break;
2801
2802 case FW_ISO_CONTEXT_RECEIVE:
2803 index = ctx - ohci->ir_context_list;
2804 ohci->ir_context_mask |= 1 << index;
2805 ohci->ir_context_channels |= 1ULL << base->channel;
2806 break;
2807
2808 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2809 index = ctx - ohci->ir_context_list;
2810 ohci->ir_context_mask |= 1 << index;
2811 ohci->ir_context_channels |= ohci->mc_channels;
2812 ohci->mc_channels = 0;
2813 ohci->mc_allocated = false;
2814 break;
2815 }
2816
2817 spin_unlock_irqrestore(&ohci->lock, flags);
2818 }
2819
2820 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2821 {
2822 struct fw_ohci *ohci = fw_ohci(base->card);
2823 unsigned long flags;
2824 int ret;
2825
2826 switch (base->type) {
2827 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2828
2829 spin_lock_irqsave(&ohci->lock, flags);
2830
2831 /* Don't allow multichannel to grab other contexts' channels. */
2832 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2833 *channels = ohci->ir_context_channels;
2834 ret = -EBUSY;
2835 } else {
2836 set_multichannel_mask(ohci, *channels);
2837 ret = 0;
2838 }
2839
2840 spin_unlock_irqrestore(&ohci->lock, flags);
2841
2842 break;
2843 default:
2844 ret = -EINVAL;
2845 }
2846
2847 return ret;
2848 }
2849
2850 #ifdef CONFIG_PM
2851 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
2852 {
2853 int i;
2854 struct iso_context *ctx;
2855
2856 for (i = 0 ; i < ohci->n_ir ; i++) {
2857 ctx = &ohci->ir_context_list[i];
2858 if (ctx->context.running)
2859 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
2860 }
2861
2862 for (i = 0 ; i < ohci->n_it ; i++) {
2863 ctx = &ohci->it_context_list[i];
2864 if (ctx->context.running)
2865 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
2866 }
2867 }
2868 #endif
2869
2870 static int queue_iso_transmit(struct iso_context *ctx,
2871 struct fw_iso_packet *packet,
2872 struct fw_iso_buffer *buffer,
2873 unsigned long payload)
2874 {
2875 struct descriptor *d, *last, *pd;
2876 struct fw_iso_packet *p;
2877 __le32 *header;
2878 dma_addr_t d_bus, page_bus;
2879 u32 z, header_z, payload_z, irq;
2880 u32 payload_index, payload_end_index, next_page_index;
2881 int page, end_page, i, length, offset;
2882
2883 p = packet;
2884 payload_index = payload;
2885
2886 if (p->skip)
2887 z = 1;
2888 else
2889 z = 2;
2890 if (p->header_length > 0)
2891 z++;
2892
2893 /* Determine the first page the payload isn't contained in. */
2894 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2895 if (p->payload_length > 0)
2896 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2897 else
2898 payload_z = 0;
2899
2900 z += payload_z;
2901
2902 /* Get header size in number of descriptors. */
2903 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2904
2905 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2906 if (d == NULL)
2907 return -ENOMEM;
2908
2909 if (!p->skip) {
2910 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2911 d[0].req_count = cpu_to_le16(8);
2912 /*
2913 * Link the skip address to this descriptor itself. This causes
2914 * a context to skip a cycle whenever lost cycles or FIFO
2915 * overruns occur, without dropping the data. The application
2916 * should then decide whether this is an error condition or not.
2917 * FIXME: Make the context's cycle-lost behaviour configurable?
2918 */
2919 d[0].branch_address = cpu_to_le32(d_bus | z);
2920
2921 header = (__le32 *) &d[1];
2922 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2923 IT_HEADER_TAG(p->tag) |
2924 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2925 IT_HEADER_CHANNEL(ctx->base.channel) |
2926 IT_HEADER_SPEED(ctx->base.speed));
2927 header[1] =
2928 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2929 p->payload_length));
2930 }
2931
2932 if (p->header_length > 0) {
2933 d[2].req_count = cpu_to_le16(p->header_length);
2934 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2935 memcpy(&d[z], p->header, p->header_length);
2936 }
2937
2938 pd = d + z - payload_z;
2939 payload_end_index = payload_index + p->payload_length;
2940 for (i = 0; i < payload_z; i++) {
2941 page = payload_index >> PAGE_SHIFT;
2942 offset = payload_index & ~PAGE_MASK;
2943 next_page_index = (page + 1) << PAGE_SHIFT;
2944 length =
2945 min(next_page_index, payload_end_index) - payload_index;
2946 pd[i].req_count = cpu_to_le16(length);
2947
2948 page_bus = page_private(buffer->pages[page]);
2949 pd[i].data_address = cpu_to_le32(page_bus + offset);
2950
2951 payload_index += length;
2952 }
2953
2954 if (p->interrupt)
2955 irq = DESCRIPTOR_IRQ_ALWAYS;
2956 else
2957 irq = DESCRIPTOR_NO_IRQ;
2958
2959 last = z == 2 ? d : d + z - 1;
2960 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2961 DESCRIPTOR_STATUS |
2962 DESCRIPTOR_BRANCH_ALWAYS |
2963 irq);
2964
2965 context_append(&ctx->context, d, z, header_z);
2966
2967 return 0;
2968 }
2969
2970 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2971 struct fw_iso_packet *packet,
2972 struct fw_iso_buffer *buffer,
2973 unsigned long payload)
2974 {
2975 struct descriptor *d, *pd;
2976 dma_addr_t d_bus, page_bus;
2977 u32 z, header_z, rest;
2978 int i, j, length;
2979 int page, offset, packet_count, header_size, payload_per_buffer;
2980
2981 /*
2982 * The OHCI controller puts the isochronous header and trailer in the
2983 * buffer, so we need at least 8 bytes.
2984 */
2985 packet_count = packet->header_length / ctx->base.header_size;
2986 header_size = max(ctx->base.header_size, (size_t)8);
2987
2988 /* Get header size in number of descriptors. */
2989 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2990 page = payload >> PAGE_SHIFT;
2991 offset = payload & ~PAGE_MASK;
2992 payload_per_buffer = packet->payload_length / packet_count;
2993
2994 for (i = 0; i < packet_count; i++) {
2995 /* d points to the header descriptor */
2996 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2997 d = context_get_descriptors(&ctx->context,
2998 z + header_z, &d_bus);
2999 if (d == NULL)
3000 return -ENOMEM;
3001
3002 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
3003 DESCRIPTOR_INPUT_MORE);
3004 if (packet->skip && i == 0)
3005 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3006 d->req_count = cpu_to_le16(header_size);
3007 d->res_count = d->req_count;
3008 d->transfer_status = 0;
3009 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3010
3011 rest = payload_per_buffer;
3012 pd = d;
3013 for (j = 1; j < z; j++) {
3014 pd++;
3015 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3016 DESCRIPTOR_INPUT_MORE);
3017
3018 if (offset + rest < PAGE_SIZE)
3019 length = rest;
3020 else
3021 length = PAGE_SIZE - offset;
3022 pd->req_count = cpu_to_le16(length);
3023 pd->res_count = pd->req_count;
3024 pd->transfer_status = 0;
3025
3026 page_bus = page_private(buffer->pages[page]);
3027 pd->data_address = cpu_to_le32(page_bus + offset);
3028
3029 offset = (offset + length) & ~PAGE_MASK;
3030 rest -= length;
3031 if (offset == 0)
3032 page++;
3033 }
3034 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3035 DESCRIPTOR_INPUT_LAST |
3036 DESCRIPTOR_BRANCH_ALWAYS);
3037 if (packet->interrupt && i == packet_count - 1)
3038 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3039
3040 context_append(&ctx->context, d, z, header_z);
3041 }
3042
3043 return 0;
3044 }
3045
3046 static int queue_iso_buffer_fill(struct iso_context *ctx,
3047 struct fw_iso_packet *packet,
3048 struct fw_iso_buffer *buffer,
3049 unsigned long payload)
3050 {
3051 struct descriptor *d;
3052 dma_addr_t d_bus, page_bus;
3053 int page, offset, rest, z, i, length;
3054
3055 page = payload >> PAGE_SHIFT;
3056 offset = payload & ~PAGE_MASK;
3057 rest = packet->payload_length;
3058
3059 /* We need one descriptor for each page in the buffer. */
3060 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3061
3062 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3063 return -EFAULT;
3064
3065 for (i = 0; i < z; i++) {
3066 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3067 if (d == NULL)
3068 return -ENOMEM;
3069
3070 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3071 DESCRIPTOR_BRANCH_ALWAYS);
3072 if (packet->skip && i == 0)
3073 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3074 if (packet->interrupt && i == z - 1)
3075 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3076
3077 if (offset + rest < PAGE_SIZE)
3078 length = rest;
3079 else
3080 length = PAGE_SIZE - offset;
3081 d->req_count = cpu_to_le16(length);
3082 d->res_count = d->req_count;
3083 d->transfer_status = 0;
3084
3085 page_bus = page_private(buffer->pages[page]);
3086 d->data_address = cpu_to_le32(page_bus + offset);
3087
3088 rest -= length;
3089 offset = 0;
3090 page++;
3091
3092 context_append(&ctx->context, d, 1, 0);
3093 }
3094
3095 return 0;
3096 }
3097
3098 static int ohci_queue_iso(struct fw_iso_context *base,
3099 struct fw_iso_packet *packet,
3100 struct fw_iso_buffer *buffer,
3101 unsigned long payload)
3102 {
3103 struct iso_context *ctx = container_of(base, struct iso_context, base);
3104 unsigned long flags;
3105 int ret = -ENOSYS;
3106
3107 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3108 switch (base->type) {
3109 case FW_ISO_CONTEXT_TRANSMIT:
3110 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3111 break;
3112 case FW_ISO_CONTEXT_RECEIVE:
3113 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3114 break;
3115 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3116 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3117 break;
3118 }
3119 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3120
3121 return ret;
3122 }
3123
3124 static const struct fw_card_driver ohci_driver = {
3125 .enable = ohci_enable,
3126 .read_phy_reg = ohci_read_phy_reg,
3127 .update_phy_reg = ohci_update_phy_reg,
3128 .set_config_rom = ohci_set_config_rom,
3129 .send_request = ohci_send_request,
3130 .send_response = ohci_send_response,
3131 .cancel_packet = ohci_cancel_packet,
3132 .enable_phys_dma = ohci_enable_phys_dma,
3133 .read_csr = ohci_read_csr,
3134 .write_csr = ohci_write_csr,
3135
3136 .allocate_iso_context = ohci_allocate_iso_context,
3137 .free_iso_context = ohci_free_iso_context,
3138 .set_iso_channels = ohci_set_iso_channels,
3139 .queue_iso = ohci_queue_iso,
3140 .start_iso = ohci_start_iso,
3141 .stop_iso = ohci_stop_iso,
3142 };
3143
3144 #ifdef CONFIG_PPC_PMAC
3145 static void pmac_ohci_on(struct pci_dev *dev)
3146 {
3147 if (machine_is(powermac)) {
3148 struct device_node *ofn = pci_device_to_OF_node(dev);
3149
3150 if (ofn) {
3151 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3152 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3153 }
3154 }
3155 }
3156
3157 static void pmac_ohci_off(struct pci_dev *dev)
3158 {
3159 if (machine_is(powermac)) {
3160 struct device_node *ofn = pci_device_to_OF_node(dev);
3161
3162 if (ofn) {
3163 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3164 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3165 }
3166 }
3167 }
3168 #else
3169 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3170 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3171 #endif /* CONFIG_PPC_PMAC */
3172
3173 static int __devinit pci_probe(struct pci_dev *dev,
3174 const struct pci_device_id *ent)
3175 {
3176 struct fw_ohci *ohci;
3177 u32 bus_options, max_receive, link_speed, version;
3178 u64 guid;
3179 int i, err;
3180 size_t size;
3181
3182 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3183 if (ohci == NULL) {
3184 err = -ENOMEM;
3185 goto fail;
3186 }
3187
3188 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3189
3190 pmac_ohci_on(dev);
3191
3192 err = pci_enable_device(dev);
3193 if (err) {
3194 fw_error("Failed to enable OHCI hardware\n");
3195 goto fail_free;
3196 }
3197
3198 pci_set_master(dev);
3199 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3200 pci_set_drvdata(dev, ohci);
3201
3202 spin_lock_init(&ohci->lock);
3203 mutex_init(&ohci->phy_reg_mutex);
3204
3205 tasklet_init(&ohci->bus_reset_tasklet,
3206 bus_reset_tasklet, (unsigned long)ohci);
3207
3208 err = pci_request_region(dev, 0, ohci_driver_name);
3209 if (err) {
3210 fw_error("MMIO resource unavailable\n");
3211 goto fail_disable;
3212 }
3213
3214 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3215 if (ohci->registers == NULL) {
3216 fw_error("Failed to remap registers\n");
3217 err = -ENXIO;
3218 goto fail_iomem;
3219 }
3220
3221 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3222 if ((ohci_quirks[i].vendor == dev->vendor) &&
3223 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3224 ohci_quirks[i].device == dev->device) &&
3225 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3226 ohci_quirks[i].revision >= dev->revision)) {
3227 ohci->quirks = ohci_quirks[i].flags;
3228 break;
3229 }
3230 if (param_quirks)
3231 ohci->quirks = param_quirks;
3232
3233 /*
3234 * Because dma_alloc_coherent() allocates at least one page,
3235 * we save space by using a common buffer for the AR request/
3236 * response descriptors and the self IDs buffer.
3237 */
3238 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3239 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3240 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3241 PAGE_SIZE,
3242 &ohci->misc_buffer_bus,
3243 GFP_KERNEL);
3244 if (!ohci->misc_buffer) {
3245 err = -ENOMEM;
3246 goto fail_iounmap;
3247 }
3248
3249 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3250 OHCI1394_AsReqRcvContextControlSet);
3251 if (err < 0)
3252 goto fail_misc_buf;
3253
3254 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3255 OHCI1394_AsRspRcvContextControlSet);
3256 if (err < 0)
3257 goto fail_arreq_ctx;
3258
3259 err = context_init(&ohci->at_request_ctx, ohci,
3260 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3261 if (err < 0)
3262 goto fail_arrsp_ctx;
3263
3264 err = context_init(&ohci->at_response_ctx, ohci,
3265 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3266 if (err < 0)
3267 goto fail_atreq_ctx;
3268
3269 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3270 ohci->ir_context_channels = ~0ULL;
3271 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3272 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3273 ohci->ir_context_mask = ohci->ir_context_support;
3274 ohci->n_ir = hweight32(ohci->ir_context_mask);
3275 size = sizeof(struct iso_context) * ohci->n_ir;
3276 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3277
3278 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3279 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3280 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3281 ohci->it_context_mask = ohci->it_context_support;
3282 ohci->n_it = hweight32(ohci->it_context_mask);
3283 size = sizeof(struct iso_context) * ohci->n_it;
3284 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3285
3286 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3287 err = -ENOMEM;
3288 goto fail_contexts;
3289 }
3290
3291 ohci->self_id_cpu = ohci->misc_buffer + PAGE_SIZE/2;
3292 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3293
3294 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3295 max_receive = (bus_options >> 12) & 0xf;
3296 link_speed = bus_options & 0x7;
3297 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3298 reg_read(ohci, OHCI1394_GUIDLo);
3299
3300 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3301 if (err)
3302 goto fail_contexts;
3303
3304 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3305 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
3306 "%d IR + %d IT contexts, quirks 0x%x\n",
3307 dev_name(&dev->dev), version >> 16, version & 0xff,
3308 ohci->n_ir, ohci->n_it, ohci->quirks);
3309
3310 return 0;
3311
3312 fail_contexts:
3313 kfree(ohci->ir_context_list);
3314 kfree(ohci->it_context_list);
3315 context_release(&ohci->at_response_ctx);
3316 fail_atreq_ctx:
3317 context_release(&ohci->at_request_ctx);
3318 fail_arrsp_ctx:
3319 ar_context_release(&ohci->ar_response_ctx);
3320 fail_arreq_ctx:
3321 ar_context_release(&ohci->ar_request_ctx);
3322 fail_misc_buf:
3323 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3324 ohci->misc_buffer, ohci->misc_buffer_bus);
3325 fail_iounmap:
3326 pci_iounmap(dev, ohci->registers);
3327 fail_iomem:
3328 pci_release_region(dev, 0);
3329 fail_disable:
3330 pci_disable_device(dev);
3331 fail_free:
3332 kfree(ohci);
3333 pmac_ohci_off(dev);
3334 fail:
3335 if (err == -ENOMEM)
3336 fw_error("Out of memory\n");
3337
3338 return err;
3339 }
3340
3341 static void pci_remove(struct pci_dev *dev)
3342 {
3343 struct fw_ohci *ohci;
3344
3345 ohci = pci_get_drvdata(dev);
3346 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3347 flush_writes(ohci);
3348 fw_core_remove_card(&ohci->card);
3349
3350 /*
3351 * FIXME: Fail all pending packets here, now that the upper
3352 * layers can't queue any more.
3353 */
3354
3355 software_reset(ohci);
3356 free_irq(dev->irq, ohci);
3357
3358 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3359 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3360 ohci->next_config_rom, ohci->next_config_rom_bus);
3361 if (ohci->config_rom)
3362 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3363 ohci->config_rom, ohci->config_rom_bus);
3364 ar_context_release(&ohci->ar_request_ctx);
3365 ar_context_release(&ohci->ar_response_ctx);
3366 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3367 ohci->misc_buffer, ohci->misc_buffer_bus);
3368 context_release(&ohci->at_request_ctx);
3369 context_release(&ohci->at_response_ctx);
3370 kfree(ohci->it_context_list);
3371 kfree(ohci->ir_context_list);
3372 pci_disable_msi(dev);
3373 pci_iounmap(dev, ohci->registers);
3374 pci_release_region(dev, 0);
3375 pci_disable_device(dev);
3376 kfree(ohci);
3377 pmac_ohci_off(dev);
3378
3379 fw_notify("Removed fw-ohci device.\n");
3380 }
3381
3382 #ifdef CONFIG_PM
3383 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3384 {
3385 struct fw_ohci *ohci = pci_get_drvdata(dev);
3386 int err;
3387
3388 software_reset(ohci);
3389 free_irq(dev->irq, ohci);
3390 pci_disable_msi(dev);
3391 err = pci_save_state(dev);
3392 if (err) {
3393 fw_error("pci_save_state failed\n");
3394 return err;
3395 }
3396 err = pci_set_power_state(dev, pci_choose_state(dev, state));
3397 if (err)
3398 fw_error("pci_set_power_state failed with %d\n", err);
3399 pmac_ohci_off(dev);
3400
3401 return 0;
3402 }
3403
3404 static int pci_resume(struct pci_dev *dev)
3405 {
3406 struct fw_ohci *ohci = pci_get_drvdata(dev);
3407 int err;
3408
3409 pmac_ohci_on(dev);
3410 pci_set_power_state(dev, PCI_D0);
3411 pci_restore_state(dev);
3412 err = pci_enable_device(dev);
3413 if (err) {
3414 fw_error("pci_enable_device failed\n");
3415 return err;
3416 }
3417
3418 /* Some systems don't setup GUID register on resume from ram */
3419 if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3420 !reg_read(ohci, OHCI1394_GUIDHi)) {
3421 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3422 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3423 }
3424
3425 err = ohci_enable(&ohci->card, NULL, 0);
3426 if (err)
3427 return err;
3428
3429 ohci_resume_iso_dma(ohci);
3430
3431 return 0;
3432 }
3433 #endif
3434
3435 static const struct pci_device_id pci_table[] = {
3436 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3437 { }
3438 };
3439
3440 MODULE_DEVICE_TABLE(pci, pci_table);
3441
3442 static struct pci_driver fw_ohci_pci_driver = {
3443 .name = ohci_driver_name,
3444 .id_table = pci_table,
3445 .probe = pci_probe,
3446 .remove = pci_remove,
3447 #ifdef CONFIG_PM
3448 .resume = pci_resume,
3449 .suspend = pci_suspend,
3450 #endif
3451 };
3452
3453 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3454 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3455 MODULE_LICENSE("GPL");
3456
3457 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3458 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3459 MODULE_ALIAS("ohci1394");
3460 #endif
3461
3462 static int __init fw_ohci_init(void)
3463 {
3464 return pci_register_driver(&fw_ohci_pci_driver);
3465 }
3466
3467 static void __exit fw_ohci_cleanup(void)
3468 {
3469 pci_unregister_driver(&fw_ohci_pci_driver);
3470 }
3471
3472 module_init(fw_ohci_init);
3473 module_exit(fw_ohci_cleanup);
Linux kernel - Deliverables
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