2 * Atheros AR71XX/AR724X/AR913X GPIO API support
4 * Copyright (C) 2015 Alban Bedel <albeu@free.fr>
5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/gpio/driver.h>
15 #include <linux/platform_data/gpio-ath79.h>
16 #include <linux/of_device.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
20 #define AR71XX_GPIO_REG_OE 0x00
21 #define AR71XX_GPIO_REG_IN 0x04
22 #define AR71XX_GPIO_REG_SET 0x0c
23 #define AR71XX_GPIO_REG_CLEAR 0x10
25 #define AR71XX_GPIO_REG_INT_ENABLE 0x14
26 #define AR71XX_GPIO_REG_INT_TYPE 0x18
27 #define AR71XX_GPIO_REG_INT_POLARITY 0x1c
28 #define AR71XX_GPIO_REG_INT_PENDING 0x20
29 #define AR71XX_GPIO_REG_INT_MASK 0x24
31 struct ath79_gpio_ctrl
{
35 unsigned long both_edges
;
38 static struct ath79_gpio_ctrl
*irq_data_to_ath79_gpio(struct irq_data
*data
)
40 struct gpio_chip
*gc
= irq_data_get_irq_chip_data(data
);
42 return container_of(gc
, struct ath79_gpio_ctrl
, gc
);
45 static u32
ath79_gpio_read(struct ath79_gpio_ctrl
*ctrl
, unsigned reg
)
47 return readl(ctrl
->base
+ reg
);
50 static void ath79_gpio_write(struct ath79_gpio_ctrl
*ctrl
,
51 unsigned reg
, u32 val
)
53 return writel(val
, ctrl
->base
+ reg
);
56 static bool ath79_gpio_update_bits(
57 struct ath79_gpio_ctrl
*ctrl
, unsigned reg
, u32 mask
, u32 bits
)
61 old_val
= ath79_gpio_read(ctrl
, reg
);
62 new_val
= (old_val
& ~mask
) | (bits
& mask
);
64 if (new_val
!= old_val
)
65 ath79_gpio_write(ctrl
, reg
, new_val
);
67 return new_val
!= old_val
;
70 static void ath79_gpio_irq_unmask(struct irq_data
*data
)
72 struct ath79_gpio_ctrl
*ctrl
= irq_data_to_ath79_gpio(data
);
73 u32 mask
= BIT(irqd_to_hwirq(data
));
76 spin_lock_irqsave(&ctrl
->lock
, flags
);
77 ath79_gpio_update_bits(ctrl
, AR71XX_GPIO_REG_INT_MASK
, mask
, mask
);
78 spin_unlock_irqrestore(&ctrl
->lock
, flags
);
81 static void ath79_gpio_irq_mask(struct irq_data
*data
)
83 struct ath79_gpio_ctrl
*ctrl
= irq_data_to_ath79_gpio(data
);
84 u32 mask
= BIT(irqd_to_hwirq(data
));
87 spin_lock_irqsave(&ctrl
->lock
, flags
);
88 ath79_gpio_update_bits(ctrl
, AR71XX_GPIO_REG_INT_MASK
, mask
, 0);
89 spin_unlock_irqrestore(&ctrl
->lock
, flags
);
92 static void ath79_gpio_irq_enable(struct irq_data
*data
)
94 struct ath79_gpio_ctrl
*ctrl
= irq_data_to_ath79_gpio(data
);
95 u32 mask
= BIT(irqd_to_hwirq(data
));
98 spin_lock_irqsave(&ctrl
->lock
, flags
);
99 ath79_gpio_update_bits(ctrl
, AR71XX_GPIO_REG_INT_ENABLE
, mask
, mask
);
100 ath79_gpio_update_bits(ctrl
, AR71XX_GPIO_REG_INT_MASK
, mask
, mask
);
101 spin_unlock_irqrestore(&ctrl
->lock
, flags
);
104 static void ath79_gpio_irq_disable(struct irq_data
*data
)
106 struct ath79_gpio_ctrl
*ctrl
= irq_data_to_ath79_gpio(data
);
107 u32 mask
= BIT(irqd_to_hwirq(data
));
110 spin_lock_irqsave(&ctrl
->lock
, flags
);
111 ath79_gpio_update_bits(ctrl
, AR71XX_GPIO_REG_INT_MASK
, mask
, 0);
112 ath79_gpio_update_bits(ctrl
, AR71XX_GPIO_REG_INT_ENABLE
, mask
, 0);
113 spin_unlock_irqrestore(&ctrl
->lock
, flags
);
116 static int ath79_gpio_irq_set_type(struct irq_data
*data
,
117 unsigned int flow_type
)
119 struct ath79_gpio_ctrl
*ctrl
= irq_data_to_ath79_gpio(data
);
120 u32 mask
= BIT(irqd_to_hwirq(data
));
121 u32 type
= 0, polarity
= 0;
126 case IRQ_TYPE_EDGE_RISING
:
128 case IRQ_TYPE_EDGE_FALLING
:
129 case IRQ_TYPE_EDGE_BOTH
:
132 case IRQ_TYPE_LEVEL_HIGH
:
134 case IRQ_TYPE_LEVEL_LOW
:
142 spin_lock_irqsave(&ctrl
->lock
, flags
);
144 if (flow_type
== IRQ_TYPE_EDGE_BOTH
) {
145 ctrl
->both_edges
|= mask
;
146 polarity
= ~ath79_gpio_read(ctrl
, AR71XX_GPIO_REG_IN
);
148 ctrl
->both_edges
&= ~mask
;
151 /* As the IRQ configuration can't be loaded atomically we
152 * have to disable the interrupt while the configuration state
155 disabled
= ath79_gpio_update_bits(
156 ctrl
, AR71XX_GPIO_REG_INT_ENABLE
, mask
, 0);
158 ath79_gpio_update_bits(
159 ctrl
, AR71XX_GPIO_REG_INT_TYPE
, mask
, type
);
160 ath79_gpio_update_bits(
161 ctrl
, AR71XX_GPIO_REG_INT_POLARITY
, mask
, polarity
);
164 ath79_gpio_update_bits(
165 ctrl
, AR71XX_GPIO_REG_INT_ENABLE
, mask
, mask
);
167 spin_unlock_irqrestore(&ctrl
->lock
, flags
);
172 static struct irq_chip ath79_gpio_irqchip
= {
173 .name
= "gpio-ath79",
174 .irq_enable
= ath79_gpio_irq_enable
,
175 .irq_disable
= ath79_gpio_irq_disable
,
176 .irq_mask
= ath79_gpio_irq_mask
,
177 .irq_unmask
= ath79_gpio_irq_unmask
,
178 .irq_set_type
= ath79_gpio_irq_set_type
,
181 static void ath79_gpio_irq_handler(struct irq_desc
*desc
)
183 struct gpio_chip
*gc
= irq_desc_get_handler_data(desc
);
184 struct irq_chip
*irqchip
= irq_desc_get_chip(desc
);
185 struct ath79_gpio_ctrl
*ctrl
=
186 container_of(gc
, struct ath79_gpio_ctrl
, gc
);
187 unsigned long flags
, pending
;
188 u32 both_edges
, state
;
191 chained_irq_enter(irqchip
, desc
);
193 spin_lock_irqsave(&ctrl
->lock
, flags
);
195 pending
= ath79_gpio_read(ctrl
, AR71XX_GPIO_REG_INT_PENDING
);
197 /* Update the polarity of the both edges irqs */
198 both_edges
= ctrl
->both_edges
& pending
;
200 state
= ath79_gpio_read(ctrl
, AR71XX_GPIO_REG_IN
);
201 ath79_gpio_update_bits(ctrl
, AR71XX_GPIO_REG_INT_POLARITY
,
205 spin_unlock_irqrestore(&ctrl
->lock
, flags
);
208 for_each_set_bit(irq
, &pending
, gc
->ngpio
)
210 irq_linear_revmap(gc
->irqdomain
, irq
));
213 chained_irq_exit(irqchip
, desc
);
216 static const struct of_device_id ath79_gpio_of_match
[] = {
217 { .compatible
= "qca,ar7100-gpio" },
218 { .compatible
= "qca,ar9340-gpio" },
222 static int ath79_gpio_probe(struct platform_device
*pdev
)
224 struct ath79_gpio_platform_data
*pdata
= dev_get_platdata(&pdev
->dev
);
225 struct device_node
*np
= pdev
->dev
.of_node
;
226 struct ath79_gpio_ctrl
*ctrl
;
227 struct resource
*res
;
228 u32 ath79_gpio_count
;
232 ctrl
= devm_kzalloc(&pdev
->dev
, sizeof(*ctrl
), GFP_KERNEL
);
235 platform_set_drvdata(pdev
, ctrl
);
238 err
= of_property_read_u32(np
, "ngpios", &ath79_gpio_count
);
240 dev_err(&pdev
->dev
, "ngpios property is not valid\n");
243 oe_inverted
= of_device_is_compatible(np
, "qca,ar9340-gpio");
245 ath79_gpio_count
= pdata
->ngpios
;
246 oe_inverted
= pdata
->oe_inverted
;
248 dev_err(&pdev
->dev
, "No DT node or platform data found\n");
252 if (ath79_gpio_count
>= 32) {
253 dev_err(&pdev
->dev
, "ngpios must be less than 32\n");
257 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
258 ctrl
->base
= devm_ioremap_nocache(
259 &pdev
->dev
, res
->start
, resource_size(res
));
263 spin_lock_init(&ctrl
->lock
);
264 err
= bgpio_init(&ctrl
->gc
, &pdev
->dev
, 4,
265 ctrl
->base
+ AR71XX_GPIO_REG_IN
,
266 ctrl
->base
+ AR71XX_GPIO_REG_SET
,
267 ctrl
->base
+ AR71XX_GPIO_REG_CLEAR
,
268 oe_inverted
? NULL
: ctrl
->base
+ AR71XX_GPIO_REG_OE
,
269 oe_inverted
? ctrl
->base
+ AR71XX_GPIO_REG_OE
: NULL
,
272 dev_err(&pdev
->dev
, "bgpio_init failed\n");
275 /* Use base 0 to stay compatible with legacy platforms */
278 err
= gpiochip_add_data(&ctrl
->gc
, ctrl
);
281 "cannot add AR71xx GPIO chip, error=%d", err
);
285 if (np
&& !of_property_read_bool(np
, "interrupt-controller"))
288 err
= gpiochip_irqchip_add(&ctrl
->gc
, &ath79_gpio_irqchip
, 0,
289 handle_simple_irq
, IRQ_TYPE_NONE
);
291 dev_err(&pdev
->dev
, "failed to add gpiochip_irqchip\n");
292 goto gpiochip_remove
;
295 gpiochip_set_chained_irqchip(&ctrl
->gc
, &ath79_gpio_irqchip
,
296 platform_get_irq(pdev
, 0),
297 ath79_gpio_irq_handler
);
302 gpiochip_remove(&ctrl
->gc
);
306 static int ath79_gpio_remove(struct platform_device
*pdev
)
308 struct ath79_gpio_ctrl
*ctrl
= platform_get_drvdata(pdev
);
310 gpiochip_remove(&ctrl
->gc
);
314 static struct platform_driver ath79_gpio_driver
= {
316 .name
= "ath79-gpio",
317 .of_match_table
= ath79_gpio_of_match
,
319 .probe
= ath79_gpio_probe
,
320 .remove
= ath79_gpio_remove
,
323 module_platform_driver(ath79_gpio_driver
);