drivers/gpio/gpio-f7188x.c

   1 /*
   2  * GPIO driver for Fintek Super-I/O F71869, F71869A, F71882, F71889 and F81866
   3  *
   4  * Copyright (C) 2010-2013 LaCie
   5  *
   6  * Author: Simon Guinot <simon.guinot@sequanux.org>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/io.h>
  18 #include <linux/gpio/driver.h>
  19 #include <linux/bitops.h>
  20
  21 #define DRVNAME "gpio-f7188x"
  22
  23 /*
  24  * Super-I/O registers
  25  */
  26 #define SIO_LDSEL               0x07    /* Logical device select */
  27 #define SIO_DEVID               0x20    /* Device ID (2 bytes) */
  28 #define SIO_DEVREV              0x22    /* Device revision */
  29 #define SIO_MANID               0x23    /* Fintek ID (2 bytes) */
  30
  31 #define SIO_LD_GPIO             0x06    /* GPIO logical device */
  32 #define SIO_UNLOCK_KEY          0x87    /* Key to enable Super-I/O */
  33 #define SIO_LOCK_KEY            0xAA    /* Key to disable Super-I/O */
  34
  35 #define SIO_FINTEK_ID           0x1934  /* Manufacturer ID */
  36 #define SIO_F71869_ID           0x0814  /* F71869 chipset ID */
  37 #define SIO_F71869A_ID          0x1007  /* F71869A chipset ID */
  38 #define SIO_F71882_ID           0x0541  /* F71882 chipset ID */
  39 #define SIO_F71889_ID           0x0909  /* F71889 chipset ID */
  40 #define SIO_F81866_ID           0x1010  /* F81866 chipset ID */
  41
  42 enum chips { f71869, f71869a, f71882fg, f71889f, f81866 };
  43
  44 static const char * const f7188x_names[] = {
  45         "f71869",
  46         "f71869a",
  47         "f71882fg",
  48         "f71889f",
  49         "f81866",
  50 };
  51
  52 struct f7188x_sio {
  53         int addr;
  54         enum chips type;
  55 };
  56
  57 struct f7188x_gpio_bank {
  58         struct gpio_chip chip;
  59         unsigned int regbase;
  60         struct f7188x_gpio_data *data;
  61 };
  62
  63 struct f7188x_gpio_data {
  64         struct f7188x_sio *sio;
  65         int nr_bank;
  66         struct f7188x_gpio_bank *bank;
  67 };
  68
  69 /*
  70  * Super-I/O functions.
  71  */
  72
  73 static inline int superio_inb(int base, int reg)
  74 {
  75         outb(reg, base);
  76         return inb(base + 1);
  77 }
  78
  79 static int superio_inw(int base, int reg)
  80 {
  81         int val;
  82
  83         outb(reg++, base);
  84         val = inb(base + 1) << 8;
  85         outb(reg, base);
  86         val |= inb(base + 1);
  87
  88         return val;
  89 }
  90
  91 static inline void superio_outb(int base, int reg, int val)
  92 {
  93         outb(reg, base);
  94         outb(val, base + 1);
  95 }
  96
  97 static inline int superio_enter(int base)
  98 {
  99         /* Don't step on other drivers' I/O space by accident. */
 100         if (!request_muxed_region(base, 2, DRVNAME)) {
 101                 pr_err(DRVNAME "I/O address 0x%04x already in use\n", base);
 102                 return -EBUSY;
 103         }
 104
 105         /* According to the datasheet the key must be send twice. */
 106         outb(SIO_UNLOCK_KEY, base);
 107         outb(SIO_UNLOCK_KEY, base);
 108
 109         return 0;
 110 }
 111
 112 static inline void superio_select(int base, int ld)
 113 {
 114         outb(SIO_LDSEL, base);
 115         outb(ld, base + 1);
 116 }
 117
 118 static inline void superio_exit(int base)
 119 {
 120         outb(SIO_LOCK_KEY, base);
 121         release_region(base, 2);
 122 }
 123
 124 /*
 125  * GPIO chip.
 126  */
 127
 128 static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset);
 129 static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset);
 130 static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset);
 131 static int f7188x_gpio_direction_out(struct gpio_chip *chip,
 132                                      unsigned offset, int value);
 133 static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value);
 134 static int f7188x_gpio_set_single_ended(struct gpio_chip *gc,
 135                                         unsigned offset,
 136                                         enum single_ended_mode mode);
 137
 138 #define F7188X_GPIO_BANK(_base, _ngpio, _regbase)                       \
 139         {                                                               \
 140                 .chip = {                                               \
 141                         .label            = DRVNAME,                    \
 142                         .owner            = THIS_MODULE,                \
 143                         .get_direction    = f7188x_gpio_get_direction,  \
 144                         .direction_input  = f7188x_gpio_direction_in,   \
 145                         .get              = f7188x_gpio_get,            \
 146                         .direction_output = f7188x_gpio_direction_out,  \
 147                         .set              = f7188x_gpio_set,            \
 148                         .set_single_ended = f7188x_gpio_set_single_ended, \
 149                         .base             = _base,                      \
 150                         .ngpio            = _ngpio,                     \
 151                         .can_sleep        = true,                       \
 152                 },                                                      \
 153                 .regbase = _regbase,                                    \
 154         }
 155
 156 #define gpio_dir(base) (base + 0)
 157 #define gpio_data_out(base) (base + 1)
 158 #define gpio_data_in(base) (base + 2)
 159 /* Output mode register (0:open drain 1:push-pull). */
 160 #define gpio_out_mode(base) (base + 3)
 161
 162 static struct f7188x_gpio_bank f71869_gpio_bank[] = {
 163         F7188X_GPIO_BANK(0, 6, 0xF0),
 164         F7188X_GPIO_BANK(10, 8, 0xE0),
 165         F7188X_GPIO_BANK(20, 8, 0xD0),
 166         F7188X_GPIO_BANK(30, 8, 0xC0),
 167         F7188X_GPIO_BANK(40, 8, 0xB0),
 168         F7188X_GPIO_BANK(50, 5, 0xA0),
 169         F7188X_GPIO_BANK(60, 6, 0x90),
 170 };
 171
 172 static struct f7188x_gpio_bank f71869a_gpio_bank[] = {
 173         F7188X_GPIO_BANK(0, 6, 0xF0),
 174         F7188X_GPIO_BANK(10, 8, 0xE0),
 175         F7188X_GPIO_BANK(20, 8, 0xD0),
 176         F7188X_GPIO_BANK(30, 8, 0xC0),
 177         F7188X_GPIO_BANK(40, 8, 0xB0),
 178         F7188X_GPIO_BANK(50, 5, 0xA0),
 179         F7188X_GPIO_BANK(60, 8, 0x90),
 180         F7188X_GPIO_BANK(70, 8, 0x80),
 181 };
 182
 183 static struct f7188x_gpio_bank f71882_gpio_bank[] = {
 184         F7188X_GPIO_BANK(0, 8, 0xF0),
 185         F7188X_GPIO_BANK(10, 8, 0xE0),
 186         F7188X_GPIO_BANK(20, 8, 0xD0),
 187         F7188X_GPIO_BANK(30, 4, 0xC0),
 188         F7188X_GPIO_BANK(40, 4, 0xB0),
 189 };
 190
 191 static struct f7188x_gpio_bank f71889_gpio_bank[] = {
 192         F7188X_GPIO_BANK(0, 7, 0xF0),
 193         F7188X_GPIO_BANK(10, 7, 0xE0),
 194         F7188X_GPIO_BANK(20, 8, 0xD0),
 195         F7188X_GPIO_BANK(30, 8, 0xC0),
 196         F7188X_GPIO_BANK(40, 8, 0xB0),
 197         F7188X_GPIO_BANK(50, 5, 0xA0),
 198         F7188X_GPIO_BANK(60, 8, 0x90),
 199         F7188X_GPIO_BANK(70, 8, 0x80),
 200 };
 201
 202 static struct f7188x_gpio_bank f81866_gpio_bank[] = {
 203         F7188X_GPIO_BANK(0, 8, 0xF0),
 204         F7188X_GPIO_BANK(10, 8, 0xE0),
 205         F7188X_GPIO_BANK(20, 8, 0xD0),
 206         F7188X_GPIO_BANK(30, 8, 0xC0),
 207         F7188X_GPIO_BANK(40, 8, 0xB0),
 208         F7188X_GPIO_BANK(50, 8, 0xA0),
 209         F7188X_GPIO_BANK(60, 8, 0x90),
 210         F7188X_GPIO_BANK(70, 8, 0x80),
 211         F7188X_GPIO_BANK(80, 8, 0x88),
 212 };
 213
 214 static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
 215 {
 216         int err;
 217         struct f7188x_gpio_bank *bank =
 218                 container_of(chip, struct f7188x_gpio_bank, chip);
 219         struct f7188x_sio *sio = bank->data->sio;
 220         u8 dir;
 221
 222         err = superio_enter(sio->addr);
 223         if (err)
 224                 return err;
 225         superio_select(sio->addr, SIO_LD_GPIO);
 226
 227         dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
 228
 229         superio_exit(sio->addr);
 230
 231         return !(dir & 1 << offset);
 232 }
 233
 234 static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
 235 {
 236         int err;
 237         struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
 238         struct f7188x_sio *sio = bank->data->sio;
 239         u8 dir;
 240
 241         err = superio_enter(sio->addr);
 242         if (err)
 243                 return err;
 244         superio_select(sio->addr, SIO_LD_GPIO);
 245
 246         dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
 247         dir &= ~BIT(offset);
 248         superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
 249
 250         superio_exit(sio->addr);
 251
 252         return 0;
 253 }
 254
 255 static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset)
 256 {
 257         int err;
 258         struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
 259         struct f7188x_sio *sio = bank->data->sio;
 260         u8 dir, data;
 261
 262         err = superio_enter(sio->addr);
 263         if (err)
 264                 return err;
 265         superio_select(sio->addr, SIO_LD_GPIO);
 266
 267         dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
 268         dir = !!(dir & BIT(offset));
 269         if (dir)
 270                 data = superio_inb(sio->addr, gpio_data_out(bank->regbase));
 271         else
 272                 data = superio_inb(sio->addr, gpio_data_in(bank->regbase));
 273
 274         superio_exit(sio->addr);
 275
 276         return !!(data & BIT(offset));
 277 }
 278
 279 static int f7188x_gpio_direction_out(struct gpio_chip *chip,
 280                                      unsigned offset, int value)
 281 {
 282         int err;
 283         struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
 284         struct f7188x_sio *sio = bank->data->sio;
 285         u8 dir, data_out;
 286
 287         err = superio_enter(sio->addr);
 288         if (err)
 289                 return err;
 290         superio_select(sio->addr, SIO_LD_GPIO);
 291
 292         data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
 293         if (value)
 294                 data_out |= BIT(offset);
 295         else
 296                 data_out &= ~BIT(offset);
 297         superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
 298
 299         dir = superio_inb(sio->addr, gpio_dir(bank->regbase));
 300         dir |= BIT(offset);
 301         superio_outb(sio->addr, gpio_dir(bank->regbase), dir);
 302
 303         superio_exit(sio->addr);
 304
 305         return 0;
 306 }
 307
 308 static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 309 {
 310         int err;
 311         struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
 312         struct f7188x_sio *sio = bank->data->sio;
 313         u8 data_out;
 314
 315         err = superio_enter(sio->addr);
 316         if (err)
 317                 return;
 318         superio_select(sio->addr, SIO_LD_GPIO);
 319
 320         data_out = superio_inb(sio->addr, gpio_data_out(bank->regbase));
 321         if (value)
 322                 data_out |= BIT(offset);
 323         else
 324                 data_out &= ~BIT(offset);
 325         superio_outb(sio->addr, gpio_data_out(bank->regbase), data_out);
 326
 327         superio_exit(sio->addr);
 328 }
 329
 330 static int f7188x_gpio_set_single_ended(struct gpio_chip *chip,
 331                                         unsigned offset,
 332                                         enum single_ended_mode mode)
 333 {
 334         int err;
 335         struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
 336         struct f7188x_sio *sio = bank->data->sio;
 337         u8 data;
 338
 339         if (mode != LINE_MODE_OPEN_DRAIN &&
 340             mode != LINE_MODE_PUSH_PULL)
 341                 return -ENOTSUPP;
 342
 343         err = superio_enter(sio->addr);
 344         if (err)
 345                 return err;
 346         superio_select(sio->addr, SIO_LD_GPIO);
 347
 348         data = superio_inb(sio->addr, gpio_out_mode(bank->regbase));
 349         if (mode == LINE_MODE_OPEN_DRAIN)
 350                 data &= ~BIT(offset);
 351         else
 352                 data |= BIT(offset);
 353         superio_outb(sio->addr, gpio_out_mode(bank->regbase), data);
 354
 355         superio_exit(sio->addr);
 356         return 0;
 357 }
 358
 359 /*
 360  * Platform device and driver.
 361  */
 362
 363 static int f7188x_gpio_probe(struct platform_device *pdev)
 364 {
 365         int err;
 366         int i;
 367         struct f7188x_sio *sio = dev_get_platdata(&pdev->dev);
 368         struct f7188x_gpio_data *data;
 369
 370         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 371         if (!data)
 372                 return -ENOMEM;
 373
 374         switch (sio->type) {
 375         case f71869:
 376                 data->nr_bank = ARRAY_SIZE(f71869_gpio_bank);
 377                 data->bank = f71869_gpio_bank;
 378                 break;
 379         case f71869a:
 380                 data->nr_bank = ARRAY_SIZE(f71869a_gpio_bank);
 381                 data->bank = f71869a_gpio_bank;
 382                 break;
 383         case f71882fg:
 384                 data->nr_bank = ARRAY_SIZE(f71882_gpio_bank);
 385                 data->bank = f71882_gpio_bank;
 386                 break;
 387         case f71889f:
 388                 data->nr_bank = ARRAY_SIZE(f71889_gpio_bank);
 389                 data->bank = f71889_gpio_bank;
 390                 break;
 391         case f81866:
 392                 data->nr_bank = ARRAY_SIZE(f81866_gpio_bank);
 393                 data->bank = f81866_gpio_bank;
 394                 break;
 395         default:
 396                 return -ENODEV;
 397         }
 398         data->sio = sio;
 399
 400         platform_set_drvdata(pdev, data);
 401
 402         /* For each GPIO bank, register a GPIO chip. */
 403         for (i = 0; i < data->nr_bank; i++) {
 404                 struct f7188x_gpio_bank *bank = &data->bank[i];
 405
 406                 bank->chip.parent = &pdev->dev;
 407                 bank->data = data;
 408
 409                 err = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);
 410                 if (err) {
 411                         dev_err(&pdev->dev,
 412                                 "Failed to register gpiochip %d: %d\n",
 413                                 i, err);
 414                         return err;
 415                 }
 416         }
 417
 418         return 0;
 419 }
 420
 421 static int __init f7188x_find(int addr, struct f7188x_sio *sio)
 422 {
 423         int err;
 424         u16 devid;
 425
 426         err = superio_enter(addr);
 427         if (err)
 428                 return err;
 429
 430         err = -ENODEV;
 431         devid = superio_inw(addr, SIO_MANID);
 432         if (devid != SIO_FINTEK_ID) {
 433                 pr_debug(DRVNAME ": Not a Fintek device at 0x%08x\n", addr);
 434                 goto err;
 435         }
 436
 437         devid = superio_inw(addr, SIO_DEVID);
 438         switch (devid) {
 439         case SIO_F71869_ID:
 440                 sio->type = f71869;
 441                 break;
 442         case SIO_F71869A_ID:
 443                 sio->type = f71869a;
 444                 break;
 445         case SIO_F71882_ID:
 446                 sio->type = f71882fg;
 447                 break;
 448         case SIO_F71889_ID:
 449                 sio->type = f71889f;
 450                 break;
 451         case SIO_F81866_ID:
 452                 sio->type = f81866;
 453                 break;
 454         default:
 455                 pr_info(DRVNAME ": Unsupported Fintek device 0x%04x\n", devid);
 456                 goto err;
 457         }
 458         sio->addr = addr;
 459         err = 0;
 460
 461         pr_info(DRVNAME ": Found %s at %#x, revision %d\n",
 462                 f7188x_names[sio->type],
 463                 (unsigned int) addr,
 464                 (int) superio_inb(addr, SIO_DEVREV));
 465
 466 err:
 467         superio_exit(addr);
 468         return err;
 469 }
 470
 471 static struct platform_device *f7188x_gpio_pdev;
 472
 473 static int __init
 474 f7188x_gpio_device_add(const struct f7188x_sio *sio)
 475 {
 476         int err;
 477
 478         f7188x_gpio_pdev = platform_device_alloc(DRVNAME, -1);
 479         if (!f7188x_gpio_pdev)
 480                 return -ENOMEM;
 481
 482         err = platform_device_add_data(f7188x_gpio_pdev,
 483                                        sio, sizeof(*sio));
 484         if (err) {
 485                 pr_err(DRVNAME "Platform data allocation failed\n");
 486                 goto err;
 487         }
 488
 489         err = platform_device_add(f7188x_gpio_pdev);
 490         if (err) {
 491                 pr_err(DRVNAME "Device addition failed\n");
 492                 goto err;
 493         }
 494
 495         return 0;
 496
 497 err:
 498         platform_device_put(f7188x_gpio_pdev);
 499
 500         return err;
 501 }
 502
 503 /*
 504  * Try to match a supported Fintek device by reading the (hard-wired)
 505  * configuration I/O ports. If available, then register both the platform
 506  * device and driver to support the GPIOs.
 507  */
 508
 509 static struct platform_driver f7188x_gpio_driver = {
 510         .driver = {
 511                 .name   = DRVNAME,
 512         },
 513         .probe          = f7188x_gpio_probe,
 514 };
 515
 516 static int __init f7188x_gpio_init(void)
 517 {
 518         int err;
 519         struct f7188x_sio sio;
 520
 521         if (f7188x_find(0x2e, &sio) &&
 522             f7188x_find(0x4e, &sio))
 523                 return -ENODEV;
 524
 525         err = platform_driver_register(&f7188x_gpio_driver);
 526         if (!err) {
 527                 err = f7188x_gpio_device_add(&sio);
 528                 if (err)
 529                         platform_driver_unregister(&f7188x_gpio_driver);
 530         }
 531
 532         return err;
 533 }
 534 subsys_initcall(f7188x_gpio_init);
 535
 536 static void __exit f7188x_gpio_exit(void)
 537 {
 538         platform_device_unregister(f7188x_gpio_pdev);
 539         platform_driver_unregister(&f7188x_gpio_driver);
 540 }
 541 module_exit(f7188x_gpio_exit);
 542
 543 MODULE_DESCRIPTION("GPIO driver for Super-I/O chips F71869, F71869A, F71882FG, F71889F and F81866");
 544 MODULE_AUTHOR("Simon Guinot <simon.guinot@sequanux.org>");
 545 MODULE_LICENSE("GPL");