2 * GPIO driver for Marvell SoCs
4 * Copyright (C) 2012 Marvell
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * Andrew Lunn <andrew@lunn.ch>
8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
14 * This driver is a fairly straightforward GPIO driver for the
15 * complete family of Marvell EBU SoC platforms (Orion, Dove,
16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
17 * driver is the different register layout that exists between the
18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * platforms (MV78200 from the Discovery family and the Armada
20 * XP). Therefore, this driver handles three variants of the GPIO
22 * - the basic variant, called "orion-gpio", with the simplest
23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
24 * non-SMP Discovery systems
25 * - the mv78200 variant for MV78200 Discovery systems. This variant
26 * turns the edge mask and level mask registers into CPU0 edge
27 * mask/level mask registers, and adds CPU1 edge mask/level mask
29 * - the armadaxp variant for Armada XP systems. This variant keeps
30 * the normal cause/edge mask/level mask registers when the global
31 * interrupts are used, but adds per-CPU cause/edge mask/level mask
32 * registers n a separate memory area for the per-CPU GPIO
36 #include <linux/module.h>
37 #include <linux/gpio.h>
38 #include <linux/irq.h>
39 #include <linux/slab.h>
40 #include <linux/irqdomain.h>
42 #include <linux/of_irq.h>
43 #include <linux/of_device.h>
44 #include <linux/platform_device.h>
45 #include <linux/pinctrl/consumer.h>
48 * GPIO unit register offsets.
50 #define GPIO_OUT_OFF 0x0000
51 #define GPIO_IO_CONF_OFF 0x0004
52 #define GPIO_BLINK_EN_OFF 0x0008
53 #define GPIO_IN_POL_OFF 0x000c
54 #define GPIO_DATA_IN_OFF 0x0010
55 #define GPIO_EDGE_CAUSE_OFF 0x0014
56 #define GPIO_EDGE_MASK_OFF 0x0018
57 #define GPIO_LEVEL_MASK_OFF 0x001c
59 /* The MV78200 has per-CPU registers for edge mask and level mask */
60 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
61 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
63 /* The Armada XP has per-CPU registers for interrupt cause, interrupt
64 * mask and interrupt level mask. Those are relative to the
66 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
67 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
68 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
70 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
71 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
72 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
74 #define MVEBU_MAX_GPIO_PER_BANK 32
76 struct mvebu_gpio_chip
{
77 struct gpio_chip chip
;
79 void __iomem
*membase
;
80 void __iomem
*percpu_membase
;
82 struct irq_domain
*domain
;
87 * Functions returning addresses of individual registers for a given
90 static inline void __iomem
*mvebu_gpioreg_out(struct mvebu_gpio_chip
*mvchip
)
92 return mvchip
->membase
+ GPIO_OUT_OFF
;
95 static inline void __iomem
*mvebu_gpioreg_io_conf(struct mvebu_gpio_chip
*mvchip
)
97 return mvchip
->membase
+ GPIO_IO_CONF_OFF
;
100 static inline void __iomem
*mvebu_gpioreg_in_pol(struct mvebu_gpio_chip
*mvchip
)
102 return mvchip
->membase
+ GPIO_IN_POL_OFF
;
105 static inline void __iomem
*mvebu_gpioreg_data_in(struct mvebu_gpio_chip
*mvchip
)
107 return mvchip
->membase
+ GPIO_DATA_IN_OFF
;
110 static inline void __iomem
*mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip
*mvchip
)
114 switch(mvchip
->soc_variant
) {
115 case MVEBU_GPIO_SOC_VARIANT_ORION
:
116 case MVEBU_GPIO_SOC_VARIANT_MV78200
:
117 return mvchip
->membase
+ GPIO_EDGE_CAUSE_OFF
;
118 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP
:
119 cpu
= smp_processor_id();
120 return mvchip
->percpu_membase
+ GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu
);
126 static inline void __iomem
*mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip
*mvchip
)
130 switch(mvchip
->soc_variant
) {
131 case MVEBU_GPIO_SOC_VARIANT_ORION
:
132 return mvchip
->membase
+ GPIO_EDGE_MASK_OFF
;
133 case MVEBU_GPIO_SOC_VARIANT_MV78200
:
134 cpu
= smp_processor_id();
135 return mvchip
->membase
+ GPIO_EDGE_MASK_MV78200_OFF(cpu
);
136 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP
:
137 cpu
= smp_processor_id();
138 return mvchip
->percpu_membase
+ GPIO_EDGE_MASK_ARMADAXP_OFF(cpu
);
144 static void __iomem
*mvebu_gpioreg_level_mask(struct mvebu_gpio_chip
*mvchip
)
148 switch(mvchip
->soc_variant
) {
149 case MVEBU_GPIO_SOC_VARIANT_ORION
:
150 return mvchip
->membase
+ GPIO_LEVEL_MASK_OFF
;
151 case MVEBU_GPIO_SOC_VARIANT_MV78200
:
152 cpu
= smp_processor_id();
153 return mvchip
->membase
+ GPIO_LEVEL_MASK_MV78200_OFF(cpu
);
154 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP
:
155 cpu
= smp_processor_id();
156 return mvchip
->percpu_membase
+ GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu
);
163 * Functions implementing the gpio_chip methods
166 int mvebu_gpio_request(struct gpio_chip
*chip
, unsigned pin
)
168 return pinctrl_request_gpio(chip
->base
+ pin
);
171 void mvebu_gpio_free(struct gpio_chip
*chip
, unsigned pin
)
173 pinctrl_free_gpio(chip
->base
+ pin
);
176 static void mvebu_gpio_set(struct gpio_chip
*chip
, unsigned pin
, int value
)
178 struct mvebu_gpio_chip
*mvchip
=
179 container_of(chip
, struct mvebu_gpio_chip
, chip
);
183 spin_lock_irqsave(&mvchip
->lock
, flags
);
184 u
= readl_relaxed(mvebu_gpioreg_out(mvchip
));
189 writel_relaxed(u
, mvebu_gpioreg_out(mvchip
));
190 spin_unlock_irqrestore(&mvchip
->lock
, flags
);
193 static int mvebu_gpio_get(struct gpio_chip
*chip
, unsigned pin
)
195 struct mvebu_gpio_chip
*mvchip
=
196 container_of(chip
, struct mvebu_gpio_chip
, chip
);
199 if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip
)) & (1 << pin
)) {
200 u
= readl_relaxed(mvebu_gpioreg_data_in(mvchip
)) ^
201 readl_relaxed(mvebu_gpioreg_in_pol(mvchip
));
203 u
= readl_relaxed(mvebu_gpioreg_out(mvchip
));
206 return (u
>> pin
) & 1;
209 static int mvebu_gpio_direction_input(struct gpio_chip
*chip
, unsigned pin
)
211 struct mvebu_gpio_chip
*mvchip
=
212 container_of(chip
, struct mvebu_gpio_chip
, chip
);
217 /* Check with the pinctrl driver whether this pin is usable as
219 ret
= pinctrl_gpio_direction_input(chip
->base
+ pin
);
223 spin_lock_irqsave(&mvchip
->lock
, flags
);
224 u
= readl_relaxed(mvebu_gpioreg_io_conf(mvchip
));
226 writel_relaxed(u
, mvebu_gpioreg_io_conf(mvchip
));
227 spin_unlock_irqrestore(&mvchip
->lock
, flags
);
232 static int mvebu_gpio_direction_output(struct gpio_chip
*chip
, unsigned pin
,
235 struct mvebu_gpio_chip
*mvchip
=
236 container_of(chip
, struct mvebu_gpio_chip
, chip
);
241 /* Check with the pinctrl driver whether this pin is usable as
243 ret
= pinctrl_gpio_direction_output(chip
->base
+ pin
);
247 spin_lock_irqsave(&mvchip
->lock
, flags
);
248 u
= readl_relaxed(mvebu_gpioreg_io_conf(mvchip
));
250 writel_relaxed(u
, mvebu_gpioreg_io_conf(mvchip
));
251 spin_unlock_irqrestore(&mvchip
->lock
, flags
);
256 static int mvebu_gpio_to_irq(struct gpio_chip
*chip
, unsigned pin
)
258 struct mvebu_gpio_chip
*mvchip
=
259 container_of(chip
, struct mvebu_gpio_chip
, chip
);
260 return irq_create_mapping(mvchip
->domain
, pin
);
264 * Functions implementing the irq_chip methods
266 static void mvebu_gpio_irq_ack(struct irq_data
*d
)
268 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
269 struct mvebu_gpio_chip
*mvchip
= gc
->private;
270 u32 mask
= ~(1 << (d
->irq
- gc
->irq_base
));
273 writel_relaxed(mask
, mvebu_gpioreg_edge_cause(mvchip
));
277 static void mvebu_gpio_edge_irq_mask(struct irq_data
*d
)
279 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
280 struct mvebu_gpio_chip
*mvchip
= gc
->private;
281 u32 mask
= 1 << (d
->irq
- gc
->irq_base
);
284 gc
->mask_cache
&= ~mask
;
285 writel_relaxed(gc
->mask_cache
, mvebu_gpioreg_edge_mask(mvchip
));
289 static void mvebu_gpio_edge_irq_unmask(struct irq_data
*d
)
291 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
292 struct mvebu_gpio_chip
*mvchip
= gc
->private;
293 u32 mask
= 1 << (d
->irq
- gc
->irq_base
);
296 gc
->mask_cache
|= mask
;
297 writel_relaxed(gc
->mask_cache
, mvebu_gpioreg_edge_mask(mvchip
));
301 static void mvebu_gpio_level_irq_mask(struct irq_data
*d
)
303 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
304 struct mvebu_gpio_chip
*mvchip
= gc
->private;
305 u32 mask
= 1 << (d
->irq
- gc
->irq_base
);
308 gc
->mask_cache
&= ~mask
;
309 writel_relaxed(gc
->mask_cache
, mvebu_gpioreg_level_mask(mvchip
));
313 static void mvebu_gpio_level_irq_unmask(struct irq_data
*d
)
315 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
316 struct mvebu_gpio_chip
*mvchip
= gc
->private;
317 u32 mask
= 1 << (d
->irq
- gc
->irq_base
);
320 gc
->mask_cache
|= mask
;
321 writel_relaxed(gc
->mask_cache
, mvebu_gpioreg_level_mask(mvchip
));
325 /*****************************************************************************
328 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
329 * value of the line or the opposite value.
331 * Level IRQ handlers: DATA_IN is used directly as cause register.
332 * Interrupt are masked by LEVEL_MASK registers.
333 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
334 * Interrupt are masked by EDGE_MASK registers.
335 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
336 * the polarity to catch the next line transaction.
337 * This is a race condition that might not perfectly
338 * work on some use cases.
340 * Every eight GPIO lines are grouped (OR'ed) before going up to main
344 * data-in /--------| |-----| |----\
345 * -----| |----- ---- to main cause reg
346 * X \----------------| |----/
347 * polarity LEVEL mask
349 ****************************************************************************/
351 static int mvebu_gpio_irq_set_type(struct irq_data
*d
, unsigned int type
)
353 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
354 struct irq_chip_type
*ct
= irq_data_get_chip_type(d
);
355 struct mvebu_gpio_chip
*mvchip
= gc
->private;
361 u
= readl_relaxed(mvebu_gpioreg_io_conf(mvchip
)) & (1 << pin
);
366 type
&= IRQ_TYPE_SENSE_MASK
;
367 if (type
== IRQ_TYPE_NONE
)
370 /* Check if we need to change chip and handler */
371 if (!(ct
->type
& type
))
372 if (irq_setup_alt_chip(d
, type
))
376 * Configure interrupt polarity.
379 case IRQ_TYPE_EDGE_RISING
:
380 case IRQ_TYPE_LEVEL_HIGH
:
381 u
= readl_relaxed(mvebu_gpioreg_in_pol(mvchip
));
383 writel_relaxed(u
, mvebu_gpioreg_in_pol(mvchip
));
384 case IRQ_TYPE_EDGE_FALLING
:
385 case IRQ_TYPE_LEVEL_LOW
:
386 u
= readl_relaxed(mvebu_gpioreg_in_pol(mvchip
));
388 writel_relaxed(u
, mvebu_gpioreg_in_pol(mvchip
));
389 case IRQ_TYPE_EDGE_BOTH
: {
392 v
= readl_relaxed(mvebu_gpioreg_in_pol(mvchip
)) ^
393 readl_relaxed(mvebu_gpioreg_data_in(mvchip
));
396 * set initial polarity based on current input level
398 u
= readl_relaxed(mvebu_gpioreg_in_pol(mvchip
));
400 u
|= 1 << pin
; /* falling */
402 u
&= ~(1 << pin
); /* rising */
403 writel_relaxed(u
, mvebu_gpioreg_in_pol(mvchip
));
409 static void mvebu_gpio_irq_handler(unsigned int irq
, struct irq_desc
*desc
)
411 struct mvebu_gpio_chip
*mvchip
= irq_get_handler_data(irq
);
418 cause
= readl_relaxed(mvebu_gpioreg_data_in(mvchip
)) &
419 readl_relaxed(mvebu_gpioreg_level_mask(mvchip
));
420 cause
|= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip
)) &
421 readl_relaxed(mvebu_gpioreg_edge_mask(mvchip
));
423 for (i
= 0; i
< mvchip
->chip
.ngpio
; i
++) {
426 irq
= mvchip
->irqbase
+ i
;
428 if (!(cause
& (1 << i
)))
431 type
= irqd_get_trigger_type(irq_get_irq_data(irq
));
432 if ((type
& IRQ_TYPE_SENSE_MASK
) == IRQ_TYPE_EDGE_BOTH
) {
433 /* Swap polarity (race with GPIO line) */
436 polarity
= readl_relaxed(mvebu_gpioreg_in_pol(mvchip
));
438 writel_relaxed(polarity
, mvebu_gpioreg_in_pol(mvchip
));
440 generic_handle_irq(irq
);
444 static struct platform_device_id mvebu_gpio_ids
[] = {
446 .name
= "orion-gpio",
448 .name
= "mv78200-gpio",
450 .name
= "armadaxp-gpio",
455 MODULE_DEVICE_TABLE(platform
, mvebu_gpio_ids
);
457 static struct of_device_id mvebu_gpio_of_match
[] __devinitdata
= {
459 .compatible
= "marvell,orion-gpio",
460 .data
= (void*) MVEBU_GPIO_SOC_VARIANT_ORION
,
463 .compatible
= "marvell,mv78200-gpio",
464 .data
= (void*) MVEBU_GPIO_SOC_VARIANT_MV78200
,
467 .compatible
= "marvell,armadaxp-gpio",
468 .data
= (void*) MVEBU_GPIO_SOC_VARIANT_ARMADAXP
,
474 MODULE_DEVICE_TABLE(of
, mvebu_gpio_of_match
);
476 static int __devinit
mvebu_gpio_probe(struct platform_device
*pdev
)
478 struct mvebu_gpio_chip
*mvchip
;
479 const struct of_device_id
*match
;
480 struct device_node
*np
= pdev
->dev
.of_node
;
481 struct resource
*res
;
482 struct irq_chip_generic
*gc
;
483 struct irq_chip_type
*ct
;
488 match
= of_match_device(mvebu_gpio_of_match
, &pdev
->dev
);
490 soc_variant
= (int) match
->data
;
492 soc_variant
= MVEBU_GPIO_SOC_VARIANT_ORION
;
494 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
496 dev_err(&pdev
->dev
, "Cannot get memory resource\n");
500 mvchip
= devm_kzalloc(&pdev
->dev
, sizeof(struct mvebu_gpio_chip
), GFP_KERNEL
);
502 dev_err(&pdev
->dev
, "Cannot allocate memory\n");
506 if (of_property_read_u32(pdev
->dev
.of_node
, "ngpios", &ngpios
)) {
507 dev_err(&pdev
->dev
, "Missing ngpios OF property\n");
511 id
= of_alias_get_id(pdev
->dev
.of_node
, "gpio");
513 dev_err(&pdev
->dev
, "Couldn't get OF id\n");
517 mvchip
->soc_variant
= soc_variant
;
518 mvchip
->chip
.label
= dev_name(&pdev
->dev
);
519 mvchip
->chip
.dev
= &pdev
->dev
;
520 mvchip
->chip
.request
= mvebu_gpio_request
;
521 mvchip
->chip
.direction_input
= mvebu_gpio_direction_input
;
522 mvchip
->chip
.get
= mvebu_gpio_get
;
523 mvchip
->chip
.direction_output
= mvebu_gpio_direction_output
;
524 mvchip
->chip
.set
= mvebu_gpio_set
;
525 mvchip
->chip
.to_irq
= mvebu_gpio_to_irq
;
526 mvchip
->chip
.base
= id
* MVEBU_MAX_GPIO_PER_BANK
;
527 mvchip
->chip
.ngpio
= ngpios
;
528 mvchip
->chip
.can_sleep
= 0;
530 mvchip
->chip
.of_node
= np
;
533 spin_lock_init(&mvchip
->lock
);
534 mvchip
->membase
= devm_request_and_ioremap(&pdev
->dev
, res
);
535 if (! mvchip
->membase
) {
536 dev_err(&pdev
->dev
, "Cannot ioremap\n");
537 kfree(mvchip
->chip
.label
);
541 /* The Armada XP has a second range of registers for the
542 * per-CPU registers */
543 if (soc_variant
== MVEBU_GPIO_SOC_VARIANT_ARMADAXP
) {
544 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
546 dev_err(&pdev
->dev
, "Cannot get memory resource\n");
547 kfree(mvchip
->chip
.label
);
551 mvchip
->percpu_membase
= devm_request_and_ioremap(&pdev
->dev
, res
);
552 if (! mvchip
->percpu_membase
) {
553 dev_err(&pdev
->dev
, "Cannot ioremap\n");
554 kfree(mvchip
->chip
.label
);
560 * Mask and clear GPIO interrupts.
562 switch(soc_variant
) {
563 case MVEBU_GPIO_SOC_VARIANT_ORION
:
564 writel_relaxed(0, mvchip
->membase
+ GPIO_EDGE_CAUSE_OFF
);
565 writel_relaxed(0, mvchip
->membase
+ GPIO_EDGE_MASK_OFF
);
566 writel_relaxed(0, mvchip
->membase
+ GPIO_LEVEL_MASK_OFF
);
568 case MVEBU_GPIO_SOC_VARIANT_MV78200
:
569 writel_relaxed(0, mvchip
->membase
+ GPIO_EDGE_CAUSE_OFF
);
570 for (cpu
= 0; cpu
< 2; cpu
++) {
571 writel_relaxed(0, mvchip
->membase
+
572 GPIO_EDGE_MASK_MV78200_OFF(cpu
));
573 writel_relaxed(0, mvchip
->membase
+
574 GPIO_LEVEL_MASK_MV78200_OFF(cpu
));
577 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP
:
578 writel_relaxed(0, mvchip
->membase
+ GPIO_EDGE_CAUSE_OFF
);
579 writel_relaxed(0, mvchip
->membase
+ GPIO_EDGE_MASK_OFF
);
580 writel_relaxed(0, mvchip
->membase
+ GPIO_LEVEL_MASK_OFF
);
581 for (cpu
= 0; cpu
< 4; cpu
++) {
582 writel_relaxed(0, mvchip
->percpu_membase
+
583 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu
));
584 writel_relaxed(0, mvchip
->percpu_membase
+
585 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu
));
586 writel_relaxed(0, mvchip
->percpu_membase
+
587 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu
));
594 gpiochip_add(&mvchip
->chip
);
596 /* Some gpio controllers do not provide irq support */
597 if (!of_irq_count(np
))
600 /* Setup the interrupt handlers. Each chip can have up to 4
601 * interrupt handlers, with each handler dealing with 8 GPIO
603 for (i
= 0; i
< 4; i
++) {
605 irq
= platform_get_irq(pdev
, i
);
608 irq_set_handler_data(irq
, mvchip
);
609 irq_set_chained_handler(irq
, mvebu_gpio_irq_handler
);
612 mvchip
->irqbase
= irq_alloc_descs(-1, 0, ngpios
, -1);
613 if (mvchip
->irqbase
< 0) {
614 dev_err(&pdev
->dev
, "no irqs\n");
615 kfree(mvchip
->chip
.label
);
619 gc
= irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip
->irqbase
,
620 mvchip
->membase
, handle_level_irq
);
622 dev_err(&pdev
->dev
, "Cannot allocate generic irq_chip\n");
623 kfree(mvchip
->chip
.label
);
627 gc
->private = mvchip
;
628 ct
= &gc
->chip_types
[0];
629 ct
->type
= IRQ_TYPE_LEVEL_HIGH
| IRQ_TYPE_LEVEL_LOW
;
630 ct
->chip
.irq_mask
= mvebu_gpio_level_irq_mask
;
631 ct
->chip
.irq_unmask
= mvebu_gpio_level_irq_unmask
;
632 ct
->chip
.irq_set_type
= mvebu_gpio_irq_set_type
;
633 ct
->chip
.name
= mvchip
->chip
.label
;
635 ct
= &gc
->chip_types
[1];
636 ct
->type
= IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
;
637 ct
->chip
.irq_ack
= mvebu_gpio_irq_ack
;
638 ct
->chip
.irq_mask
= mvebu_gpio_edge_irq_mask
;
639 ct
->chip
.irq_unmask
= mvebu_gpio_edge_irq_unmask
;
640 ct
->chip
.irq_set_type
= mvebu_gpio_irq_set_type
;
641 ct
->handler
= handle_edge_irq
;
642 ct
->chip
.name
= mvchip
->chip
.label
;
644 irq_setup_generic_chip(gc
, IRQ_MSK(ngpios
), IRQ_GC_INIT_MASK_CACHE
,
645 IRQ_NOREQUEST
, IRQ_LEVEL
| IRQ_NOPROBE
);
647 /* Setup irq domain on top of the generic chip. */
648 mvchip
->domain
= irq_domain_add_legacy(np
, mvchip
->chip
.ngpio
,
650 &irq_domain_simple_ops
,
652 if (!mvchip
->domain
) {
653 dev_err(&pdev
->dev
, "couldn't allocate irq domain %s (DT).\n",
655 irq_remove_generic_chip(gc
, IRQ_MSK(ngpios
), IRQ_NOREQUEST
,
656 IRQ_LEVEL
| IRQ_NOPROBE
);
658 kfree(mvchip
->chip
.label
);
665 static struct platform_driver mvebu_gpio_driver
= {
667 .name
= "mvebu-gpio",
668 .owner
= THIS_MODULE
,
669 .of_match_table
= mvebu_gpio_of_match
,
671 .probe
= mvebu_gpio_probe
,
672 .id_table
= mvebu_gpio_ids
,
675 static int __init
mvebu_gpio_init(void)
677 return platform_driver_register(&mvebu_gpio_driver
);
679 postcore_initcall(mvebu_gpio_init
);