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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[deliverable/linux.git] / drivers / gpio / gpio-mvebu.c
1 /*
2 * GPIO driver for Marvell SoCs
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 * Andrew Lunn <andrew@lunn.ch>
8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 *
14 * This driver is a fairly straightforward GPIO driver for the
15 * complete family of Marvell EBU SoC platforms (Orion, Dove,
16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
17 * driver is the different register layout that exists between the
18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
19 * platforms (MV78200 from the Discovery family and the Armada
20 * XP). Therefore, this driver handles three variants of the GPIO
21 * block:
22 * - the basic variant, called "orion-gpio", with the simplest
23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
24 * non-SMP Discovery systems
25 * - the mv78200 variant for MV78200 Discovery systems. This variant
26 * turns the edge mask and level mask registers into CPU0 edge
27 * mask/level mask registers, and adds CPU1 edge mask/level mask
28 * registers.
29 * - the armadaxp variant for Armada XP systems. This variant keeps
30 * the normal cause/edge mask/level mask registers when the global
31 * interrupts are used, but adds per-CPU cause/edge mask/level mask
32 * registers n a separate memory area for the per-CPU GPIO
33 * interrupts.
34 */
35
36 #include <linux/err.h>
37 #include <linux/module.h>
38 #include <linux/gpio.h>
39 #include <linux/irq.h>
40 #include <linux/slab.h>
41 #include <linux/irqdomain.h>
42 #include <linux/io.h>
43 #include <linux/of_irq.h>
44 #include <linux/of_device.h>
45 #include <linux/clk.h>
46 #include <linux/pinctrl/consumer.h>
47 #include <linux/irqchip/chained_irq.h>
48
49 /*
50 * GPIO unit register offsets.
51 */
52 #define GPIO_OUT_OFF 0x0000
53 #define GPIO_IO_CONF_OFF 0x0004
54 #define GPIO_BLINK_EN_OFF 0x0008
55 #define GPIO_IN_POL_OFF 0x000c
56 #define GPIO_DATA_IN_OFF 0x0010
57 #define GPIO_EDGE_CAUSE_OFF 0x0014
58 #define GPIO_EDGE_MASK_OFF 0x0018
59 #define GPIO_LEVEL_MASK_OFF 0x001c
60
61 /* The MV78200 has per-CPU registers for edge mask and level mask */
62 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
63 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
64
65 /* The Armada XP has per-CPU registers for interrupt cause, interrupt
66 * mask and interrupt level mask. Those are relative to the
67 * percpu_membase. */
68 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
69 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
70 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
71
72 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1
73 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2
74 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
75
76 #define MVEBU_MAX_GPIO_PER_BANK 32
77
78 struct mvebu_gpio_chip {
79 struct gpio_chip chip;
80 spinlock_t lock;
81 void __iomem *membase;
82 void __iomem *percpu_membase;
83 int irqbase;
84 struct irq_domain *domain;
85 int soc_variant;
86
87 /* Used to preserve GPIO registers across suspend/resume */
88 u32 out_reg;
89 u32 io_conf_reg;
90 u32 blink_en_reg;
91 u32 in_pol_reg;
92 u32 edge_mask_regs[4];
93 u32 level_mask_regs[4];
94 };
95
96 /*
97 * Functions returning addresses of individual registers for a given
98 * GPIO controller.
99 */
100 static inline void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip)
101 {
102 return mvchip->membase + GPIO_OUT_OFF;
103 }
104
105 static inline void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip)
106 {
107 return mvchip->membase + GPIO_BLINK_EN_OFF;
108 }
109
110 static inline void __iomem *
111 mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip)
112 {
113 return mvchip->membase + GPIO_IO_CONF_OFF;
114 }
115
116 static inline void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip)
117 {
118 return mvchip->membase + GPIO_IN_POL_OFF;
119 }
120
121 static inline void __iomem *
122 mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip)
123 {
124 return mvchip->membase + GPIO_DATA_IN_OFF;
125 }
126
127 static inline void __iomem *
128 mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip)
129 {
130 int cpu;
131
132 switch (mvchip->soc_variant) {
133 case MVEBU_GPIO_SOC_VARIANT_ORION:
134 case MVEBU_GPIO_SOC_VARIANT_MV78200:
135 return mvchip->membase + GPIO_EDGE_CAUSE_OFF;
136 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
137 cpu = smp_processor_id();
138 return mvchip->percpu_membase +
139 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
140 default:
141 BUG();
142 }
143 }
144
145 static inline void __iomem *
146 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip)
147 {
148 int cpu;
149
150 switch (mvchip->soc_variant) {
151 case MVEBU_GPIO_SOC_VARIANT_ORION:
152 return mvchip->membase + GPIO_EDGE_MASK_OFF;
153 case MVEBU_GPIO_SOC_VARIANT_MV78200:
154 cpu = smp_processor_id();
155 return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu);
156 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
157 cpu = smp_processor_id();
158 return mvchip->percpu_membase +
159 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
160 default:
161 BUG();
162 }
163 }
164
165 static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip)
166 {
167 int cpu;
168
169 switch (mvchip->soc_variant) {
170 case MVEBU_GPIO_SOC_VARIANT_ORION:
171 return mvchip->membase + GPIO_LEVEL_MASK_OFF;
172 case MVEBU_GPIO_SOC_VARIANT_MV78200:
173 cpu = smp_processor_id();
174 return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu);
175 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
176 cpu = smp_processor_id();
177 return mvchip->percpu_membase +
178 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
179 default:
180 BUG();
181 }
182 }
183
184 /*
185 * Functions implementing the gpio_chip methods
186 */
187
188 static int mvebu_gpio_request(struct gpio_chip *chip, unsigned pin)
189 {
190 return pinctrl_request_gpio(chip->base + pin);
191 }
192
193 static void mvebu_gpio_free(struct gpio_chip *chip, unsigned pin)
194 {
195 pinctrl_free_gpio(chip->base + pin);
196 }
197
198 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
199 {
200 struct mvebu_gpio_chip *mvchip =
201 container_of(chip, struct mvebu_gpio_chip, chip);
202 unsigned long flags;
203 u32 u;
204
205 spin_lock_irqsave(&mvchip->lock, flags);
206 u = readl_relaxed(mvebu_gpioreg_out(mvchip));
207 if (value)
208 u |= 1 << pin;
209 else
210 u &= ~(1 << pin);
211 writel_relaxed(u, mvebu_gpioreg_out(mvchip));
212 spin_unlock_irqrestore(&mvchip->lock, flags);
213 }
214
215 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin)
216 {
217 struct mvebu_gpio_chip *mvchip =
218 container_of(chip, struct mvebu_gpio_chip, chip);
219 u32 u;
220
221 if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) {
222 u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^
223 readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
224 } else {
225 u = readl_relaxed(mvebu_gpioreg_out(mvchip));
226 }
227
228 return (u >> pin) & 1;
229 }
230
231 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value)
232 {
233 struct mvebu_gpio_chip *mvchip =
234 container_of(chip, struct mvebu_gpio_chip, chip);
235 unsigned long flags;
236 u32 u;
237
238 spin_lock_irqsave(&mvchip->lock, flags);
239 u = readl_relaxed(mvebu_gpioreg_blink(mvchip));
240 if (value)
241 u |= 1 << pin;
242 else
243 u &= ~(1 << pin);
244 writel_relaxed(u, mvebu_gpioreg_blink(mvchip));
245 spin_unlock_irqrestore(&mvchip->lock, flags);
246 }
247
248 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
249 {
250 struct mvebu_gpio_chip *mvchip =
251 container_of(chip, struct mvebu_gpio_chip, chip);
252 unsigned long flags;
253 int ret;
254 u32 u;
255
256 /* Check with the pinctrl driver whether this pin is usable as
257 * an input GPIO */
258 ret = pinctrl_gpio_direction_input(chip->base + pin);
259 if (ret)
260 return ret;
261
262 spin_lock_irqsave(&mvchip->lock, flags);
263 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
264 u |= 1 << pin;
265 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
266 spin_unlock_irqrestore(&mvchip->lock, flags);
267
268 return 0;
269 }
270
271 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
272 int value)
273 {
274 struct mvebu_gpio_chip *mvchip =
275 container_of(chip, struct mvebu_gpio_chip, chip);
276 unsigned long flags;
277 int ret;
278 u32 u;
279
280 /* Check with the pinctrl driver whether this pin is usable as
281 * an output GPIO */
282 ret = pinctrl_gpio_direction_output(chip->base + pin);
283 if (ret)
284 return ret;
285
286 mvebu_gpio_blink(chip, pin, 0);
287 mvebu_gpio_set(chip, pin, value);
288
289 spin_lock_irqsave(&mvchip->lock, flags);
290 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
291 u &= ~(1 << pin);
292 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
293 spin_unlock_irqrestore(&mvchip->lock, flags);
294
295 return 0;
296 }
297
298 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
299 {
300 struct mvebu_gpio_chip *mvchip =
301 container_of(chip, struct mvebu_gpio_chip, chip);
302 return irq_create_mapping(mvchip->domain, pin);
303 }
304
305 /*
306 * Functions implementing the irq_chip methods
307 */
308 static void mvebu_gpio_irq_ack(struct irq_data *d)
309 {
310 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
311 struct mvebu_gpio_chip *mvchip = gc->private;
312 u32 mask = ~(1 << (d->irq - gc->irq_base));
313
314 irq_gc_lock(gc);
315 writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip));
316 irq_gc_unlock(gc);
317 }
318
319 static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
320 {
321 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
322 struct mvebu_gpio_chip *mvchip = gc->private;
323 struct irq_chip_type *ct = irq_data_get_chip_type(d);
324 u32 mask = 1 << (d->irq - gc->irq_base);
325
326 irq_gc_lock(gc);
327 ct->mask_cache_priv &= ~mask;
328
329 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip));
330 irq_gc_unlock(gc);
331 }
332
333 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
334 {
335 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
336 struct mvebu_gpio_chip *mvchip = gc->private;
337 struct irq_chip_type *ct = irq_data_get_chip_type(d);
338
339 u32 mask = 1 << (d->irq - gc->irq_base);
340
341 irq_gc_lock(gc);
342 ct->mask_cache_priv |= mask;
343 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip));
344 irq_gc_unlock(gc);
345 }
346
347 static void mvebu_gpio_level_irq_mask(struct irq_data *d)
348 {
349 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
350 struct mvebu_gpio_chip *mvchip = gc->private;
351 struct irq_chip_type *ct = irq_data_get_chip_type(d);
352
353 u32 mask = 1 << (d->irq - gc->irq_base);
354
355 irq_gc_lock(gc);
356 ct->mask_cache_priv &= ~mask;
357 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip));
358 irq_gc_unlock(gc);
359 }
360
361 static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
362 {
363 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
364 struct mvebu_gpio_chip *mvchip = gc->private;
365 struct irq_chip_type *ct = irq_data_get_chip_type(d);
366
367 u32 mask = 1 << (d->irq - gc->irq_base);
368
369 irq_gc_lock(gc);
370 ct->mask_cache_priv |= mask;
371 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip));
372 irq_gc_unlock(gc);
373 }
374
375 /*****************************************************************************
376 * MVEBU GPIO IRQ
377 *
378 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
379 * value of the line or the opposite value.
380 *
381 * Level IRQ handlers: DATA_IN is used directly as cause register.
382 * Interrupt are masked by LEVEL_MASK registers.
383 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
384 * Interrupt are masked by EDGE_MASK registers.
385 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
386 * the polarity to catch the next line transaction.
387 * This is a race condition that might not perfectly
388 * work on some use cases.
389 *
390 * Every eight GPIO lines are grouped (OR'ed) before going up to main
391 * cause register.
392 *
393 * EDGE cause mask
394 * data-in /--------| |-----| |----\
395 * -----| |----- ---- to main cause reg
396 * X \----------------| |----/
397 * polarity LEVEL mask
398 *
399 ****************************************************************************/
400
401 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
402 {
403 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
404 struct irq_chip_type *ct = irq_data_get_chip_type(d);
405 struct mvebu_gpio_chip *mvchip = gc->private;
406 int pin;
407 u32 u;
408
409 pin = d->hwirq;
410
411 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin);
412 if (!u)
413 return -EINVAL;
414
415 type &= IRQ_TYPE_SENSE_MASK;
416 if (type == IRQ_TYPE_NONE)
417 return -EINVAL;
418
419 /* Check if we need to change chip and handler */
420 if (!(ct->type & type))
421 if (irq_setup_alt_chip(d, type))
422 return -EINVAL;
423
424 /*
425 * Configure interrupt polarity.
426 */
427 switch (type) {
428 case IRQ_TYPE_EDGE_RISING:
429 case IRQ_TYPE_LEVEL_HIGH:
430 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
431 u &= ~(1 << pin);
432 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
433 break;
434 case IRQ_TYPE_EDGE_FALLING:
435 case IRQ_TYPE_LEVEL_LOW:
436 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
437 u |= 1 << pin;
438 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
439 break;
440 case IRQ_TYPE_EDGE_BOTH: {
441 u32 v;
442
443 v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^
444 readl_relaxed(mvebu_gpioreg_data_in(mvchip));
445
446 /*
447 * set initial polarity based on current input level
448 */
449 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
450 if (v & (1 << pin))
451 u |= 1 << pin; /* falling */
452 else
453 u &= ~(1 << pin); /* rising */
454 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
455 break;
456 }
457 }
458 return 0;
459 }
460
461 static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
462 {
463 struct mvebu_gpio_chip *mvchip = irq_get_handler_data(irq);
464 struct irq_chip *chip = irq_desc_get_chip(desc);
465 u32 cause, type;
466 int i;
467
468 if (mvchip == NULL)
469 return;
470
471 chained_irq_enter(chip, desc);
472
473 cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) &
474 readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
475 cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) &
476 readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
477
478 for (i = 0; i < mvchip->chip.ngpio; i++) {
479 int irq;
480
481 irq = mvchip->irqbase + i;
482
483 if (!(cause & (1 << i)))
484 continue;
485
486 type = irq_get_trigger_type(irq);
487 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
488 /* Swap polarity (race with GPIO line) */
489 u32 polarity;
490
491 polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
492 polarity ^= 1 << i;
493 writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip));
494 }
495
496 generic_handle_irq(irq);
497 }
498
499 chained_irq_exit(chip, desc);
500 }
501
502 #ifdef CONFIG_DEBUG_FS
503 #include <linux/seq_file.h>
504
505 static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
506 {
507 struct mvebu_gpio_chip *mvchip =
508 container_of(chip, struct mvebu_gpio_chip, chip);
509 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk;
510 int i;
511
512 out = readl_relaxed(mvebu_gpioreg_out(mvchip));
513 io_conf = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
514 blink = readl_relaxed(mvebu_gpioreg_blink(mvchip));
515 in_pol = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
516 data_in = readl_relaxed(mvebu_gpioreg_data_in(mvchip));
517 cause = readl_relaxed(mvebu_gpioreg_edge_cause(mvchip));
518 edg_msk = readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
519 lvl_msk = readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
520
521 for (i = 0; i < chip->ngpio; i++) {
522 const char *label;
523 u32 msk;
524 bool is_out;
525
526 label = gpiochip_is_requested(chip, i);
527 if (!label)
528 continue;
529
530 msk = 1 << i;
531 is_out = !(io_conf & msk);
532
533 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);
534
535 if (is_out) {
536 seq_printf(s, " out %s %s\n",
537 out & msk ? "hi" : "lo",
538 blink & msk ? "(blink )" : "");
539 continue;
540 }
541
542 seq_printf(s, " in %s (act %s) - IRQ",
543 (data_in ^ in_pol) & msk ? "hi" : "lo",
544 in_pol & msk ? "lo" : "hi");
545 if (!((edg_msk | lvl_msk) & msk)) {
546 seq_puts(s, " disabled\n");
547 continue;
548 }
549 if (edg_msk & msk)
550 seq_puts(s, " edge ");
551 if (lvl_msk & msk)
552 seq_puts(s, " level");
553 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear ");
554 }
555 }
556 #else
557 #define mvebu_gpio_dbg_show NULL
558 #endif
559
560 static const struct of_device_id mvebu_gpio_of_match[] = {
561 {
562 .compatible = "marvell,orion-gpio",
563 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION,
564 },
565 {
566 .compatible = "marvell,mv78200-gpio",
567 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200,
568 },
569 {
570 .compatible = "marvell,armadaxp-gpio",
571 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
572 },
573 {
574 /* sentinel */
575 },
576 };
577 MODULE_DEVICE_TABLE(of, mvebu_gpio_of_match);
578
579 static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state)
580 {
581 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
582 int i;
583
584 mvchip->out_reg = readl(mvebu_gpioreg_out(mvchip));
585 mvchip->io_conf_reg = readl(mvebu_gpioreg_io_conf(mvchip));
586 mvchip->blink_en_reg = readl(mvebu_gpioreg_blink(mvchip));
587 mvchip->in_pol_reg = readl(mvebu_gpioreg_in_pol(mvchip));
588
589 switch (mvchip->soc_variant) {
590 case MVEBU_GPIO_SOC_VARIANT_ORION:
591 mvchip->edge_mask_regs[0] =
592 readl(mvchip->membase + GPIO_EDGE_MASK_OFF);
593 mvchip->level_mask_regs[0] =
594 readl(mvchip->membase + GPIO_LEVEL_MASK_OFF);
595 break;
596 case MVEBU_GPIO_SOC_VARIANT_MV78200:
597 for (i = 0; i < 2; i++) {
598 mvchip->edge_mask_regs[i] =
599 readl(mvchip->membase +
600 GPIO_EDGE_MASK_MV78200_OFF(i));
601 mvchip->level_mask_regs[i] =
602 readl(mvchip->membase +
603 GPIO_LEVEL_MASK_MV78200_OFF(i));
604 }
605 break;
606 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
607 for (i = 0; i < 4; i++) {
608 mvchip->edge_mask_regs[i] =
609 readl(mvchip->membase +
610 GPIO_EDGE_MASK_ARMADAXP_OFF(i));
611 mvchip->level_mask_regs[i] =
612 readl(mvchip->membase +
613 GPIO_LEVEL_MASK_ARMADAXP_OFF(i));
614 }
615 break;
616 default:
617 BUG();
618 }
619
620 return 0;
621 }
622
623 static int mvebu_gpio_resume(struct platform_device *pdev)
624 {
625 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev);
626 int i;
627
628 writel(mvchip->out_reg, mvebu_gpioreg_out(mvchip));
629 writel(mvchip->io_conf_reg, mvebu_gpioreg_io_conf(mvchip));
630 writel(mvchip->blink_en_reg, mvebu_gpioreg_blink(mvchip));
631 writel(mvchip->in_pol_reg, mvebu_gpioreg_in_pol(mvchip));
632
633 switch (mvchip->soc_variant) {
634 case MVEBU_GPIO_SOC_VARIANT_ORION:
635 writel(mvchip->edge_mask_regs[0],
636 mvchip->membase + GPIO_EDGE_MASK_OFF);
637 writel(mvchip->level_mask_regs[0],
638 mvchip->membase + GPIO_LEVEL_MASK_OFF);
639 break;
640 case MVEBU_GPIO_SOC_VARIANT_MV78200:
641 for (i = 0; i < 2; i++) {
642 writel(mvchip->edge_mask_regs[i],
643 mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(i));
644 writel(mvchip->level_mask_regs[i],
645 mvchip->membase +
646 GPIO_LEVEL_MASK_MV78200_OFF(i));
647 }
648 break;
649 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
650 for (i = 0; i < 4; i++) {
651 writel(mvchip->edge_mask_regs[i],
652 mvchip->membase +
653 GPIO_EDGE_MASK_ARMADAXP_OFF(i));
654 writel(mvchip->level_mask_regs[i],
655 mvchip->membase +
656 GPIO_LEVEL_MASK_ARMADAXP_OFF(i));
657 }
658 break;
659 default:
660 BUG();
661 }
662
663 return 0;
664 }
665
666 static int mvebu_gpio_probe(struct platform_device *pdev)
667 {
668 struct mvebu_gpio_chip *mvchip;
669 const struct of_device_id *match;
670 struct device_node *np = pdev->dev.of_node;
671 struct resource *res;
672 struct irq_chip_generic *gc;
673 struct irq_chip_type *ct;
674 struct clk *clk;
675 unsigned int ngpios;
676 int soc_variant;
677 int i, cpu, id;
678 int err;
679
680 match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
681 if (match)
682 soc_variant = (int) match->data;
683 else
684 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
685
686 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip),
687 GFP_KERNEL);
688 if (!mvchip)
689 return -ENOMEM;
690
691 platform_set_drvdata(pdev, mvchip);
692
693 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
694 dev_err(&pdev->dev, "Missing ngpios OF property\n");
695 return -ENODEV;
696 }
697
698 id = of_alias_get_id(pdev->dev.of_node, "gpio");
699 if (id < 0) {
700 dev_err(&pdev->dev, "Couldn't get OF id\n");
701 return id;
702 }
703
704 clk = devm_clk_get(&pdev->dev, NULL);
705 /* Not all SoCs require a clock.*/
706 if (!IS_ERR(clk))
707 clk_prepare_enable(clk);
708
709 mvchip->soc_variant = soc_variant;
710 mvchip->chip.label = dev_name(&pdev->dev);
711 mvchip->chip.dev = &pdev->dev;
712 mvchip->chip.request = mvebu_gpio_request;
713 mvchip->chip.free = mvebu_gpio_free;
714 mvchip->chip.direction_input = mvebu_gpio_direction_input;
715 mvchip->chip.get = mvebu_gpio_get;
716 mvchip->chip.direction_output = mvebu_gpio_direction_output;
717 mvchip->chip.set = mvebu_gpio_set;
718 mvchip->chip.to_irq = mvebu_gpio_to_irq;
719 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
720 mvchip->chip.ngpio = ngpios;
721 mvchip->chip.can_sleep = false;
722 mvchip->chip.of_node = np;
723 mvchip->chip.dbg_show = mvebu_gpio_dbg_show;
724
725 spin_lock_init(&mvchip->lock);
726 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
727 mvchip->membase = devm_ioremap_resource(&pdev->dev, res);
728 if (IS_ERR(mvchip->membase))
729 return PTR_ERR(mvchip->membase);
730
731 /* The Armada XP has a second range of registers for the
732 * per-CPU registers */
733 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
734 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
735 mvchip->percpu_membase = devm_ioremap_resource(&pdev->dev,
736 res);
737 if (IS_ERR(mvchip->percpu_membase))
738 return PTR_ERR(mvchip->percpu_membase);
739 }
740
741 /*
742 * Mask and clear GPIO interrupts.
743 */
744 switch (soc_variant) {
745 case MVEBU_GPIO_SOC_VARIANT_ORION:
746 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
747 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
748 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
749 break;
750 case MVEBU_GPIO_SOC_VARIANT_MV78200:
751 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
752 for (cpu = 0; cpu < 2; cpu++) {
753 writel_relaxed(0, mvchip->membase +
754 GPIO_EDGE_MASK_MV78200_OFF(cpu));
755 writel_relaxed(0, mvchip->membase +
756 GPIO_LEVEL_MASK_MV78200_OFF(cpu));
757 }
758 break;
759 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
760 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
761 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
762 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
763 for (cpu = 0; cpu < 4; cpu++) {
764 writel_relaxed(0, mvchip->percpu_membase +
765 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu));
766 writel_relaxed(0, mvchip->percpu_membase +
767 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu));
768 writel_relaxed(0, mvchip->percpu_membase +
769 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu));
770 }
771 break;
772 default:
773 BUG();
774 }
775
776 gpiochip_add(&mvchip->chip);
777
778 /* Some gpio controllers do not provide irq support */
779 if (!of_irq_count(np))
780 return 0;
781
782 /* Setup the interrupt handlers. Each chip can have up to 4
783 * interrupt handlers, with each handler dealing with 8 GPIO
784 * pins. */
785 for (i = 0; i < 4; i++) {
786 int irq = platform_get_irq(pdev, i);
787
788 if (irq < 0)
789 continue;
790 irq_set_handler_data(irq, mvchip);
791 irq_set_chained_handler(irq, mvebu_gpio_irq_handler);
792 }
793
794 mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1);
795 if (mvchip->irqbase < 0) {
796 dev_err(&pdev->dev, "no irqs\n");
797 err = mvchip->irqbase;
798 goto err_gpiochip_add;
799 }
800
801 gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase,
802 mvchip->membase, handle_level_irq);
803 if (!gc) {
804 dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n");
805 err = -ENOMEM;
806 goto err_gpiochip_add;
807 }
808
809 gc->private = mvchip;
810 ct = &gc->chip_types[0];
811 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
812 ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
813 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
814 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
815 ct->chip.name = mvchip->chip.label;
816
817 ct = &gc->chip_types[1];
818 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
819 ct->chip.irq_ack = mvebu_gpio_irq_ack;
820 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
821 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
822 ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
823 ct->handler = handle_edge_irq;
824 ct->chip.name = mvchip->chip.label;
825
826 irq_setup_generic_chip(gc, IRQ_MSK(ngpios), 0,
827 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
828
829 /* Setup irq domain on top of the generic chip. */
830 mvchip->domain = irq_domain_add_simple(np, mvchip->chip.ngpio,
831 mvchip->irqbase,
832 &irq_domain_simple_ops,
833 mvchip);
834 if (!mvchip->domain) {
835 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
836 mvchip->chip.label);
837 err = -ENODEV;
838 goto err_generic_chip;
839 }
840
841 return 0;
842
843 err_generic_chip:
844 irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST,
845 IRQ_LEVEL | IRQ_NOPROBE);
846 kfree(gc);
847
848 err_gpiochip_add:
849 gpiochip_remove(&mvchip->chip);
850
851 return err;
852 }
853
854 static struct platform_driver mvebu_gpio_driver = {
855 .driver = {
856 .name = "mvebu-gpio",
857 .of_match_table = mvebu_gpio_of_match,
858 },
859 .probe = mvebu_gpio_probe,
860 .suspend = mvebu_gpio_suspend,
861 .resume = mvebu_gpio_resume,
862 };
863 module_platform_driver(mvebu_gpio_driver);
Linux kernel - Deliverables
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