2 * Support functions for OMAP GPIO
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
26 #include <linux/of_device.h>
27 #include <linux/gpio.h>
28 #include <linux/bitops.h>
29 #include <linux/platform_data/gpio-omap.h>
33 static LIST_HEAD(omap_gpio_list
);
51 struct list_head node
;
55 u32 enabled_non_wakeup_gpios
;
56 struct gpio_regs context
;
61 struct gpio_chip chip
;
74 int context_loss_count
;
76 bool workaround_enabled
;
78 void (*set_dataout
)(struct gpio_bank
*bank
, int gpio
, int enable
);
79 int (*get_context_loss_count
)(struct device
*dev
);
81 struct omap_gpio_reg_offs
*regs
;
84 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
85 #define GPIO_BIT(bank, gpio) (BIT(GPIO_INDEX(bank, gpio)))
86 #define GPIO_MOD_CTRL_BIT BIT(0)
88 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
89 #define LINE_USED(line, offset) (line & (BIT(offset)))
91 static int omap_irq_to_gpio(struct gpio_bank
*bank
, unsigned int gpio_irq
)
93 return bank
->chip
.base
+ gpio_irq
;
96 static inline struct gpio_bank
*omap_irq_data_get_bank(struct irq_data
*d
)
98 struct gpio_chip
*chip
= irq_data_get_irq_chip_data(d
);
99 return container_of(chip
, struct gpio_bank
, chip
);
102 static void omap_set_gpio_direction(struct gpio_bank
*bank
, int gpio
,
105 void __iomem
*reg
= bank
->base
;
108 reg
+= bank
->regs
->direction
;
109 l
= readl_relaxed(reg
);
114 writel_relaxed(l
, reg
);
115 bank
->context
.oe
= l
;
119 /* set data out value using dedicate set/clear register */
120 static void omap_set_gpio_dataout_reg(struct gpio_bank
*bank
, int gpio
,
123 void __iomem
*reg
= bank
->base
;
124 u32 l
= GPIO_BIT(bank
, gpio
);
127 reg
+= bank
->regs
->set_dataout
;
128 bank
->context
.dataout
|= l
;
130 reg
+= bank
->regs
->clr_dataout
;
131 bank
->context
.dataout
&= ~l
;
134 writel_relaxed(l
, reg
);
137 /* set data out value using mask register */
138 static void omap_set_gpio_dataout_mask(struct gpio_bank
*bank
, int gpio
,
141 void __iomem
*reg
= bank
->base
+ bank
->regs
->dataout
;
142 u32 gpio_bit
= GPIO_BIT(bank
, gpio
);
145 l
= readl_relaxed(reg
);
150 writel_relaxed(l
, reg
);
151 bank
->context
.dataout
= l
;
154 static int omap_get_gpio_datain(struct gpio_bank
*bank
, int offset
)
156 void __iomem
*reg
= bank
->base
+ bank
->regs
->datain
;
158 return (readl_relaxed(reg
) & (BIT(offset
))) != 0;
161 static int omap_get_gpio_dataout(struct gpio_bank
*bank
, int offset
)
163 void __iomem
*reg
= bank
->base
+ bank
->regs
->dataout
;
165 return (readl_relaxed(reg
) & (BIT(offset
))) != 0;
168 static inline void omap_gpio_rmw(void __iomem
*base
, u32 reg
, u32 mask
, bool set
)
170 int l
= readl_relaxed(base
+ reg
);
177 writel_relaxed(l
, base
+ reg
);
180 static inline void omap_gpio_dbck_enable(struct gpio_bank
*bank
)
182 if (bank
->dbck_enable_mask
&& !bank
->dbck_enabled
) {
183 clk_prepare_enable(bank
->dbck
);
184 bank
->dbck_enabled
= true;
186 writel_relaxed(bank
->dbck_enable_mask
,
187 bank
->base
+ bank
->regs
->debounce_en
);
191 static inline void omap_gpio_dbck_disable(struct gpio_bank
*bank
)
193 if (bank
->dbck_enable_mask
&& bank
->dbck_enabled
) {
195 * Disable debounce before cutting it's clock. If debounce is
196 * enabled but the clock is not, GPIO module seems to be unable
197 * to detect events and generate interrupts at least on OMAP3.
199 writel_relaxed(0, bank
->base
+ bank
->regs
->debounce_en
);
201 clk_disable_unprepare(bank
->dbck
);
202 bank
->dbck_enabled
= false;
207 * omap2_set_gpio_debounce - low level gpio debounce time
208 * @bank: the gpio bank we're acting upon
209 * @gpio: the gpio number on this @gpio
210 * @debounce: debounce time to use
212 * OMAP's debounce time is in 31us steps so we need
213 * to convert and round up to the closest unit.
215 static void omap2_set_gpio_debounce(struct gpio_bank
*bank
, unsigned gpio
,
222 if (!bank
->dbck_flag
)
227 else if (debounce
> 7936)
230 debounce
= (debounce
/ 0x1f) - 1;
232 l
= GPIO_BIT(bank
, gpio
);
234 clk_prepare_enable(bank
->dbck
);
235 reg
= bank
->base
+ bank
->regs
->debounce
;
236 writel_relaxed(debounce
, reg
);
238 reg
= bank
->base
+ bank
->regs
->debounce_en
;
239 val
= readl_relaxed(reg
);
245 bank
->dbck_enable_mask
= val
;
247 writel_relaxed(val
, reg
);
248 clk_disable_unprepare(bank
->dbck
);
250 * Enable debounce clock per module.
251 * This call is mandatory because in omap_gpio_request() when
252 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
253 * runtime callbck fails to turn on dbck because dbck_enable_mask
254 * used within _gpio_dbck_enable() is still not initialized at
255 * that point. Therefore we have to enable dbck here.
257 omap_gpio_dbck_enable(bank
);
258 if (bank
->dbck_enable_mask
) {
259 bank
->context
.debounce
= debounce
;
260 bank
->context
.debounce_en
= val
;
265 * omap_clear_gpio_debounce - clear debounce settings for a gpio
266 * @bank: the gpio bank we're acting upon
267 * @gpio: the gpio number on this @gpio
269 * If a gpio is using debounce, then clear the debounce enable bit and if
270 * this is the only gpio in this bank using debounce, then clear the debounce
271 * time too. The debounce clock will also be disabled when calling this function
272 * if this is the only gpio in the bank using debounce.
274 static void omap_clear_gpio_debounce(struct gpio_bank
*bank
, unsigned gpio
)
276 u32 gpio_bit
= GPIO_BIT(bank
, gpio
);
278 if (!bank
->dbck_flag
)
281 if (!(bank
->dbck_enable_mask
& gpio_bit
))
284 bank
->dbck_enable_mask
&= ~gpio_bit
;
285 bank
->context
.debounce_en
&= ~gpio_bit
;
286 writel_relaxed(bank
->context
.debounce_en
,
287 bank
->base
+ bank
->regs
->debounce_en
);
289 if (!bank
->dbck_enable_mask
) {
290 bank
->context
.debounce
= 0;
291 writel_relaxed(bank
->context
.debounce
, bank
->base
+
292 bank
->regs
->debounce
);
293 clk_disable_unprepare(bank
->dbck
);
294 bank
->dbck_enabled
= false;
298 static inline void omap_set_gpio_trigger(struct gpio_bank
*bank
, int gpio
,
301 void __iomem
*base
= bank
->base
;
302 u32 gpio_bit
= BIT(gpio
);
304 omap_gpio_rmw(base
, bank
->regs
->leveldetect0
, gpio_bit
,
305 trigger
& IRQ_TYPE_LEVEL_LOW
);
306 omap_gpio_rmw(base
, bank
->regs
->leveldetect1
, gpio_bit
,
307 trigger
& IRQ_TYPE_LEVEL_HIGH
);
308 omap_gpio_rmw(base
, bank
->regs
->risingdetect
, gpio_bit
,
309 trigger
& IRQ_TYPE_EDGE_RISING
);
310 omap_gpio_rmw(base
, bank
->regs
->fallingdetect
, gpio_bit
,
311 trigger
& IRQ_TYPE_EDGE_FALLING
);
313 bank
->context
.leveldetect0
=
314 readl_relaxed(bank
->base
+ bank
->regs
->leveldetect0
);
315 bank
->context
.leveldetect1
=
316 readl_relaxed(bank
->base
+ bank
->regs
->leveldetect1
);
317 bank
->context
.risingdetect
=
318 readl_relaxed(bank
->base
+ bank
->regs
->risingdetect
);
319 bank
->context
.fallingdetect
=
320 readl_relaxed(bank
->base
+ bank
->regs
->fallingdetect
);
322 if (likely(!(bank
->non_wakeup_gpios
& gpio_bit
))) {
323 omap_gpio_rmw(base
, bank
->regs
->wkup_en
, gpio_bit
, trigger
!= 0);
324 bank
->context
.wake_en
=
325 readl_relaxed(bank
->base
+ bank
->regs
->wkup_en
);
328 /* This part needs to be executed always for OMAP{34xx, 44xx} */
329 if (!bank
->regs
->irqctrl
) {
330 /* On omap24xx proceed only when valid GPIO bit is set */
331 if (bank
->non_wakeup_gpios
) {
332 if (!(bank
->non_wakeup_gpios
& gpio_bit
))
337 * Log the edge gpio and manually trigger the IRQ
338 * after resume if the input level changes
339 * to avoid irq lost during PER RET/OFF mode
340 * Applies for omap2 non-wakeup gpio and all omap3 gpios
342 if (trigger
& IRQ_TYPE_EDGE_BOTH
)
343 bank
->enabled_non_wakeup_gpios
|= gpio_bit
;
345 bank
->enabled_non_wakeup_gpios
&= ~gpio_bit
;
350 readl_relaxed(bank
->base
+ bank
->regs
->leveldetect0
) |
351 readl_relaxed(bank
->base
+ bank
->regs
->leveldetect1
);
354 #ifdef CONFIG_ARCH_OMAP1
356 * This only applies to chips that can't do both rising and falling edge
357 * detection at once. For all other chips, this function is a noop.
359 static void omap_toggle_gpio_edge_triggering(struct gpio_bank
*bank
, int gpio
)
361 void __iomem
*reg
= bank
->base
;
364 if (!bank
->regs
->irqctrl
)
367 reg
+= bank
->regs
->irqctrl
;
369 l
= readl_relaxed(reg
);
375 writel_relaxed(l
, reg
);
378 static void omap_toggle_gpio_edge_triggering(struct gpio_bank
*bank
, int gpio
) {}
381 static int omap_set_gpio_triggering(struct gpio_bank
*bank
, int gpio
,
384 void __iomem
*reg
= bank
->base
;
385 void __iomem
*base
= bank
->base
;
388 if (bank
->regs
->leveldetect0
&& bank
->regs
->wkup_en
) {
389 omap_set_gpio_trigger(bank
, gpio
, trigger
);
390 } else if (bank
->regs
->irqctrl
) {
391 reg
+= bank
->regs
->irqctrl
;
393 l
= readl_relaxed(reg
);
394 if ((trigger
& IRQ_TYPE_SENSE_MASK
) == IRQ_TYPE_EDGE_BOTH
)
395 bank
->toggle_mask
|= BIT(gpio
);
396 if (trigger
& IRQ_TYPE_EDGE_RISING
)
398 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
403 writel_relaxed(l
, reg
);
404 } else if (bank
->regs
->edgectrl1
) {
406 reg
+= bank
->regs
->edgectrl2
;
408 reg
+= bank
->regs
->edgectrl1
;
411 l
= readl_relaxed(reg
);
412 l
&= ~(3 << (gpio
<< 1));
413 if (trigger
& IRQ_TYPE_EDGE_RISING
)
414 l
|= 2 << (gpio
<< 1);
415 if (trigger
& IRQ_TYPE_EDGE_FALLING
)
418 /* Enable wake-up during idle for dynamic tick */
419 omap_gpio_rmw(base
, bank
->regs
->wkup_en
, BIT(gpio
), trigger
);
420 bank
->context
.wake_en
=
421 readl_relaxed(bank
->base
+ bank
->regs
->wkup_en
);
422 writel_relaxed(l
, reg
);
427 static void omap_enable_gpio_module(struct gpio_bank
*bank
, unsigned offset
)
429 if (bank
->regs
->pinctrl
) {
430 void __iomem
*reg
= bank
->base
+ bank
->regs
->pinctrl
;
432 /* Claim the pin for MPU */
433 writel_relaxed(readl_relaxed(reg
) | (BIT(offset
)), reg
);
436 if (bank
->regs
->ctrl
&& !BANK_USED(bank
)) {
437 void __iomem
*reg
= bank
->base
+ bank
->regs
->ctrl
;
440 ctrl
= readl_relaxed(reg
);
441 /* Module is enabled, clocks are not gated */
442 ctrl
&= ~GPIO_MOD_CTRL_BIT
;
443 writel_relaxed(ctrl
, reg
);
444 bank
->context
.ctrl
= ctrl
;
448 static void omap_disable_gpio_module(struct gpio_bank
*bank
, unsigned offset
)
450 void __iomem
*base
= bank
->base
;
452 if (bank
->regs
->wkup_en
&&
453 !LINE_USED(bank
->mod_usage
, offset
) &&
454 !LINE_USED(bank
->irq_usage
, offset
)) {
455 /* Disable wake-up during idle for dynamic tick */
456 omap_gpio_rmw(base
, bank
->regs
->wkup_en
, BIT(offset
), 0);
457 bank
->context
.wake_en
=
458 readl_relaxed(bank
->base
+ bank
->regs
->wkup_en
);
461 if (bank
->regs
->ctrl
&& !BANK_USED(bank
)) {
462 void __iomem
*reg
= bank
->base
+ bank
->regs
->ctrl
;
465 ctrl
= readl_relaxed(reg
);
466 /* Module is disabled, clocks are gated */
467 ctrl
|= GPIO_MOD_CTRL_BIT
;
468 writel_relaxed(ctrl
, reg
);
469 bank
->context
.ctrl
= ctrl
;
473 static int omap_gpio_is_input(struct gpio_bank
*bank
, int mask
)
475 void __iomem
*reg
= bank
->base
+ bank
->regs
->direction
;
477 return readl_relaxed(reg
) & mask
;
480 static int omap_gpio_irq_type(struct irq_data
*d
, unsigned type
)
482 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
488 if (!BANK_USED(bank
))
489 pm_runtime_get_sync(bank
->dev
);
491 #ifdef CONFIG_ARCH_OMAP1
492 if (d
->irq
> IH_MPUIO_BASE
)
493 gpio
= OMAP_MPUIO(d
->irq
- IH_MPUIO_BASE
);
497 gpio
= omap_irq_to_gpio(bank
, d
->hwirq
);
499 if (type
& ~IRQ_TYPE_SENSE_MASK
)
502 if (!bank
->regs
->leveldetect0
&&
503 (type
& (IRQ_TYPE_LEVEL_LOW
|IRQ_TYPE_LEVEL_HIGH
)))
506 spin_lock_irqsave(&bank
->lock
, flags
);
507 offset
= GPIO_INDEX(bank
, gpio
);
508 retval
= omap_set_gpio_triggering(bank
, offset
, type
);
509 if (!LINE_USED(bank
->mod_usage
, offset
)) {
510 omap_enable_gpio_module(bank
, offset
);
511 omap_set_gpio_direction(bank
, offset
, 1);
512 } else if (!omap_gpio_is_input(bank
, BIT(offset
))) {
513 spin_unlock_irqrestore(&bank
->lock
, flags
);
517 bank
->irq_usage
|= BIT(GPIO_INDEX(bank
, gpio
));
518 spin_unlock_irqrestore(&bank
->lock
, flags
);
520 if (type
& (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
))
521 __irq_set_handler_locked(d
->irq
, handle_level_irq
);
522 else if (type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
523 __irq_set_handler_locked(d
->irq
, handle_edge_irq
);
528 static void omap_clear_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
)
530 void __iomem
*reg
= bank
->base
;
532 reg
+= bank
->regs
->irqstatus
;
533 writel_relaxed(gpio_mask
, reg
);
535 /* Workaround for clearing DSP GPIO interrupts to allow retention */
536 if (bank
->regs
->irqstatus2
) {
537 reg
= bank
->base
+ bank
->regs
->irqstatus2
;
538 writel_relaxed(gpio_mask
, reg
);
541 /* Flush posted write for the irq status to avoid spurious interrupts */
545 static inline void omap_clear_gpio_irqstatus(struct gpio_bank
*bank
, int gpio
)
547 omap_clear_gpio_irqbank(bank
, GPIO_BIT(bank
, gpio
));
550 static u32
omap_get_gpio_irqbank_mask(struct gpio_bank
*bank
)
552 void __iomem
*reg
= bank
->base
;
554 u32 mask
= (BIT(bank
->width
)) - 1;
556 reg
+= bank
->regs
->irqenable
;
557 l
= readl_relaxed(reg
);
558 if (bank
->regs
->irqenable_inv
)
564 static void omap_enable_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
)
566 void __iomem
*reg
= bank
->base
;
569 if (bank
->regs
->set_irqenable
) {
570 reg
+= bank
->regs
->set_irqenable
;
572 bank
->context
.irqenable1
|= gpio_mask
;
574 reg
+= bank
->regs
->irqenable
;
575 l
= readl_relaxed(reg
);
576 if (bank
->regs
->irqenable_inv
)
580 bank
->context
.irqenable1
= l
;
583 writel_relaxed(l
, reg
);
586 static void omap_disable_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
)
588 void __iomem
*reg
= bank
->base
;
591 if (bank
->regs
->clr_irqenable
) {
592 reg
+= bank
->regs
->clr_irqenable
;
594 bank
->context
.irqenable1
&= ~gpio_mask
;
596 reg
+= bank
->regs
->irqenable
;
597 l
= readl_relaxed(reg
);
598 if (bank
->regs
->irqenable_inv
)
602 bank
->context
.irqenable1
= l
;
605 writel_relaxed(l
, reg
);
608 static inline void omap_set_gpio_irqenable(struct gpio_bank
*bank
, int gpio
,
612 omap_enable_gpio_irqbank(bank
, GPIO_BIT(bank
, gpio
));
614 omap_disable_gpio_irqbank(bank
, GPIO_BIT(bank
, gpio
));
618 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
619 * 1510 does not seem to have a wake-up register. If JTAG is connected
620 * to the target, system will wake up always on GPIO events. While
621 * system is running all registered GPIO interrupts need to have wake-up
622 * enabled. When system is suspended, only selected GPIO interrupts need
623 * to have wake-up enabled.
625 static int omap_set_gpio_wakeup(struct gpio_bank
*bank
, int gpio
, int enable
)
627 u32 gpio_bit
= GPIO_BIT(bank
, gpio
);
630 if (bank
->non_wakeup_gpios
& gpio_bit
) {
632 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio
);
636 spin_lock_irqsave(&bank
->lock
, flags
);
638 bank
->context
.wake_en
|= gpio_bit
;
640 bank
->context
.wake_en
&= ~gpio_bit
;
642 writel_relaxed(bank
->context
.wake_en
, bank
->base
+ bank
->regs
->wkup_en
);
643 spin_unlock_irqrestore(&bank
->lock
, flags
);
648 static void omap_reset_gpio(struct gpio_bank
*bank
, int gpio
)
650 omap_set_gpio_direction(bank
, GPIO_INDEX(bank
, gpio
), 1);
651 omap_set_gpio_irqenable(bank
, gpio
, 0);
652 omap_clear_gpio_irqstatus(bank
, gpio
);
653 omap_set_gpio_triggering(bank
, GPIO_INDEX(bank
, gpio
), IRQ_TYPE_NONE
);
654 omap_clear_gpio_debounce(bank
, gpio
);
657 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
658 static int omap_gpio_wake_enable(struct irq_data
*d
, unsigned int enable
)
660 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
661 unsigned int gpio
= omap_irq_to_gpio(bank
, d
->hwirq
);
663 return omap_set_gpio_wakeup(bank
, gpio
, enable
);
666 static int omap_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
668 struct gpio_bank
*bank
= container_of(chip
, struct gpio_bank
, chip
);
672 * If this is the first gpio_request for the bank,
673 * enable the bank module.
675 if (!BANK_USED(bank
))
676 pm_runtime_get_sync(bank
->dev
);
678 spin_lock_irqsave(&bank
->lock
, flags
);
679 /* Set trigger to none. You need to enable the desired trigger with
680 * request_irq() or set_irq_type(). Only do this if the IRQ line has
681 * not already been requested.
683 if (!LINE_USED(bank
->irq_usage
, offset
)) {
684 omap_set_gpio_triggering(bank
, offset
, IRQ_TYPE_NONE
);
685 omap_enable_gpio_module(bank
, offset
);
687 bank
->mod_usage
|= BIT(offset
);
688 spin_unlock_irqrestore(&bank
->lock
, flags
);
693 static void omap_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
695 struct gpio_bank
*bank
= container_of(chip
, struct gpio_bank
, chip
);
698 spin_lock_irqsave(&bank
->lock
, flags
);
699 bank
->mod_usage
&= ~(BIT(offset
));
700 omap_disable_gpio_module(bank
, offset
);
701 omap_reset_gpio(bank
, bank
->chip
.base
+ offset
);
702 spin_unlock_irqrestore(&bank
->lock
, flags
);
705 * If this is the last gpio to be freed in the bank,
706 * disable the bank module.
708 if (!BANK_USED(bank
))
709 pm_runtime_put(bank
->dev
);
713 * We need to unmask the GPIO bank interrupt as soon as possible to
714 * avoid missing GPIO interrupts for other lines in the bank.
715 * Then we need to mask-read-clear-unmask the triggered GPIO lines
716 * in the bank to avoid missing nested interrupts for a GPIO line.
717 * If we wait to unmask individual GPIO lines in the bank after the
718 * line's interrupt handler has been run, we may miss some nested
721 static void omap_gpio_irq_handler(unsigned int irq
, struct irq_desc
*desc
)
723 void __iomem
*isr_reg
= NULL
;
726 struct gpio_bank
*bank
;
728 struct irq_chip
*irqchip
= irq_desc_get_chip(desc
);
729 struct gpio_chip
*chip
= irq_get_handler_data(irq
);
731 chained_irq_enter(irqchip
, desc
);
733 bank
= container_of(chip
, struct gpio_bank
, chip
);
734 isr_reg
= bank
->base
+ bank
->regs
->irqstatus
;
735 pm_runtime_get_sync(bank
->dev
);
737 if (WARN_ON(!isr_reg
))
741 u32 isr_saved
, level_mask
= 0;
744 enabled
= omap_get_gpio_irqbank_mask(bank
);
745 isr_saved
= isr
= readl_relaxed(isr_reg
) & enabled
;
747 if (bank
->level_mask
)
748 level_mask
= bank
->level_mask
& enabled
;
750 /* clear edge sensitive interrupts before handler(s) are
751 called so that we don't miss any interrupt occurred while
753 omap_disable_gpio_irqbank(bank
, isr_saved
& ~level_mask
);
754 omap_clear_gpio_irqbank(bank
, isr_saved
& ~level_mask
);
755 omap_enable_gpio_irqbank(bank
, isr_saved
& ~level_mask
);
757 /* if there is only edge sensitive GPIO pin interrupts
758 configured, we could unmask GPIO bank interrupt immediately */
759 if (!level_mask
&& !unmasked
) {
761 chained_irq_exit(irqchip
, desc
);
772 * Some chips can't respond to both rising and falling
773 * at the same time. If this irq was requested with
774 * both flags, we need to flip the ICR data for the IRQ
775 * to respond to the IRQ for the opposite direction.
776 * This will be indicated in the bank toggle_mask.
778 if (bank
->toggle_mask
& (BIT(bit
)))
779 omap_toggle_gpio_edge_triggering(bank
, bit
);
781 generic_handle_irq(irq_find_mapping(bank
->chip
.irqdomain
,
785 /* if bank has any level sensitive GPIO pin interrupt
786 configured, we must unmask the bank interrupt only after
787 handler(s) are executed in order to avoid spurious bank
791 chained_irq_exit(irqchip
, desc
);
792 pm_runtime_put(bank
->dev
);
795 static void omap_gpio_irq_shutdown(struct irq_data
*d
)
797 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
798 unsigned int gpio
= omap_irq_to_gpio(bank
, d
->hwirq
);
800 unsigned offset
= GPIO_INDEX(bank
, gpio
);
802 spin_lock_irqsave(&bank
->lock
, flags
);
803 gpio_unlock_as_irq(&bank
->chip
, offset
);
804 bank
->irq_usage
&= ~(BIT(offset
));
805 omap_disable_gpio_module(bank
, offset
);
806 omap_reset_gpio(bank
, gpio
);
807 spin_unlock_irqrestore(&bank
->lock
, flags
);
810 * If this is the last IRQ to be freed in the bank,
811 * disable the bank module.
813 if (!BANK_USED(bank
))
814 pm_runtime_put(bank
->dev
);
817 static void omap_gpio_ack_irq(struct irq_data
*d
)
819 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
820 unsigned int gpio
= omap_irq_to_gpio(bank
, d
->hwirq
);
822 omap_clear_gpio_irqstatus(bank
, gpio
);
825 static void omap_gpio_mask_irq(struct irq_data
*d
)
827 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
828 unsigned int gpio
= omap_irq_to_gpio(bank
, d
->hwirq
);
831 spin_lock_irqsave(&bank
->lock
, flags
);
832 omap_set_gpio_irqenable(bank
, gpio
, 0);
833 omap_set_gpio_triggering(bank
, GPIO_INDEX(bank
, gpio
), IRQ_TYPE_NONE
);
834 spin_unlock_irqrestore(&bank
->lock
, flags
);
837 static void omap_gpio_unmask_irq(struct irq_data
*d
)
839 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
840 unsigned int gpio
= omap_irq_to_gpio(bank
, d
->hwirq
);
841 unsigned int irq_mask
= GPIO_BIT(bank
, gpio
);
842 u32 trigger
= irqd_get_trigger_type(d
);
845 spin_lock_irqsave(&bank
->lock
, flags
);
847 omap_set_gpio_triggering(bank
, GPIO_INDEX(bank
, gpio
), trigger
);
849 /* For level-triggered GPIOs, the clearing must be done after
850 * the HW source is cleared, thus after the handler has run */
851 if (bank
->level_mask
& irq_mask
) {
852 omap_set_gpio_irqenable(bank
, gpio
, 0);
853 omap_clear_gpio_irqstatus(bank
, gpio
);
856 omap_set_gpio_irqenable(bank
, gpio
, 1);
857 spin_unlock_irqrestore(&bank
->lock
, flags
);
860 static struct irq_chip gpio_irq_chip
= {
862 .irq_shutdown
= omap_gpio_irq_shutdown
,
863 .irq_ack
= omap_gpio_ack_irq
,
864 .irq_mask
= omap_gpio_mask_irq
,
865 .irq_unmask
= omap_gpio_unmask_irq
,
866 .irq_set_type
= omap_gpio_irq_type
,
867 .irq_set_wake
= omap_gpio_wake_enable
,
870 /*---------------------------------------------------------------------*/
872 static int omap_mpuio_suspend_noirq(struct device
*dev
)
874 struct platform_device
*pdev
= to_platform_device(dev
);
875 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
876 void __iomem
*mask_reg
= bank
->base
+
877 OMAP_MPUIO_GPIO_MASKIT
/ bank
->stride
;
880 spin_lock_irqsave(&bank
->lock
, flags
);
881 writel_relaxed(0xffff & ~bank
->context
.wake_en
, mask_reg
);
882 spin_unlock_irqrestore(&bank
->lock
, flags
);
887 static int omap_mpuio_resume_noirq(struct device
*dev
)
889 struct platform_device
*pdev
= to_platform_device(dev
);
890 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
891 void __iomem
*mask_reg
= bank
->base
+
892 OMAP_MPUIO_GPIO_MASKIT
/ bank
->stride
;
895 spin_lock_irqsave(&bank
->lock
, flags
);
896 writel_relaxed(bank
->context
.wake_en
, mask_reg
);
897 spin_unlock_irqrestore(&bank
->lock
, flags
);
902 static const struct dev_pm_ops omap_mpuio_dev_pm_ops
= {
903 .suspend_noirq
= omap_mpuio_suspend_noirq
,
904 .resume_noirq
= omap_mpuio_resume_noirq
,
907 /* use platform_driver for this. */
908 static struct platform_driver omap_mpuio_driver
= {
911 .pm
= &omap_mpuio_dev_pm_ops
,
915 static struct platform_device omap_mpuio_device
= {
919 .driver
= &omap_mpuio_driver
.driver
,
921 /* could list the /proc/iomem resources */
924 static inline void omap_mpuio_init(struct gpio_bank
*bank
)
926 platform_set_drvdata(&omap_mpuio_device
, bank
);
928 if (platform_driver_register(&omap_mpuio_driver
) == 0)
929 (void) platform_device_register(&omap_mpuio_device
);
932 /*---------------------------------------------------------------------*/
934 static int omap_gpio_get_direction(struct gpio_chip
*chip
, unsigned offset
)
936 struct gpio_bank
*bank
;
941 bank
= container_of(chip
, struct gpio_bank
, chip
);
942 reg
= bank
->base
+ bank
->regs
->direction
;
943 spin_lock_irqsave(&bank
->lock
, flags
);
944 dir
= !!(readl_relaxed(reg
) & BIT(offset
));
945 spin_unlock_irqrestore(&bank
->lock
, flags
);
949 static int omap_gpio_input(struct gpio_chip
*chip
, unsigned offset
)
951 struct gpio_bank
*bank
;
954 bank
= container_of(chip
, struct gpio_bank
, chip
);
955 spin_lock_irqsave(&bank
->lock
, flags
);
956 omap_set_gpio_direction(bank
, offset
, 1);
957 spin_unlock_irqrestore(&bank
->lock
, flags
);
961 static int omap_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
963 struct gpio_bank
*bank
;
966 bank
= container_of(chip
, struct gpio_bank
, chip
);
967 mask
= (BIT(offset
));
969 if (omap_gpio_is_input(bank
, mask
))
970 return omap_get_gpio_datain(bank
, offset
);
972 return omap_get_gpio_dataout(bank
, offset
);
975 static int omap_gpio_output(struct gpio_chip
*chip
, unsigned offset
, int value
)
977 struct gpio_bank
*bank
;
980 bank
= container_of(chip
, struct gpio_bank
, chip
);
981 spin_lock_irqsave(&bank
->lock
, flags
);
982 bank
->set_dataout(bank
, offset
, value
);
983 omap_set_gpio_direction(bank
, offset
, 0);
984 spin_unlock_irqrestore(&bank
->lock
, flags
);
988 static int omap_gpio_debounce(struct gpio_chip
*chip
, unsigned offset
,
991 struct gpio_bank
*bank
;
994 bank
= container_of(chip
, struct gpio_bank
, chip
);
996 spin_lock_irqsave(&bank
->lock
, flags
);
997 omap2_set_gpio_debounce(bank
, offset
, debounce
);
998 spin_unlock_irqrestore(&bank
->lock
, flags
);
1003 static void omap_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
1005 struct gpio_bank
*bank
;
1006 unsigned long flags
;
1008 bank
= container_of(chip
, struct gpio_bank
, chip
);
1009 spin_lock_irqsave(&bank
->lock
, flags
);
1010 bank
->set_dataout(bank
, offset
, value
);
1011 spin_unlock_irqrestore(&bank
->lock
, flags
);
1014 /*---------------------------------------------------------------------*/
1016 static void __init
omap_gpio_show_rev(struct gpio_bank
*bank
)
1021 if (called
|| bank
->regs
->revision
== USHRT_MAX
)
1024 rev
= readw_relaxed(bank
->base
+ bank
->regs
->revision
);
1025 pr_info("OMAP GPIO hardware version %d.%d\n",
1026 (rev
>> 4) & 0x0f, rev
& 0x0f);
1031 static void omap_gpio_mod_init(struct gpio_bank
*bank
)
1033 void __iomem
*base
= bank
->base
;
1036 if (bank
->width
== 16)
1039 if (bank
->is_mpuio
) {
1040 writel_relaxed(l
, bank
->base
+ bank
->regs
->irqenable
);
1044 omap_gpio_rmw(base
, bank
->regs
->irqenable
, l
,
1045 bank
->regs
->irqenable_inv
);
1046 omap_gpio_rmw(base
, bank
->regs
->irqstatus
, l
,
1047 !bank
->regs
->irqenable_inv
);
1048 if (bank
->regs
->debounce_en
)
1049 writel_relaxed(0, base
+ bank
->regs
->debounce_en
);
1051 /* Save OE default value (0xffffffff) in the context */
1052 bank
->context
.oe
= readl_relaxed(bank
->base
+ bank
->regs
->direction
);
1053 /* Initialize interface clk ungated, module enabled */
1054 if (bank
->regs
->ctrl
)
1055 writel_relaxed(0, base
+ bank
->regs
->ctrl
);
1057 bank
->dbck
= clk_get(bank
->dev
, "dbclk");
1058 if (IS_ERR(bank
->dbck
))
1059 dev_err(bank
->dev
, "Could not get gpio dbck\n");
1063 omap_mpuio_alloc_gc(struct gpio_bank
*bank
, unsigned int irq_start
,
1066 struct irq_chip_generic
*gc
;
1067 struct irq_chip_type
*ct
;
1069 gc
= irq_alloc_generic_chip("MPUIO", 1, irq_start
, bank
->base
,
1072 dev_err(bank
->dev
, "Memory alloc failed for gc\n");
1076 ct
= gc
->chip_types
;
1078 /* NOTE: No ack required, reading IRQ status clears it. */
1079 ct
->chip
.irq_mask
= irq_gc_mask_set_bit
;
1080 ct
->chip
.irq_unmask
= irq_gc_mask_clr_bit
;
1081 ct
->chip
.irq_set_type
= omap_gpio_irq_type
;
1083 if (bank
->regs
->wkup_en
)
1084 ct
->chip
.irq_set_wake
= omap_gpio_wake_enable
;
1086 ct
->regs
.mask
= OMAP_MPUIO_GPIO_INT
/ bank
->stride
;
1087 irq_setup_generic_chip(gc
, IRQ_MSK(num
), IRQ_GC_INIT_MASK_CACHE
,
1088 IRQ_NOREQUEST
| IRQ_NOPROBE
, 0);
1091 static int omap_gpio_chip_init(struct gpio_bank
*bank
)
1099 * REVISIT eventually switch from OMAP-specific gpio structs
1100 * over to the generic ones
1102 bank
->chip
.request
= omap_gpio_request
;
1103 bank
->chip
.free
= omap_gpio_free
;
1104 bank
->chip
.get_direction
= omap_gpio_get_direction
;
1105 bank
->chip
.direction_input
= omap_gpio_input
;
1106 bank
->chip
.get
= omap_gpio_get
;
1107 bank
->chip
.direction_output
= omap_gpio_output
;
1108 bank
->chip
.set_debounce
= omap_gpio_debounce
;
1109 bank
->chip
.set
= omap_gpio_set
;
1110 if (bank
->is_mpuio
) {
1111 bank
->chip
.label
= "mpuio";
1112 if (bank
->regs
->wkup_en
)
1113 bank
->chip
.dev
= &omap_mpuio_device
.dev
;
1114 bank
->chip
.base
= OMAP_MPUIO(0);
1116 bank
->chip
.label
= "gpio";
1117 bank
->chip
.base
= gpio
;
1118 gpio
+= bank
->width
;
1120 bank
->chip
.ngpio
= bank
->width
;
1122 ret
= gpiochip_add(&bank
->chip
);
1124 dev_err(bank
->dev
, "Could not register gpio chip %d\n", ret
);
1128 #ifdef CONFIG_ARCH_OMAP1
1130 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1131 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1133 irq_base
= irq_alloc_descs(-1, 0, bank
->width
, 0);
1135 dev_err(bank
->dev
, "Couldn't allocate IRQ numbers\n");
1140 ret
= gpiochip_irqchip_add(&bank
->chip
, &gpio_irq_chip
,
1141 irq_base
, omap_gpio_irq_handler
,
1145 dev_err(bank
->dev
, "Couldn't add irqchip to gpiochip %d\n", ret
);
1146 ret
= gpiochip_remove(&bank
->chip
);
1150 gpiochip_set_chained_irqchip(&bank
->chip
, &gpio_irq_chip
,
1151 bank
->irq
, omap_gpio_irq_handler
);
1153 for (j
= 0; j
< bank
->width
; j
++) {
1154 int irq
= irq_find_mapping(bank
->chip
.irqdomain
, j
);
1155 if (bank
->is_mpuio
) {
1156 omap_mpuio_alloc_gc(bank
, irq
, bank
->width
);
1157 irq_set_chip_and_handler(irq
, NULL
, NULL
);
1158 set_irq_flags(irq
, 0);
1165 static const struct of_device_id omap_gpio_match
[];
1167 static int omap_gpio_probe(struct platform_device
*pdev
)
1169 struct device
*dev
= &pdev
->dev
;
1170 struct device_node
*node
= dev
->of_node
;
1171 const struct of_device_id
*match
;
1172 const struct omap_gpio_platform_data
*pdata
;
1173 struct resource
*res
;
1174 struct gpio_bank
*bank
;
1177 match
= of_match_device(of_match_ptr(omap_gpio_match
), dev
);
1179 pdata
= match
? match
->data
: dev_get_platdata(dev
);
1183 bank
= devm_kzalloc(dev
, sizeof(struct gpio_bank
), GFP_KERNEL
);
1185 dev_err(dev
, "Memory alloc failed\n");
1189 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1190 if (unlikely(!res
)) {
1191 dev_err(dev
, "Invalid IRQ resource\n");
1195 bank
->irq
= res
->start
;
1197 bank
->chip
.dev
= dev
;
1198 bank
->dbck_flag
= pdata
->dbck_flag
;
1199 bank
->stride
= pdata
->bank_stride
;
1200 bank
->width
= pdata
->bank_width
;
1201 bank
->is_mpuio
= pdata
->is_mpuio
;
1202 bank
->non_wakeup_gpios
= pdata
->non_wakeup_gpios
;
1203 bank
->regs
= pdata
->regs
;
1204 #ifdef CONFIG_OF_GPIO
1205 bank
->chip
.of_node
= of_node_get(node
);
1208 if (!of_property_read_bool(node
, "ti,gpio-always-on"))
1209 bank
->loses_context
= true;
1211 bank
->loses_context
= pdata
->loses_context
;
1213 if (bank
->loses_context
)
1214 bank
->get_context_loss_count
=
1215 pdata
->get_context_loss_count
;
1218 if (bank
->regs
->set_dataout
&& bank
->regs
->clr_dataout
)
1219 bank
->set_dataout
= omap_set_gpio_dataout_reg
;
1221 bank
->set_dataout
= omap_set_gpio_dataout_mask
;
1223 spin_lock_init(&bank
->lock
);
1225 /* Static mapping, never released */
1226 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1227 bank
->base
= devm_ioremap_resource(dev
, res
);
1228 if (IS_ERR(bank
->base
)) {
1229 irq_domain_remove(bank
->chip
.irqdomain
);
1230 return PTR_ERR(bank
->base
);
1233 platform_set_drvdata(pdev
, bank
);
1235 pm_runtime_enable(bank
->dev
);
1236 pm_runtime_irq_safe(bank
->dev
);
1237 pm_runtime_get_sync(bank
->dev
);
1240 omap_mpuio_init(bank
);
1242 omap_gpio_mod_init(bank
);
1244 ret
= omap_gpio_chip_init(bank
);
1248 omap_gpio_show_rev(bank
);
1250 pm_runtime_put(bank
->dev
);
1252 list_add_tail(&bank
->node
, &omap_gpio_list
);
1257 #ifdef CONFIG_ARCH_OMAP2PLUS
1259 #if defined(CONFIG_PM_RUNTIME)
1260 static void omap_gpio_restore_context(struct gpio_bank
*bank
);
1262 static int omap_gpio_runtime_suspend(struct device
*dev
)
1264 struct platform_device
*pdev
= to_platform_device(dev
);
1265 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1267 unsigned long flags
;
1268 u32 wake_low
, wake_hi
;
1270 spin_lock_irqsave(&bank
->lock
, flags
);
1273 * Only edges can generate a wakeup event to the PRCM.
1275 * Therefore, ensure any wake-up capable GPIOs have
1276 * edge-detection enabled before going idle to ensure a wakeup
1277 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1280 * The normal values will be restored upon ->runtime_resume()
1281 * by writing back the values saved in bank->context.
1283 wake_low
= bank
->context
.leveldetect0
& bank
->context
.wake_en
;
1285 writel_relaxed(wake_low
| bank
->context
.fallingdetect
,
1286 bank
->base
+ bank
->regs
->fallingdetect
);
1287 wake_hi
= bank
->context
.leveldetect1
& bank
->context
.wake_en
;
1289 writel_relaxed(wake_hi
| bank
->context
.risingdetect
,
1290 bank
->base
+ bank
->regs
->risingdetect
);
1292 if (!bank
->enabled_non_wakeup_gpios
)
1293 goto update_gpio_context_count
;
1295 if (bank
->power_mode
!= OFF_MODE
) {
1296 bank
->power_mode
= 0;
1297 goto update_gpio_context_count
;
1300 * If going to OFF, remove triggering for all
1301 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1302 * generated. See OMAP2420 Errata item 1.101.
1304 bank
->saved_datain
= readl_relaxed(bank
->base
+
1305 bank
->regs
->datain
);
1306 l1
= bank
->context
.fallingdetect
;
1307 l2
= bank
->context
.risingdetect
;
1309 l1
&= ~bank
->enabled_non_wakeup_gpios
;
1310 l2
&= ~bank
->enabled_non_wakeup_gpios
;
1312 writel_relaxed(l1
, bank
->base
+ bank
->regs
->fallingdetect
);
1313 writel_relaxed(l2
, bank
->base
+ bank
->regs
->risingdetect
);
1315 bank
->workaround_enabled
= true;
1317 update_gpio_context_count
:
1318 if (bank
->get_context_loss_count
)
1319 bank
->context_loss_count
=
1320 bank
->get_context_loss_count(bank
->dev
);
1322 omap_gpio_dbck_disable(bank
);
1323 spin_unlock_irqrestore(&bank
->lock
, flags
);
1328 static void omap_gpio_init_context(struct gpio_bank
*p
);
1330 static int omap_gpio_runtime_resume(struct device
*dev
)
1332 struct platform_device
*pdev
= to_platform_device(dev
);
1333 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1334 u32 l
= 0, gen
, gen0
, gen1
;
1335 unsigned long flags
;
1338 spin_lock_irqsave(&bank
->lock
, flags
);
1341 * On the first resume during the probe, the context has not
1342 * been initialised and so initialise it now. Also initialise
1343 * the context loss count.
1345 if (bank
->loses_context
&& !bank
->context_valid
) {
1346 omap_gpio_init_context(bank
);
1348 if (bank
->get_context_loss_count
)
1349 bank
->context_loss_count
=
1350 bank
->get_context_loss_count(bank
->dev
);
1353 omap_gpio_dbck_enable(bank
);
1356 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1357 * GPIOs were set to edge trigger also in order to be able to
1358 * generate a PRCM wakeup. Here we restore the
1359 * pre-runtime_suspend() values for edge triggering.
1361 writel_relaxed(bank
->context
.fallingdetect
,
1362 bank
->base
+ bank
->regs
->fallingdetect
);
1363 writel_relaxed(bank
->context
.risingdetect
,
1364 bank
->base
+ bank
->regs
->risingdetect
);
1366 if (bank
->loses_context
) {
1367 if (!bank
->get_context_loss_count
) {
1368 omap_gpio_restore_context(bank
);
1370 c
= bank
->get_context_loss_count(bank
->dev
);
1371 if (c
!= bank
->context_loss_count
) {
1372 omap_gpio_restore_context(bank
);
1374 spin_unlock_irqrestore(&bank
->lock
, flags
);
1380 if (!bank
->workaround_enabled
) {
1381 spin_unlock_irqrestore(&bank
->lock
, flags
);
1385 l
= readl_relaxed(bank
->base
+ bank
->regs
->datain
);
1388 * Check if any of the non-wakeup interrupt GPIOs have changed
1389 * state. If so, generate an IRQ by software. This is
1390 * horribly racy, but it's the best we can do to work around
1393 l
^= bank
->saved_datain
;
1394 l
&= bank
->enabled_non_wakeup_gpios
;
1397 * No need to generate IRQs for the rising edge for gpio IRQs
1398 * configured with falling edge only; and vice versa.
1400 gen0
= l
& bank
->context
.fallingdetect
;
1401 gen0
&= bank
->saved_datain
;
1403 gen1
= l
& bank
->context
.risingdetect
;
1404 gen1
&= ~(bank
->saved_datain
);
1406 /* FIXME: Consider GPIO IRQs with level detections properly! */
1407 gen
= l
& (~(bank
->context
.fallingdetect
) &
1408 ~(bank
->context
.risingdetect
));
1409 /* Consider all GPIO IRQs needed to be updated */
1415 old0
= readl_relaxed(bank
->base
+ bank
->regs
->leveldetect0
);
1416 old1
= readl_relaxed(bank
->base
+ bank
->regs
->leveldetect1
);
1418 if (!bank
->regs
->irqstatus_raw0
) {
1419 writel_relaxed(old0
| gen
, bank
->base
+
1420 bank
->regs
->leveldetect0
);
1421 writel_relaxed(old1
| gen
, bank
->base
+
1422 bank
->regs
->leveldetect1
);
1425 if (bank
->regs
->irqstatus_raw0
) {
1426 writel_relaxed(old0
| l
, bank
->base
+
1427 bank
->regs
->leveldetect0
);
1428 writel_relaxed(old1
| l
, bank
->base
+
1429 bank
->regs
->leveldetect1
);
1431 writel_relaxed(old0
, bank
->base
+ bank
->regs
->leveldetect0
);
1432 writel_relaxed(old1
, bank
->base
+ bank
->regs
->leveldetect1
);
1435 bank
->workaround_enabled
= false;
1436 spin_unlock_irqrestore(&bank
->lock
, flags
);
1440 #endif /* CONFIG_PM_RUNTIME */
1442 void omap2_gpio_prepare_for_idle(int pwr_mode
)
1444 struct gpio_bank
*bank
;
1446 list_for_each_entry(bank
, &omap_gpio_list
, node
) {
1447 if (!BANK_USED(bank
) || !bank
->loses_context
)
1450 bank
->power_mode
= pwr_mode
;
1452 pm_runtime_put_sync_suspend(bank
->dev
);
1456 void omap2_gpio_resume_after_idle(void)
1458 struct gpio_bank
*bank
;
1460 list_for_each_entry(bank
, &omap_gpio_list
, node
) {
1461 if (!BANK_USED(bank
) || !bank
->loses_context
)
1464 pm_runtime_get_sync(bank
->dev
);
1468 #if defined(CONFIG_PM_RUNTIME)
1469 static void omap_gpio_init_context(struct gpio_bank
*p
)
1471 struct omap_gpio_reg_offs
*regs
= p
->regs
;
1472 void __iomem
*base
= p
->base
;
1474 p
->context
.ctrl
= readl_relaxed(base
+ regs
->ctrl
);
1475 p
->context
.oe
= readl_relaxed(base
+ regs
->direction
);
1476 p
->context
.wake_en
= readl_relaxed(base
+ regs
->wkup_en
);
1477 p
->context
.leveldetect0
= readl_relaxed(base
+ regs
->leveldetect0
);
1478 p
->context
.leveldetect1
= readl_relaxed(base
+ regs
->leveldetect1
);
1479 p
->context
.risingdetect
= readl_relaxed(base
+ regs
->risingdetect
);
1480 p
->context
.fallingdetect
= readl_relaxed(base
+ regs
->fallingdetect
);
1481 p
->context
.irqenable1
= readl_relaxed(base
+ regs
->irqenable
);
1482 p
->context
.irqenable2
= readl_relaxed(base
+ regs
->irqenable2
);
1484 if (regs
->set_dataout
&& p
->regs
->clr_dataout
)
1485 p
->context
.dataout
= readl_relaxed(base
+ regs
->set_dataout
);
1487 p
->context
.dataout
= readl_relaxed(base
+ regs
->dataout
);
1489 p
->context_valid
= true;
1492 static void omap_gpio_restore_context(struct gpio_bank
*bank
)
1494 writel_relaxed(bank
->context
.wake_en
,
1495 bank
->base
+ bank
->regs
->wkup_en
);
1496 writel_relaxed(bank
->context
.ctrl
, bank
->base
+ bank
->regs
->ctrl
);
1497 writel_relaxed(bank
->context
.leveldetect0
,
1498 bank
->base
+ bank
->regs
->leveldetect0
);
1499 writel_relaxed(bank
->context
.leveldetect1
,
1500 bank
->base
+ bank
->regs
->leveldetect1
);
1501 writel_relaxed(bank
->context
.risingdetect
,
1502 bank
->base
+ bank
->regs
->risingdetect
);
1503 writel_relaxed(bank
->context
.fallingdetect
,
1504 bank
->base
+ bank
->regs
->fallingdetect
);
1505 if (bank
->regs
->set_dataout
&& bank
->regs
->clr_dataout
)
1506 writel_relaxed(bank
->context
.dataout
,
1507 bank
->base
+ bank
->regs
->set_dataout
);
1509 writel_relaxed(bank
->context
.dataout
,
1510 bank
->base
+ bank
->regs
->dataout
);
1511 writel_relaxed(bank
->context
.oe
, bank
->base
+ bank
->regs
->direction
);
1513 if (bank
->dbck_enable_mask
) {
1514 writel_relaxed(bank
->context
.debounce
, bank
->base
+
1515 bank
->regs
->debounce
);
1516 writel_relaxed(bank
->context
.debounce_en
,
1517 bank
->base
+ bank
->regs
->debounce_en
);
1520 writel_relaxed(bank
->context
.irqenable1
,
1521 bank
->base
+ bank
->regs
->irqenable
);
1522 writel_relaxed(bank
->context
.irqenable2
,
1523 bank
->base
+ bank
->regs
->irqenable2
);
1525 #endif /* CONFIG_PM_RUNTIME */
1527 #define omap_gpio_runtime_suspend NULL
1528 #define omap_gpio_runtime_resume NULL
1529 static inline void omap_gpio_init_context(struct gpio_bank
*p
) {}
1532 static const struct dev_pm_ops gpio_pm_ops
= {
1533 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend
, omap_gpio_runtime_resume
,
1537 #if defined(CONFIG_OF)
1538 static struct omap_gpio_reg_offs omap2_gpio_regs
= {
1539 .revision
= OMAP24XX_GPIO_REVISION
,
1540 .direction
= OMAP24XX_GPIO_OE
,
1541 .datain
= OMAP24XX_GPIO_DATAIN
,
1542 .dataout
= OMAP24XX_GPIO_DATAOUT
,
1543 .set_dataout
= OMAP24XX_GPIO_SETDATAOUT
,
1544 .clr_dataout
= OMAP24XX_GPIO_CLEARDATAOUT
,
1545 .irqstatus
= OMAP24XX_GPIO_IRQSTATUS1
,
1546 .irqstatus2
= OMAP24XX_GPIO_IRQSTATUS2
,
1547 .irqenable
= OMAP24XX_GPIO_IRQENABLE1
,
1548 .irqenable2
= OMAP24XX_GPIO_IRQENABLE2
,
1549 .set_irqenable
= OMAP24XX_GPIO_SETIRQENABLE1
,
1550 .clr_irqenable
= OMAP24XX_GPIO_CLEARIRQENABLE1
,
1551 .debounce
= OMAP24XX_GPIO_DEBOUNCE_VAL
,
1552 .debounce_en
= OMAP24XX_GPIO_DEBOUNCE_EN
,
1553 .ctrl
= OMAP24XX_GPIO_CTRL
,
1554 .wkup_en
= OMAP24XX_GPIO_WAKE_EN
,
1555 .leveldetect0
= OMAP24XX_GPIO_LEVELDETECT0
,
1556 .leveldetect1
= OMAP24XX_GPIO_LEVELDETECT1
,
1557 .risingdetect
= OMAP24XX_GPIO_RISINGDETECT
,
1558 .fallingdetect
= OMAP24XX_GPIO_FALLINGDETECT
,
1561 static struct omap_gpio_reg_offs omap4_gpio_regs
= {
1562 .revision
= OMAP4_GPIO_REVISION
,
1563 .direction
= OMAP4_GPIO_OE
,
1564 .datain
= OMAP4_GPIO_DATAIN
,
1565 .dataout
= OMAP4_GPIO_DATAOUT
,
1566 .set_dataout
= OMAP4_GPIO_SETDATAOUT
,
1567 .clr_dataout
= OMAP4_GPIO_CLEARDATAOUT
,
1568 .irqstatus
= OMAP4_GPIO_IRQSTATUS0
,
1569 .irqstatus2
= OMAP4_GPIO_IRQSTATUS1
,
1570 .irqenable
= OMAP4_GPIO_IRQSTATUSSET0
,
1571 .irqenable2
= OMAP4_GPIO_IRQSTATUSSET1
,
1572 .set_irqenable
= OMAP4_GPIO_IRQSTATUSSET0
,
1573 .clr_irqenable
= OMAP4_GPIO_IRQSTATUSCLR0
,
1574 .debounce
= OMAP4_GPIO_DEBOUNCINGTIME
,
1575 .debounce_en
= OMAP4_GPIO_DEBOUNCENABLE
,
1576 .ctrl
= OMAP4_GPIO_CTRL
,
1577 .wkup_en
= OMAP4_GPIO_IRQWAKEN0
,
1578 .leveldetect0
= OMAP4_GPIO_LEVELDETECT0
,
1579 .leveldetect1
= OMAP4_GPIO_LEVELDETECT1
,
1580 .risingdetect
= OMAP4_GPIO_RISINGDETECT
,
1581 .fallingdetect
= OMAP4_GPIO_FALLINGDETECT
,
1584 static const struct omap_gpio_platform_data omap2_pdata
= {
1585 .regs
= &omap2_gpio_regs
,
1590 static const struct omap_gpio_platform_data omap3_pdata
= {
1591 .regs
= &omap2_gpio_regs
,
1596 static const struct omap_gpio_platform_data omap4_pdata
= {
1597 .regs
= &omap4_gpio_regs
,
1602 static const struct of_device_id omap_gpio_match
[] = {
1604 .compatible
= "ti,omap4-gpio",
1605 .data
= &omap4_pdata
,
1608 .compatible
= "ti,omap3-gpio",
1609 .data
= &omap3_pdata
,
1612 .compatible
= "ti,omap2-gpio",
1613 .data
= &omap2_pdata
,
1617 MODULE_DEVICE_TABLE(of
, omap_gpio_match
);
1620 static struct platform_driver omap_gpio_driver
= {
1621 .probe
= omap_gpio_probe
,
1623 .name
= "omap_gpio",
1625 .of_match_table
= of_match_ptr(omap_gpio_match
),
1630 * gpio driver register needs to be done before
1631 * machine_init functions access gpio APIs.
1632 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1634 static int __init
omap_gpio_drv_reg(void)
1636 return platform_driver_register(&omap_gpio_driver
);
1638 postcore_initcall(omap_gpio_drv_reg
);