projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
gpio/omap: remove MPUIO handling from _clear_gpio_irqbank()
[deliverable/linux.git] / drivers / gpio / gpio-omap.c
1 /*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/slab.h>
23 #include <linux/pm_runtime.h>
24
25 #include <mach/hardware.h>
26 #include <asm/irq.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
30
31 struct gpio_bank {
32 unsigned long pbase;
33 void __iomem *base;
34 u16 irq;
35 u16 virtual_irq_start;
36 int method;
37 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
38 u32 suspend_wakeup;
39 u32 saved_wakeup;
40 #endif
41 u32 non_wakeup_gpios;
42 u32 enabled_non_wakeup_gpios;
43
44 u32 saved_datain;
45 u32 saved_fallingdetect;
46 u32 saved_risingdetect;
47 u32 level_mask;
48 u32 toggle_mask;
49 spinlock_t lock;
50 struct gpio_chip chip;
51 struct clk *dbck;
52 u32 mod_usage;
53 u32 dbck_enable_mask;
54 struct device *dev;
55 bool dbck_flag;
56 int stride;
57 };
58
59 #ifdef CONFIG_ARCH_OMAP3
60 struct omap3_gpio_regs {
61 u32 irqenable1;
62 u32 irqenable2;
63 u32 wake_en;
64 u32 ctrl;
65 u32 oe;
66 u32 leveldetect0;
67 u32 leveldetect1;
68 u32 risingdetect;
69 u32 fallingdetect;
70 u32 dataout;
71 };
72
73 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
74 #endif
75
76 /*
77 * TODO: Cleanup gpio_bank usage as it is having information
78 * related to all instances of the device
79 */
80 static struct gpio_bank *gpio_bank;
81
82 static int bank_width;
83
84 /* TODO: Analyze removing gpio_bank_count usage from driver code */
85 int gpio_bank_count;
86
87 static inline struct gpio_bank *get_gpio_bank(int gpio)
88 {
89 if (cpu_is_omap15xx()) {
90 if (OMAP_GPIO_IS_MPUIO(gpio))
91 return &gpio_bank[0];
92 return &gpio_bank[1];
93 }
94 if (cpu_is_omap16xx()) {
95 if (OMAP_GPIO_IS_MPUIO(gpio))
96 return &gpio_bank[0];
97 return &gpio_bank[1 + (gpio >> 4)];
98 }
99 if (cpu_is_omap7xx()) {
100 if (OMAP_GPIO_IS_MPUIO(gpio))
101 return &gpio_bank[0];
102 return &gpio_bank[1 + (gpio >> 5)];
103 }
104 if (cpu_is_omap24xx())
105 return &gpio_bank[gpio >> 5];
106 if (cpu_is_omap34xx() || cpu_is_omap44xx())
107 return &gpio_bank[gpio >> 5];
108 BUG();
109 return NULL;
110 }
111
112 static inline int get_gpio_index(int gpio)
113 {
114 if (cpu_is_omap7xx())
115 return gpio & 0x1f;
116 if (cpu_is_omap24xx())
117 return gpio & 0x1f;
118 if (cpu_is_omap34xx() || cpu_is_omap44xx())
119 return gpio & 0x1f;
120 return gpio & 0x0f;
121 }
122
123 static inline int gpio_valid(int gpio)
124 {
125 if (gpio < 0)
126 return -1;
127 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
128 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
129 return -1;
130 return 0;
131 }
132 if (cpu_is_omap15xx() && gpio < 16)
133 return 0;
134 if ((cpu_is_omap16xx()) && gpio < 64)
135 return 0;
136 if (cpu_is_omap7xx() && gpio < 192)
137 return 0;
138 if (cpu_is_omap2420() && gpio < 128)
139 return 0;
140 if (cpu_is_omap2430() && gpio < 160)
141 return 0;
142 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
143 return 0;
144 return -1;
145 }
146
147 static int check_gpio(int gpio)
148 {
149 if (unlikely(gpio_valid(gpio) < 0)) {
150 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
151 dump_stack();
152 return -1;
153 }
154 return 0;
155 }
156
157 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
158 {
159 void __iomem *reg = bank->base;
160 u32 l;
161
162 switch (bank->method) {
163 #ifdef CONFIG_ARCH_OMAP1
164 case METHOD_MPUIO:
165 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
166 break;
167 #endif
168 #ifdef CONFIG_ARCH_OMAP15XX
169 case METHOD_GPIO_1510:
170 reg += OMAP1510_GPIO_DIR_CONTROL;
171 break;
172 #endif
173 #ifdef CONFIG_ARCH_OMAP16XX
174 case METHOD_GPIO_1610:
175 reg += OMAP1610_GPIO_DIRECTION;
176 break;
177 #endif
178 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
179 case METHOD_GPIO_7XX:
180 reg += OMAP7XX_GPIO_DIR_CONTROL;
181 break;
182 #endif
183 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
184 case METHOD_GPIO_24XX:
185 reg += OMAP24XX_GPIO_OE;
186 break;
187 #endif
188 #if defined(CONFIG_ARCH_OMAP4)
189 case METHOD_GPIO_44XX:
190 reg += OMAP4_GPIO_OE;
191 break;
192 #endif
193 default:
194 WARN_ON(1);
195 return;
196 }
197 l = __raw_readl(reg);
198 if (is_input)
199 l |= 1 << gpio;
200 else
201 l &= ~(1 << gpio);
202 __raw_writel(l, reg);
203 }
204
205 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
206 {
207 void __iomem *reg = bank->base;
208 u32 l = 0;
209
210 switch (bank->method) {
211 #ifdef CONFIG_ARCH_OMAP1
212 case METHOD_MPUIO:
213 reg += OMAP_MPUIO_OUTPUT / bank->stride;
214 l = __raw_readl(reg);
215 if (enable)
216 l |= 1 << gpio;
217 else
218 l &= ~(1 << gpio);
219 break;
220 #endif
221 #ifdef CONFIG_ARCH_OMAP15XX
222 case METHOD_GPIO_1510:
223 reg += OMAP1510_GPIO_DATA_OUTPUT;
224 l = __raw_readl(reg);
225 if (enable)
226 l |= 1 << gpio;
227 else
228 l &= ~(1 << gpio);
229 break;
230 #endif
231 #ifdef CONFIG_ARCH_OMAP16XX
232 case METHOD_GPIO_1610:
233 if (enable)
234 reg += OMAP1610_GPIO_SET_DATAOUT;
235 else
236 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
237 l = 1 << gpio;
238 break;
239 #endif
240 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
241 case METHOD_GPIO_7XX:
242 reg += OMAP7XX_GPIO_DATA_OUTPUT;
243 l = __raw_readl(reg);
244 if (enable)
245 l |= 1 << gpio;
246 else
247 l &= ~(1 << gpio);
248 break;
249 #endif
250 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
251 case METHOD_GPIO_24XX:
252 if (enable)
253 reg += OMAP24XX_GPIO_SETDATAOUT;
254 else
255 reg += OMAP24XX_GPIO_CLEARDATAOUT;
256 l = 1 << gpio;
257 break;
258 #endif
259 #ifdef CONFIG_ARCH_OMAP4
260 case METHOD_GPIO_44XX:
261 if (enable)
262 reg += OMAP4_GPIO_SETDATAOUT;
263 else
264 reg += OMAP4_GPIO_CLEARDATAOUT;
265 l = 1 << gpio;
266 break;
267 #endif
268 default:
269 WARN_ON(1);
270 return;
271 }
272 __raw_writel(l, reg);
273 }
274
275 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
276 {
277 void __iomem *reg;
278
279 if (check_gpio(gpio) < 0)
280 return -EINVAL;
281 reg = bank->base;
282 switch (bank->method) {
283 #ifdef CONFIG_ARCH_OMAP1
284 case METHOD_MPUIO:
285 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
286 break;
287 #endif
288 #ifdef CONFIG_ARCH_OMAP15XX
289 case METHOD_GPIO_1510:
290 reg += OMAP1510_GPIO_DATA_INPUT;
291 break;
292 #endif
293 #ifdef CONFIG_ARCH_OMAP16XX
294 case METHOD_GPIO_1610:
295 reg += OMAP1610_GPIO_DATAIN;
296 break;
297 #endif
298 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
299 case METHOD_GPIO_7XX:
300 reg += OMAP7XX_GPIO_DATA_INPUT;
301 break;
302 #endif
303 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
304 case METHOD_GPIO_24XX:
305 reg += OMAP24XX_GPIO_DATAIN;
306 break;
307 #endif
308 #ifdef CONFIG_ARCH_OMAP4
309 case METHOD_GPIO_44XX:
310 reg += OMAP4_GPIO_DATAIN;
311 break;
312 #endif
313 default:
314 return -EINVAL;
315 }
316 return (__raw_readl(reg)
317 & (1 << get_gpio_index(gpio))) != 0;
318 }
319
320 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
321 {
322 void __iomem *reg;
323
324 if (check_gpio(gpio) < 0)
325 return -EINVAL;
326 reg = bank->base;
327
328 switch (bank->method) {
329 #ifdef CONFIG_ARCH_OMAP1
330 case METHOD_MPUIO:
331 reg += OMAP_MPUIO_OUTPUT / bank->stride;
332 break;
333 #endif
334 #ifdef CONFIG_ARCH_OMAP15XX
335 case METHOD_GPIO_1510:
336 reg += OMAP1510_GPIO_DATA_OUTPUT;
337 break;
338 #endif
339 #ifdef CONFIG_ARCH_OMAP16XX
340 case METHOD_GPIO_1610:
341 reg += OMAP1610_GPIO_DATAOUT;
342 break;
343 #endif
344 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
345 case METHOD_GPIO_7XX:
346 reg += OMAP7XX_GPIO_DATA_OUTPUT;
347 break;
348 #endif
349 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
350 case METHOD_GPIO_24XX:
351 reg += OMAP24XX_GPIO_DATAOUT;
352 break;
353 #endif
354 #ifdef CONFIG_ARCH_OMAP4
355 case METHOD_GPIO_44XX:
356 reg += OMAP4_GPIO_DATAOUT;
357 break;
358 #endif
359 default:
360 return -EINVAL;
361 }
362
363 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
364 }
365
366 #define MOD_REG_BIT(reg, bit_mask, set) \
367 do { \
368 int l = __raw_readl(base + reg); \
369 if (set) l |= bit_mask; \
370 else l &= ~bit_mask; \
371 __raw_writel(l, base + reg); \
372 } while(0)
373
374 /**
375 * _set_gpio_debounce - low level gpio debounce time
376 * @bank: the gpio bank we're acting upon
377 * @gpio: the gpio number on this @gpio
378 * @debounce: debounce time to use
379 *
380 * OMAP's debounce time is in 31us steps so we need
381 * to convert and round up to the closest unit.
382 */
383 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
384 unsigned debounce)
385 {
386 void __iomem *reg = bank->base;
387 u32 val;
388 u32 l;
389
390 if (!bank->dbck_flag)
391 return;
392
393 if (debounce < 32)
394 debounce = 0x01;
395 else if (debounce > 7936)
396 debounce = 0xff;
397 else
398 debounce = (debounce / 0x1f) - 1;
399
400 l = 1 << get_gpio_index(gpio);
401
402 if (bank->method == METHOD_GPIO_44XX)
403 reg += OMAP4_GPIO_DEBOUNCINGTIME;
404 else
405 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
406
407 __raw_writel(debounce, reg);
408
409 reg = bank->base;
410 if (bank->method == METHOD_GPIO_44XX)
411 reg += OMAP4_GPIO_DEBOUNCENABLE;
412 else
413 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
414
415 val = __raw_readl(reg);
416
417 if (debounce) {
418 val |= l;
419 clk_enable(bank->dbck);
420 } else {
421 val &= ~l;
422 clk_disable(bank->dbck);
423 }
424 bank->dbck_enable_mask = val;
425
426 __raw_writel(val, reg);
427 }
428
429 #ifdef CONFIG_ARCH_OMAP2PLUS
430 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
431 int trigger)
432 {
433 void __iomem *base = bank->base;
434 u32 gpio_bit = 1 << gpio;
435
436 if (cpu_is_omap44xx()) {
437 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
438 trigger & IRQ_TYPE_LEVEL_LOW);
439 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
440 trigger & IRQ_TYPE_LEVEL_HIGH);
441 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
442 trigger & IRQ_TYPE_EDGE_RISING);
443 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
444 trigger & IRQ_TYPE_EDGE_FALLING);
445 } else {
446 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
447 trigger & IRQ_TYPE_LEVEL_LOW);
448 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
449 trigger & IRQ_TYPE_LEVEL_HIGH);
450 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
451 trigger & IRQ_TYPE_EDGE_RISING);
452 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
453 trigger & IRQ_TYPE_EDGE_FALLING);
454 }
455 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
456 if (cpu_is_omap44xx()) {
457 MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
458 trigger != 0);
459 } else {
460 /*
461 * GPIO wakeup request can only be generated on edge
462 * transitions
463 */
464 if (trigger & IRQ_TYPE_EDGE_BOTH)
465 __raw_writel(1 << gpio, bank->base
466 + OMAP24XX_GPIO_SETWKUENA);
467 else
468 __raw_writel(1 << gpio, bank->base
469 + OMAP24XX_GPIO_CLEARWKUENA);
470 }
471 }
472 /* This part needs to be executed always for OMAP34xx */
473 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
474 /*
475 * Log the edge gpio and manually trigger the IRQ
476 * after resume if the input level changes
477 * to avoid irq lost during PER RET/OFF mode
478 * Applies for omap2 non-wakeup gpio and all omap3 gpios
479 */
480 if (trigger & IRQ_TYPE_EDGE_BOTH)
481 bank->enabled_non_wakeup_gpios |= gpio_bit;
482 else
483 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
484 }
485
486 if (cpu_is_omap44xx()) {
487 bank->level_mask =
488 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
489 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
490 } else {
491 bank->level_mask =
492 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
493 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
494 }
495 }
496 #endif
497
498 #ifdef CONFIG_ARCH_OMAP1
499 /*
500 * This only applies to chips that can't do both rising and falling edge
501 * detection at once. For all other chips, this function is a noop.
502 */
503 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
504 {
505 void __iomem *reg = bank->base;
506 u32 l = 0;
507
508 switch (bank->method) {
509 case METHOD_MPUIO:
510 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
511 break;
512 #ifdef CONFIG_ARCH_OMAP15XX
513 case METHOD_GPIO_1510:
514 reg += OMAP1510_GPIO_INT_CONTROL;
515 break;
516 #endif
517 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
518 case METHOD_GPIO_7XX:
519 reg += OMAP7XX_GPIO_INT_CONTROL;
520 break;
521 #endif
522 default:
523 return;
524 }
525
526 l = __raw_readl(reg);
527 if ((l >> gpio) & 1)
528 l &= ~(1 << gpio);
529 else
530 l |= 1 << gpio;
531
532 __raw_writel(l, reg);
533 }
534 #endif
535
536 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
537 {
538 void __iomem *reg = bank->base;
539 u32 l = 0;
540
541 switch (bank->method) {
542 #ifdef CONFIG_ARCH_OMAP1
543 case METHOD_MPUIO:
544 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
545 l = __raw_readl(reg);
546 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
547 bank->toggle_mask |= 1 << gpio;
548 if (trigger & IRQ_TYPE_EDGE_RISING)
549 l |= 1 << gpio;
550 else if (trigger & IRQ_TYPE_EDGE_FALLING)
551 l &= ~(1 << gpio);
552 else
553 goto bad;
554 break;
555 #endif
556 #ifdef CONFIG_ARCH_OMAP15XX
557 case METHOD_GPIO_1510:
558 reg += OMAP1510_GPIO_INT_CONTROL;
559 l = __raw_readl(reg);
560 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
561 bank->toggle_mask |= 1 << gpio;
562 if (trigger & IRQ_TYPE_EDGE_RISING)
563 l |= 1 << gpio;
564 else if (trigger & IRQ_TYPE_EDGE_FALLING)
565 l &= ~(1 << gpio);
566 else
567 goto bad;
568 break;
569 #endif
570 #ifdef CONFIG_ARCH_OMAP16XX
571 case METHOD_GPIO_1610:
572 if (gpio & 0x08)
573 reg += OMAP1610_GPIO_EDGE_CTRL2;
574 else
575 reg += OMAP1610_GPIO_EDGE_CTRL1;
576 gpio &= 0x07;
577 l = __raw_readl(reg);
578 l &= ~(3 << (gpio << 1));
579 if (trigger & IRQ_TYPE_EDGE_RISING)
580 l |= 2 << (gpio << 1);
581 if (trigger & IRQ_TYPE_EDGE_FALLING)
582 l |= 1 << (gpio << 1);
583 if (trigger)
584 /* Enable wake-up during idle for dynamic tick */
585 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
586 else
587 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
588 break;
589 #endif
590 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
591 case METHOD_GPIO_7XX:
592 reg += OMAP7XX_GPIO_INT_CONTROL;
593 l = __raw_readl(reg);
594 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
595 bank->toggle_mask |= 1 << gpio;
596 if (trigger & IRQ_TYPE_EDGE_RISING)
597 l |= 1 << gpio;
598 else if (trigger & IRQ_TYPE_EDGE_FALLING)
599 l &= ~(1 << gpio);
600 else
601 goto bad;
602 break;
603 #endif
604 #ifdef CONFIG_ARCH_OMAP2PLUS
605 case METHOD_GPIO_24XX:
606 case METHOD_GPIO_44XX:
607 set_24xx_gpio_triggering(bank, gpio, trigger);
608 return 0;
609 #endif
610 default:
611 goto bad;
612 }
613 __raw_writel(l, reg);
614 return 0;
615 bad:
616 return -EINVAL;
617 }
618
619 static int gpio_irq_type(struct irq_data *d, unsigned type)
620 {
621 struct gpio_bank *bank;
622 unsigned gpio;
623 int retval;
624 unsigned long flags;
625
626 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
627 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
628 else
629 gpio = d->irq - IH_GPIO_BASE;
630
631 if (check_gpio(gpio) < 0)
632 return -EINVAL;
633
634 if (type & ~IRQ_TYPE_SENSE_MASK)
635 return -EINVAL;
636
637 /* OMAP1 allows only only edge triggering */
638 if (!cpu_class_is_omap2()
639 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
640 return -EINVAL;
641
642 bank = irq_data_get_irq_chip_data(d);
643 spin_lock_irqsave(&bank->lock, flags);
644 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
645 spin_unlock_irqrestore(&bank->lock, flags);
646
647 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
648 __irq_set_handler_locked(d->irq, handle_level_irq);
649 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
650 __irq_set_handler_locked(d->irq, handle_edge_irq);
651
652 return retval;
653 }
654
655 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
656 {
657 void __iomem *reg = bank->base;
658
659 switch (bank->method) {
660 #ifdef CONFIG_ARCH_OMAP15XX
661 case METHOD_GPIO_1510:
662 reg += OMAP1510_GPIO_INT_STATUS;
663 break;
664 #endif
665 #ifdef CONFIG_ARCH_OMAP16XX
666 case METHOD_GPIO_1610:
667 reg += OMAP1610_GPIO_IRQSTATUS1;
668 break;
669 #endif
670 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
671 case METHOD_GPIO_7XX:
672 reg += OMAP7XX_GPIO_INT_STATUS;
673 break;
674 #endif
675 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
676 case METHOD_GPIO_24XX:
677 reg += OMAP24XX_GPIO_IRQSTATUS1;
678 break;
679 #endif
680 #if defined(CONFIG_ARCH_OMAP4)
681 case METHOD_GPIO_44XX:
682 reg += OMAP4_GPIO_IRQSTATUS0;
683 break;
684 #endif
685 default:
686 WARN_ON(1);
687 return;
688 }
689 __raw_writel(gpio_mask, reg);
690
691 /* Workaround for clearing DSP GPIO interrupts to allow retention */
692 if (cpu_is_omap24xx() || cpu_is_omap34xx())
693 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
694 else if (cpu_is_omap44xx())
695 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
696
697 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx())
698 __raw_writel(gpio_mask, reg);
699
700 /* Flush posted write for the irq status to avoid spurious interrupts */
701 __raw_readl(reg);
702 }
703
704 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
705 {
706 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
707 }
708
709 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
710 {
711 void __iomem *reg = bank->base;
712 int inv = 0;
713 u32 l;
714 u32 mask;
715
716 switch (bank->method) {
717 #ifdef CONFIG_ARCH_OMAP1
718 case METHOD_MPUIO:
719 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
720 mask = 0xffff;
721 inv = 1;
722 break;
723 #endif
724 #ifdef CONFIG_ARCH_OMAP15XX
725 case METHOD_GPIO_1510:
726 reg += OMAP1510_GPIO_INT_MASK;
727 mask = 0xffff;
728 inv = 1;
729 break;
730 #endif
731 #ifdef CONFIG_ARCH_OMAP16XX
732 case METHOD_GPIO_1610:
733 reg += OMAP1610_GPIO_IRQENABLE1;
734 mask = 0xffff;
735 break;
736 #endif
737 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
738 case METHOD_GPIO_7XX:
739 reg += OMAP7XX_GPIO_INT_MASK;
740 mask = 0xffffffff;
741 inv = 1;
742 break;
743 #endif
744 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
745 case METHOD_GPIO_24XX:
746 reg += OMAP24XX_GPIO_IRQENABLE1;
747 mask = 0xffffffff;
748 break;
749 #endif
750 #if defined(CONFIG_ARCH_OMAP4)
751 case METHOD_GPIO_44XX:
752 reg += OMAP4_GPIO_IRQSTATUSSET0;
753 mask = 0xffffffff;
754 break;
755 #endif
756 default:
757 WARN_ON(1);
758 return 0;
759 }
760
761 l = __raw_readl(reg);
762 if (inv)
763 l = ~l;
764 l &= mask;
765 return l;
766 }
767
768 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
769 {
770 void __iomem *reg = bank->base;
771 u32 l;
772
773 switch (bank->method) {
774 #ifdef CONFIG_ARCH_OMAP1
775 case METHOD_MPUIO:
776 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
777 l = __raw_readl(reg);
778 if (enable)
779 l &= ~(gpio_mask);
780 else
781 l |= gpio_mask;
782 break;
783 #endif
784 #ifdef CONFIG_ARCH_OMAP15XX
785 case METHOD_GPIO_1510:
786 reg += OMAP1510_GPIO_INT_MASK;
787 l = __raw_readl(reg);
788 if (enable)
789 l &= ~(gpio_mask);
790 else
791 l |= gpio_mask;
792 break;
793 #endif
794 #ifdef CONFIG_ARCH_OMAP16XX
795 case METHOD_GPIO_1610:
796 if (enable)
797 reg += OMAP1610_GPIO_SET_IRQENABLE1;
798 else
799 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
800 l = gpio_mask;
801 break;
802 #endif
803 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
804 case METHOD_GPIO_7XX:
805 reg += OMAP7XX_GPIO_INT_MASK;
806 l = __raw_readl(reg);
807 if (enable)
808 l &= ~(gpio_mask);
809 else
810 l |= gpio_mask;
811 break;
812 #endif
813 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
814 case METHOD_GPIO_24XX:
815 if (enable)
816 reg += OMAP24XX_GPIO_SETIRQENABLE1;
817 else
818 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
819 l = gpio_mask;
820 break;
821 #endif
822 #ifdef CONFIG_ARCH_OMAP4
823 case METHOD_GPIO_44XX:
824 if (enable)
825 reg += OMAP4_GPIO_IRQSTATUSSET0;
826 else
827 reg += OMAP4_GPIO_IRQSTATUSCLR0;
828 l = gpio_mask;
829 break;
830 #endif
831 default:
832 WARN_ON(1);
833 return;
834 }
835 __raw_writel(l, reg);
836 }
837
838 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
839 {
840 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
841 }
842
843 /*
844 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
845 * 1510 does not seem to have a wake-up register. If JTAG is connected
846 * to the target, system will wake up always on GPIO events. While
847 * system is running all registered GPIO interrupts need to have wake-up
848 * enabled. When system is suspended, only selected GPIO interrupts need
849 * to have wake-up enabled.
850 */
851 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
852 {
853 unsigned long uninitialized_var(flags);
854
855 switch (bank->method) {
856 #ifdef CONFIG_ARCH_OMAP16XX
857 case METHOD_MPUIO:
858 case METHOD_GPIO_1610:
859 spin_lock_irqsave(&bank->lock, flags);
860 if (enable)
861 bank->suspend_wakeup |= (1 << gpio);
862 else
863 bank->suspend_wakeup &= ~(1 << gpio);
864 spin_unlock_irqrestore(&bank->lock, flags);
865 return 0;
866 #endif
867 #ifdef CONFIG_ARCH_OMAP2PLUS
868 case METHOD_GPIO_24XX:
869 case METHOD_GPIO_44XX:
870 if (bank->non_wakeup_gpios & (1 << gpio)) {
871 printk(KERN_ERR "Unable to modify wakeup on "
872 "non-wakeup GPIO%d\n",
873 (bank - gpio_bank) * 32 + gpio);
874 return -EINVAL;
875 }
876 spin_lock_irqsave(&bank->lock, flags);
877 if (enable)
878 bank->suspend_wakeup |= (1 << gpio);
879 else
880 bank->suspend_wakeup &= ~(1 << gpio);
881 spin_unlock_irqrestore(&bank->lock, flags);
882 return 0;
883 #endif
884 default:
885 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
886 bank->method);
887 return -EINVAL;
888 }
889 }
890
891 static void _reset_gpio(struct gpio_bank *bank, int gpio)
892 {
893 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
894 _set_gpio_irqenable(bank, gpio, 0);
895 _clear_gpio_irqstatus(bank, gpio);
896 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
897 }
898
899 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
900 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
901 {
902 unsigned int gpio = d->irq - IH_GPIO_BASE;
903 struct gpio_bank *bank;
904 int retval;
905
906 if (check_gpio(gpio) < 0)
907 return -ENODEV;
908 bank = irq_data_get_irq_chip_data(d);
909 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
910
911 return retval;
912 }
913
914 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
915 {
916 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
917 unsigned long flags;
918
919 spin_lock_irqsave(&bank->lock, flags);
920
921 /* Set trigger to none. You need to enable the desired trigger with
922 * request_irq() or set_irq_type().
923 */
924 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
925
926 #ifdef CONFIG_ARCH_OMAP15XX
927 if (bank->method == METHOD_GPIO_1510) {
928 void __iomem *reg;
929
930 /* Claim the pin for MPU */
931 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
932 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
933 }
934 #endif
935 if (!cpu_class_is_omap1()) {
936 if (!bank->mod_usage) {
937 void __iomem *reg = bank->base;
938 u32 ctrl;
939
940 if (cpu_is_omap24xx() || cpu_is_omap34xx())
941 reg += OMAP24XX_GPIO_CTRL;
942 else if (cpu_is_omap44xx())
943 reg += OMAP4_GPIO_CTRL;
944 ctrl = __raw_readl(reg);
945 /* Module is enabled, clocks are not gated */
946 ctrl &= 0xFFFFFFFE;
947 __raw_writel(ctrl, reg);
948 }
949 bank->mod_usage |= 1 << offset;
950 }
951 spin_unlock_irqrestore(&bank->lock, flags);
952
953 return 0;
954 }
955
956 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
957 {
958 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
959 unsigned long flags;
960
961 spin_lock_irqsave(&bank->lock, flags);
962 #ifdef CONFIG_ARCH_OMAP16XX
963 if (bank->method == METHOD_GPIO_1610) {
964 /* Disable wake-up during idle for dynamic tick */
965 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
966 __raw_writel(1 << offset, reg);
967 }
968 #endif
969 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
970 if (bank->method == METHOD_GPIO_24XX) {
971 /* Disable wake-up during idle for dynamic tick */
972 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
973 __raw_writel(1 << offset, reg);
974 }
975 #endif
976 #ifdef CONFIG_ARCH_OMAP4
977 if (bank->method == METHOD_GPIO_44XX) {
978 /* Disable wake-up during idle for dynamic tick */
979 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
980 __raw_writel(1 << offset, reg);
981 }
982 #endif
983 if (!cpu_class_is_omap1()) {
984 bank->mod_usage &= ~(1 << offset);
985 if (!bank->mod_usage) {
986 void __iomem *reg = bank->base;
987 u32 ctrl;
988
989 if (cpu_is_omap24xx() || cpu_is_omap34xx())
990 reg += OMAP24XX_GPIO_CTRL;
991 else if (cpu_is_omap44xx())
992 reg += OMAP4_GPIO_CTRL;
993 ctrl = __raw_readl(reg);
994 /* Module is disabled, clocks are gated */
995 ctrl |= 1;
996 __raw_writel(ctrl, reg);
997 }
998 }
999 _reset_gpio(bank, bank->chip.base + offset);
1000 spin_unlock_irqrestore(&bank->lock, flags);
1001 }
1002
1003 /*
1004 * We need to unmask the GPIO bank interrupt as soon as possible to
1005 * avoid missing GPIO interrupts for other lines in the bank.
1006 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1007 * in the bank to avoid missing nested interrupts for a GPIO line.
1008 * If we wait to unmask individual GPIO lines in the bank after the
1009 * line's interrupt handler has been run, we may miss some nested
1010 * interrupts.
1011 */
1012 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1013 {
1014 void __iomem *isr_reg = NULL;
1015 u32 isr;
1016 unsigned int gpio_irq, gpio_index;
1017 struct gpio_bank *bank;
1018 u32 retrigger = 0;
1019 int unmasked = 0;
1020 struct irq_chip *chip = irq_desc_get_chip(desc);
1021
1022 chained_irq_enter(chip, desc);
1023
1024 bank = irq_get_handler_data(irq);
1025 #ifdef CONFIG_ARCH_OMAP1
1026 if (bank->method == METHOD_MPUIO)
1027 isr_reg = bank->base +
1028 OMAP_MPUIO_GPIO_INT / bank->stride;
1029 #endif
1030 #ifdef CONFIG_ARCH_OMAP15XX
1031 if (bank->method == METHOD_GPIO_1510)
1032 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1033 #endif
1034 #if defined(CONFIG_ARCH_OMAP16XX)
1035 if (bank->method == METHOD_GPIO_1610)
1036 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1037 #endif
1038 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1039 if (bank->method == METHOD_GPIO_7XX)
1040 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1041 #endif
1042 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1043 if (bank->method == METHOD_GPIO_24XX)
1044 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1045 #endif
1046 #if defined(CONFIG_ARCH_OMAP4)
1047 if (bank->method == METHOD_GPIO_44XX)
1048 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1049 #endif
1050
1051 if (WARN_ON(!isr_reg))
1052 goto exit;
1053
1054 while(1) {
1055 u32 isr_saved, level_mask = 0;
1056 u32 enabled;
1057
1058 enabled = _get_gpio_irqbank_mask(bank);
1059 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1060
1061 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1062 isr &= 0x0000ffff;
1063
1064 if (cpu_class_is_omap2()) {
1065 level_mask = bank->level_mask & enabled;
1066 }
1067
1068 /* clear edge sensitive interrupts before handler(s) are
1069 called so that we don't miss any interrupt occurred while
1070 executing them */
1071 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1072 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1073 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1074
1075 /* if there is only edge sensitive GPIO pin interrupts
1076 configured, we could unmask GPIO bank interrupt immediately */
1077 if (!level_mask && !unmasked) {
1078 unmasked = 1;
1079 chained_irq_exit(chip, desc);
1080 }
1081
1082 isr |= retrigger;
1083 retrigger = 0;
1084 if (!isr)
1085 break;
1086
1087 gpio_irq = bank->virtual_irq_start;
1088 for (; isr != 0; isr >>= 1, gpio_irq++) {
1089 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1090
1091 if (!(isr & 1))
1092 continue;
1093
1094 #ifdef CONFIG_ARCH_OMAP1
1095 /*
1096 * Some chips can't respond to both rising and falling
1097 * at the same time. If this irq was requested with
1098 * both flags, we need to flip the ICR data for the IRQ
1099 * to respond to the IRQ for the opposite direction.
1100 * This will be indicated in the bank toggle_mask.
1101 */
1102 if (bank->toggle_mask & (1 << gpio_index))
1103 _toggle_gpio_edge_triggering(bank, gpio_index);
1104 #endif
1105
1106 generic_handle_irq(gpio_irq);
1107 }
1108 }
1109 /* if bank has any level sensitive GPIO pin interrupt
1110 configured, we must unmask the bank interrupt only after
1111 handler(s) are executed in order to avoid spurious bank
1112 interrupt */
1113 exit:
1114 if (!unmasked)
1115 chained_irq_exit(chip, desc);
1116 }
1117
1118 static void gpio_irq_shutdown(struct irq_data *d)
1119 {
1120 unsigned int gpio = d->irq - IH_GPIO_BASE;
1121 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1122 unsigned long flags;
1123
1124 spin_lock_irqsave(&bank->lock, flags);
1125 _reset_gpio(bank, gpio);
1126 spin_unlock_irqrestore(&bank->lock, flags);
1127 }
1128
1129 static void gpio_ack_irq(struct irq_data *d)
1130 {
1131 unsigned int gpio = d->irq - IH_GPIO_BASE;
1132 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1133
1134 _clear_gpio_irqstatus(bank, gpio);
1135 }
1136
1137 static void gpio_mask_irq(struct irq_data *d)
1138 {
1139 unsigned int gpio = d->irq - IH_GPIO_BASE;
1140 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1141 unsigned long flags;
1142
1143 spin_lock_irqsave(&bank->lock, flags);
1144 _set_gpio_irqenable(bank, gpio, 0);
1145 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1146 spin_unlock_irqrestore(&bank->lock, flags);
1147 }
1148
1149 static void gpio_unmask_irq(struct irq_data *d)
1150 {
1151 unsigned int gpio = d->irq - IH_GPIO_BASE;
1152 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1153 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1154 u32 trigger = irqd_get_trigger_type(d);
1155 unsigned long flags;
1156
1157 spin_lock_irqsave(&bank->lock, flags);
1158 if (trigger)
1159 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1160
1161 /* For level-triggered GPIOs, the clearing must be done after
1162 * the HW source is cleared, thus after the handler has run */
1163 if (bank->level_mask & irq_mask) {
1164 _set_gpio_irqenable(bank, gpio, 0);
1165 _clear_gpio_irqstatus(bank, gpio);
1166 }
1167
1168 _set_gpio_irqenable(bank, gpio, 1);
1169 spin_unlock_irqrestore(&bank->lock, flags);
1170 }
1171
1172 static struct irq_chip gpio_irq_chip = {
1173 .name = "GPIO",
1174 .irq_shutdown = gpio_irq_shutdown,
1175 .irq_ack = gpio_ack_irq,
1176 .irq_mask = gpio_mask_irq,
1177 .irq_unmask = gpio_unmask_irq,
1178 .irq_set_type = gpio_irq_type,
1179 .irq_set_wake = gpio_wake_enable,
1180 };
1181
1182 /*---------------------------------------------------------------------*/
1183
1184 #ifdef CONFIG_ARCH_OMAP1
1185
1186 /* MPUIO uses the always-on 32k clock */
1187
1188 static void mpuio_ack_irq(struct irq_data *d)
1189 {
1190 /* The ISR is reset automatically, so do nothing here. */
1191 }
1192
1193 static void mpuio_mask_irq(struct irq_data *d)
1194 {
1195 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1196 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1197
1198 _set_gpio_irqenable(bank, gpio, 0);
1199 }
1200
1201 static void mpuio_unmask_irq(struct irq_data *d)
1202 {
1203 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1204 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1205
1206 _set_gpio_irqenable(bank, gpio, 1);
1207 }
1208
1209 static struct irq_chip mpuio_irq_chip = {
1210 .name = "MPUIO",
1211 .irq_ack = mpuio_ack_irq,
1212 .irq_mask = mpuio_mask_irq,
1213 .irq_unmask = mpuio_unmask_irq,
1214 .irq_set_type = gpio_irq_type,
1215 #ifdef CONFIG_ARCH_OMAP16XX
1216 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1217 .irq_set_wake = gpio_wake_enable,
1218 #endif
1219 };
1220
1221
1222 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1223
1224
1225 #ifdef CONFIG_ARCH_OMAP16XX
1226
1227 #include <linux/platform_device.h>
1228
1229 static int omap_mpuio_suspend_noirq(struct device *dev)
1230 {
1231 struct platform_device *pdev = to_platform_device(dev);
1232 struct gpio_bank *bank = platform_get_drvdata(pdev);
1233 void __iomem *mask_reg = bank->base +
1234 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1235 unsigned long flags;
1236
1237 spin_lock_irqsave(&bank->lock, flags);
1238 bank->saved_wakeup = __raw_readl(mask_reg);
1239 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1240 spin_unlock_irqrestore(&bank->lock, flags);
1241
1242 return 0;
1243 }
1244
1245 static int omap_mpuio_resume_noirq(struct device *dev)
1246 {
1247 struct platform_device *pdev = to_platform_device(dev);
1248 struct gpio_bank *bank = platform_get_drvdata(pdev);
1249 void __iomem *mask_reg = bank->base +
1250 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1251 unsigned long flags;
1252
1253 spin_lock_irqsave(&bank->lock, flags);
1254 __raw_writel(bank->saved_wakeup, mask_reg);
1255 spin_unlock_irqrestore(&bank->lock, flags);
1256
1257 return 0;
1258 }
1259
1260 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1261 .suspend_noirq = omap_mpuio_suspend_noirq,
1262 .resume_noirq = omap_mpuio_resume_noirq,
1263 };
1264
1265 /* use platform_driver for this. */
1266 static struct platform_driver omap_mpuio_driver = {
1267 .driver = {
1268 .name = "mpuio",
1269 .pm = &omap_mpuio_dev_pm_ops,
1270 },
1271 };
1272
1273 static struct platform_device omap_mpuio_device = {
1274 .name = "mpuio",
1275 .id = -1,
1276 .dev = {
1277 .driver = &omap_mpuio_driver.driver,
1278 }
1279 /* could list the /proc/iomem resources */
1280 };
1281
1282 static inline void mpuio_init(void)
1283 {
1284 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1285 platform_set_drvdata(&omap_mpuio_device, bank);
1286
1287 if (platform_driver_register(&omap_mpuio_driver) == 0)
1288 (void) platform_device_register(&omap_mpuio_device);
1289 }
1290
1291 #else
1292 static inline void mpuio_init(void) {}
1293 #endif /* 16xx */
1294
1295 #else
1296
1297 extern struct irq_chip mpuio_irq_chip;
1298
1299 #define bank_is_mpuio(bank) 0
1300 static inline void mpuio_init(void) {}
1301
1302 #endif
1303
1304 /*---------------------------------------------------------------------*/
1305
1306 /* REVISIT these are stupid implementations! replace by ones that
1307 * don't switch on METHOD_* and which mostly avoid spinlocks
1308 */
1309
1310 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1311 {
1312 struct gpio_bank *bank;
1313 unsigned long flags;
1314
1315 bank = container_of(chip, struct gpio_bank, chip);
1316 spin_lock_irqsave(&bank->lock, flags);
1317 _set_gpio_direction(bank, offset, 1);
1318 spin_unlock_irqrestore(&bank->lock, flags);
1319 return 0;
1320 }
1321
1322 static int gpio_is_input(struct gpio_bank *bank, int mask)
1323 {
1324 void __iomem *reg = bank->base;
1325
1326 switch (bank->method) {
1327 case METHOD_MPUIO:
1328 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
1329 break;
1330 case METHOD_GPIO_1510:
1331 reg += OMAP1510_GPIO_DIR_CONTROL;
1332 break;
1333 case METHOD_GPIO_1610:
1334 reg += OMAP1610_GPIO_DIRECTION;
1335 break;
1336 case METHOD_GPIO_7XX:
1337 reg += OMAP7XX_GPIO_DIR_CONTROL;
1338 break;
1339 case METHOD_GPIO_24XX:
1340 reg += OMAP24XX_GPIO_OE;
1341 break;
1342 case METHOD_GPIO_44XX:
1343 reg += OMAP4_GPIO_OE;
1344 break;
1345 default:
1346 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1347 return -EINVAL;
1348 }
1349 return __raw_readl(reg) & mask;
1350 }
1351
1352 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1353 {
1354 struct gpio_bank *bank;
1355 void __iomem *reg;
1356 int gpio;
1357 u32 mask;
1358
1359 gpio = chip->base + offset;
1360 bank = get_gpio_bank(gpio);
1361 reg = bank->base;
1362 mask = 1 << get_gpio_index(gpio);
1363
1364 if (gpio_is_input(bank, mask))
1365 return _get_gpio_datain(bank, gpio);
1366 else
1367 return _get_gpio_dataout(bank, gpio);
1368 }
1369
1370 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1371 {
1372 struct gpio_bank *bank;
1373 unsigned long flags;
1374
1375 bank = container_of(chip, struct gpio_bank, chip);
1376 spin_lock_irqsave(&bank->lock, flags);
1377 _set_gpio_dataout(bank, offset, value);
1378 _set_gpio_direction(bank, offset, 0);
1379 spin_unlock_irqrestore(&bank->lock, flags);
1380 return 0;
1381 }
1382
1383 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1384 unsigned debounce)
1385 {
1386 struct gpio_bank *bank;
1387 unsigned long flags;
1388
1389 bank = container_of(chip, struct gpio_bank, chip);
1390
1391 if (!bank->dbck) {
1392 bank->dbck = clk_get(bank->dev, "dbclk");
1393 if (IS_ERR(bank->dbck))
1394 dev_err(bank->dev, "Could not get gpio dbck\n");
1395 }
1396
1397 spin_lock_irqsave(&bank->lock, flags);
1398 _set_gpio_debounce(bank, offset, debounce);
1399 spin_unlock_irqrestore(&bank->lock, flags);
1400
1401 return 0;
1402 }
1403
1404 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1405 {
1406 struct gpio_bank *bank;
1407 unsigned long flags;
1408
1409 bank = container_of(chip, struct gpio_bank, chip);
1410 spin_lock_irqsave(&bank->lock, flags);
1411 _set_gpio_dataout(bank, offset, value);
1412 spin_unlock_irqrestore(&bank->lock, flags);
1413 }
1414
1415 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1416 {
1417 struct gpio_bank *bank;
1418
1419 bank = container_of(chip, struct gpio_bank, chip);
1420 return bank->virtual_irq_start + offset;
1421 }
1422
1423 /*---------------------------------------------------------------------*/
1424
1425 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1426 {
1427 u32 rev;
1428
1429 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1430 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
1431 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1432 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
1433 else if (cpu_is_omap44xx())
1434 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
1435 else
1436 return;
1437
1438 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1439 (rev >> 4) & 0x0f, rev & 0x0f);
1440 }
1441
1442 /* This lock class tells lockdep that GPIO irqs are in a different
1443 * category than their parents, so it won't report false recursion.
1444 */
1445 static struct lock_class_key gpio_lock_class;
1446
1447 static inline int init_gpio_info(struct platform_device *pdev)
1448 {
1449 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1450 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1451 GFP_KERNEL);
1452 if (!gpio_bank) {
1453 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1454 return -ENOMEM;
1455 }
1456 return 0;
1457 }
1458
1459 /* TODO: Cleanup cpu_is_* checks */
1460 static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1461 {
1462 if (cpu_class_is_omap2()) {
1463 if (cpu_is_omap44xx()) {
1464 __raw_writel(0xffffffff, bank->base +
1465 OMAP4_GPIO_IRQSTATUSCLR0);
1466 __raw_writel(0x00000000, bank->base +
1467 OMAP4_GPIO_DEBOUNCENABLE);
1468 /* Initialize interface clk ungated, module enabled */
1469 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1470 } else if (cpu_is_omap34xx()) {
1471 __raw_writel(0x00000000, bank->base +
1472 OMAP24XX_GPIO_IRQENABLE1);
1473 __raw_writel(0xffffffff, bank->base +
1474 OMAP24XX_GPIO_IRQSTATUS1);
1475 __raw_writel(0x00000000, bank->base +
1476 OMAP24XX_GPIO_DEBOUNCE_EN);
1477
1478 /* Initialize interface clk ungated, module enabled */
1479 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1480 } else if (cpu_is_omap24xx()) {
1481 static const u32 non_wakeup_gpios[] = {
1482 0xe203ffc0, 0x08700040
1483 };
1484 if (id < ARRAY_SIZE(non_wakeup_gpios))
1485 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1486 }
1487 } else if (cpu_class_is_omap1()) {
1488 if (bank_is_mpuio(bank))
1489 __raw_writew(0xffff, bank->base +
1490 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1491 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1492 __raw_writew(0xffff, bank->base
1493 + OMAP1510_GPIO_INT_MASK);
1494 __raw_writew(0x0000, bank->base
1495 + OMAP1510_GPIO_INT_STATUS);
1496 }
1497 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1498 __raw_writew(0x0000, bank->base
1499 + OMAP1610_GPIO_IRQENABLE1);
1500 __raw_writew(0xffff, bank->base
1501 + OMAP1610_GPIO_IRQSTATUS1);
1502 __raw_writew(0x0014, bank->base
1503 + OMAP1610_GPIO_SYSCONFIG);
1504
1505 /*
1506 * Enable system clock for GPIO module.
1507 * The CAM_CLK_CTRL *is* really the right place.
1508 */
1509 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1510 ULPD_CAM_CLK_CTRL);
1511 }
1512 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1513 __raw_writel(0xffffffff, bank->base
1514 + OMAP7XX_GPIO_INT_MASK);
1515 __raw_writel(0x00000000, bank->base
1516 + OMAP7XX_GPIO_INT_STATUS);
1517 }
1518 }
1519 }
1520
1521 static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1522 {
1523 int j;
1524 static int gpio;
1525
1526 bank->mod_usage = 0;
1527 /*
1528 * REVISIT eventually switch from OMAP-specific gpio structs
1529 * over to the generic ones
1530 */
1531 bank->chip.request = omap_gpio_request;
1532 bank->chip.free = omap_gpio_free;
1533 bank->chip.direction_input = gpio_input;
1534 bank->chip.get = gpio_get;
1535 bank->chip.direction_output = gpio_output;
1536 bank->chip.set_debounce = gpio_debounce;
1537 bank->chip.set = gpio_set;
1538 bank->chip.to_irq = gpio_2irq;
1539 if (bank_is_mpuio(bank)) {
1540 bank->chip.label = "mpuio";
1541 #ifdef CONFIG_ARCH_OMAP16XX
1542 bank->chip.dev = &omap_mpuio_device.dev;
1543 #endif
1544 bank->chip.base = OMAP_MPUIO(0);
1545 } else {
1546 bank->chip.label = "gpio";
1547 bank->chip.base = gpio;
1548 gpio += bank_width;
1549 }
1550 bank->chip.ngpio = bank_width;
1551
1552 gpiochip_add(&bank->chip);
1553
1554 for (j = bank->virtual_irq_start;
1555 j < bank->virtual_irq_start + bank_width; j++) {
1556 irq_set_lockdep_class(j, &gpio_lock_class);
1557 irq_set_chip_data(j, bank);
1558 if (bank_is_mpuio(bank))
1559 irq_set_chip(j, &mpuio_irq_chip);
1560 else
1561 irq_set_chip(j, &gpio_irq_chip);
1562 irq_set_handler(j, handle_simple_irq);
1563 set_irq_flags(j, IRQF_VALID);
1564 }
1565 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1566 irq_set_handler_data(bank->irq, bank);
1567 }
1568
1569 static int __devinit omap_gpio_probe(struct platform_device *pdev)
1570 {
1571 static int gpio_init_done;
1572 struct omap_gpio_platform_data *pdata;
1573 struct resource *res;
1574 int id;
1575 struct gpio_bank *bank;
1576
1577 if (!pdev->dev.platform_data)
1578 return -EINVAL;
1579
1580 pdata = pdev->dev.platform_data;
1581
1582 if (!gpio_init_done) {
1583 int ret;
1584
1585 ret = init_gpio_info(pdev);
1586 if (ret)
1587 return ret;
1588 }
1589
1590 id = pdev->id;
1591 bank = &gpio_bank[id];
1592
1593 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1594 if (unlikely(!res)) {
1595 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1596 return -ENODEV;
1597 }
1598
1599 bank->irq = res->start;
1600 bank->virtual_irq_start = pdata->virtual_irq_start;
1601 bank->method = pdata->bank_type;
1602 bank->dev = &pdev->dev;
1603 bank->dbck_flag = pdata->dbck_flag;
1604 bank->stride = pdata->bank_stride;
1605 bank_width = pdata->bank_width;
1606
1607 spin_lock_init(&bank->lock);
1608
1609 /* Static mapping, never released */
1610 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1611 if (unlikely(!res)) {
1612 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1613 return -ENODEV;
1614 }
1615
1616 bank->base = ioremap(res->start, resource_size(res));
1617 if (!bank->base) {
1618 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1619 return -ENOMEM;
1620 }
1621
1622 pm_runtime_enable(bank->dev);
1623 pm_runtime_get_sync(bank->dev);
1624
1625 omap_gpio_mod_init(bank, id);
1626 omap_gpio_chip_init(bank);
1627 omap_gpio_show_rev(bank);
1628
1629 if (!gpio_init_done)
1630 gpio_init_done = 1;
1631
1632 return 0;
1633 }
1634
1635 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1636 static int omap_gpio_suspend(void)
1637 {
1638 int i;
1639
1640 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1641 return 0;
1642
1643 for (i = 0; i < gpio_bank_count; i++) {
1644 struct gpio_bank *bank = &gpio_bank[i];
1645 void __iomem *wake_status;
1646 void __iomem *wake_clear;
1647 void __iomem *wake_set;
1648 unsigned long flags;
1649
1650 switch (bank->method) {
1651 #ifdef CONFIG_ARCH_OMAP16XX
1652 case METHOD_GPIO_1610:
1653 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1654 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1655 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1656 break;
1657 #endif
1658 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1659 case METHOD_GPIO_24XX:
1660 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1661 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1662 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1663 break;
1664 #endif
1665 #ifdef CONFIG_ARCH_OMAP4
1666 case METHOD_GPIO_44XX:
1667 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1668 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1669 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1670 break;
1671 #endif
1672 default:
1673 continue;
1674 }
1675
1676 spin_lock_irqsave(&bank->lock, flags);
1677 bank->saved_wakeup = __raw_readl(wake_status);
1678 __raw_writel(0xffffffff, wake_clear);
1679 __raw_writel(bank->suspend_wakeup, wake_set);
1680 spin_unlock_irqrestore(&bank->lock, flags);
1681 }
1682
1683 return 0;
1684 }
1685
1686 static void omap_gpio_resume(void)
1687 {
1688 int i;
1689
1690 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1691 return;
1692
1693 for (i = 0; i < gpio_bank_count; i++) {
1694 struct gpio_bank *bank = &gpio_bank[i];
1695 void __iomem *wake_clear;
1696 void __iomem *wake_set;
1697 unsigned long flags;
1698
1699 switch (bank->method) {
1700 #ifdef CONFIG_ARCH_OMAP16XX
1701 case METHOD_GPIO_1610:
1702 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1703 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1704 break;
1705 #endif
1706 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1707 case METHOD_GPIO_24XX:
1708 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1709 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1710 break;
1711 #endif
1712 #ifdef CONFIG_ARCH_OMAP4
1713 case METHOD_GPIO_44XX:
1714 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1715 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1716 break;
1717 #endif
1718 default:
1719 continue;
1720 }
1721
1722 spin_lock_irqsave(&bank->lock, flags);
1723 __raw_writel(0xffffffff, wake_clear);
1724 __raw_writel(bank->saved_wakeup, wake_set);
1725 spin_unlock_irqrestore(&bank->lock, flags);
1726 }
1727 }
1728
1729 static struct syscore_ops omap_gpio_syscore_ops = {
1730 .suspend = omap_gpio_suspend,
1731 .resume = omap_gpio_resume,
1732 };
1733
1734 #endif
1735
1736 #ifdef CONFIG_ARCH_OMAP2PLUS
1737
1738 static int workaround_enabled;
1739
1740 void omap2_gpio_prepare_for_idle(int off_mode)
1741 {
1742 int i, c = 0;
1743 int min = 0;
1744
1745 if (cpu_is_omap34xx())
1746 min = 1;
1747
1748 for (i = min; i < gpio_bank_count; i++) {
1749 struct gpio_bank *bank = &gpio_bank[i];
1750 u32 l1 = 0, l2 = 0;
1751 int j;
1752
1753 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1754 clk_disable(bank->dbck);
1755
1756 if (!off_mode)
1757 continue;
1758
1759 /* If going to OFF, remove triggering for all
1760 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1761 * generated. See OMAP2420 Errata item 1.101. */
1762 if (!(bank->enabled_non_wakeup_gpios))
1763 continue;
1764
1765 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1766 bank->saved_datain = __raw_readl(bank->base +
1767 OMAP24XX_GPIO_DATAIN);
1768 l1 = __raw_readl(bank->base +
1769 OMAP24XX_GPIO_FALLINGDETECT);
1770 l2 = __raw_readl(bank->base +
1771 OMAP24XX_GPIO_RISINGDETECT);
1772 }
1773
1774 if (cpu_is_omap44xx()) {
1775 bank->saved_datain = __raw_readl(bank->base +
1776 OMAP4_GPIO_DATAIN);
1777 l1 = __raw_readl(bank->base +
1778 OMAP4_GPIO_FALLINGDETECT);
1779 l2 = __raw_readl(bank->base +
1780 OMAP4_GPIO_RISINGDETECT);
1781 }
1782
1783 bank->saved_fallingdetect = l1;
1784 bank->saved_risingdetect = l2;
1785 l1 &= ~bank->enabled_non_wakeup_gpios;
1786 l2 &= ~bank->enabled_non_wakeup_gpios;
1787
1788 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1789 __raw_writel(l1, bank->base +
1790 OMAP24XX_GPIO_FALLINGDETECT);
1791 __raw_writel(l2, bank->base +
1792 OMAP24XX_GPIO_RISINGDETECT);
1793 }
1794
1795 if (cpu_is_omap44xx()) {
1796 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1797 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1798 }
1799
1800 c++;
1801 }
1802 if (!c) {
1803 workaround_enabled = 0;
1804 return;
1805 }
1806 workaround_enabled = 1;
1807 }
1808
1809 void omap2_gpio_resume_after_idle(void)
1810 {
1811 int i;
1812 int min = 0;
1813
1814 if (cpu_is_omap34xx())
1815 min = 1;
1816 for (i = min; i < gpio_bank_count; i++) {
1817 struct gpio_bank *bank = &gpio_bank[i];
1818 u32 l = 0, gen, gen0, gen1;
1819 int j;
1820
1821 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1822 clk_enable(bank->dbck);
1823
1824 if (!workaround_enabled)
1825 continue;
1826
1827 if (!(bank->enabled_non_wakeup_gpios))
1828 continue;
1829
1830 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1831 __raw_writel(bank->saved_fallingdetect,
1832 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1833 __raw_writel(bank->saved_risingdetect,
1834 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1835 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1836 }
1837
1838 if (cpu_is_omap44xx()) {
1839 __raw_writel(bank->saved_fallingdetect,
1840 bank->base + OMAP4_GPIO_FALLINGDETECT);
1841 __raw_writel(bank->saved_risingdetect,
1842 bank->base + OMAP4_GPIO_RISINGDETECT);
1843 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1844 }
1845
1846 /* Check if any of the non-wakeup interrupt GPIOs have changed
1847 * state. If so, generate an IRQ by software. This is
1848 * horribly racy, but it's the best we can do to work around
1849 * this silicon bug. */
1850 l ^= bank->saved_datain;
1851 l &= bank->enabled_non_wakeup_gpios;
1852
1853 /*
1854 * No need to generate IRQs for the rising edge for gpio IRQs
1855 * configured with falling edge only; and vice versa.
1856 */
1857 gen0 = l & bank->saved_fallingdetect;
1858 gen0 &= bank->saved_datain;
1859
1860 gen1 = l & bank->saved_risingdetect;
1861 gen1 &= ~(bank->saved_datain);
1862
1863 /* FIXME: Consider GPIO IRQs with level detections properly! */
1864 gen = l & (~(bank->saved_fallingdetect) &
1865 ~(bank->saved_risingdetect));
1866 /* Consider all GPIO IRQs needed to be updated */
1867 gen |= gen0 | gen1;
1868
1869 if (gen) {
1870 u32 old0, old1;
1871
1872 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1873 old0 = __raw_readl(bank->base +
1874 OMAP24XX_GPIO_LEVELDETECT0);
1875 old1 = __raw_readl(bank->base +
1876 OMAP24XX_GPIO_LEVELDETECT1);
1877 __raw_writel(old0 | gen, bank->base +
1878 OMAP24XX_GPIO_LEVELDETECT0);
1879 __raw_writel(old1 | gen, bank->base +
1880 OMAP24XX_GPIO_LEVELDETECT1);
1881 __raw_writel(old0, bank->base +
1882 OMAP24XX_GPIO_LEVELDETECT0);
1883 __raw_writel(old1, bank->base +
1884 OMAP24XX_GPIO_LEVELDETECT1);
1885 }
1886
1887 if (cpu_is_omap44xx()) {
1888 old0 = __raw_readl(bank->base +
1889 OMAP4_GPIO_LEVELDETECT0);
1890 old1 = __raw_readl(bank->base +
1891 OMAP4_GPIO_LEVELDETECT1);
1892 __raw_writel(old0 | l, bank->base +
1893 OMAP4_GPIO_LEVELDETECT0);
1894 __raw_writel(old1 | l, bank->base +
1895 OMAP4_GPIO_LEVELDETECT1);
1896 __raw_writel(old0, bank->base +
1897 OMAP4_GPIO_LEVELDETECT0);
1898 __raw_writel(old1, bank->base +
1899 OMAP4_GPIO_LEVELDETECT1);
1900 }
1901 }
1902 }
1903
1904 }
1905
1906 #endif
1907
1908 #ifdef CONFIG_ARCH_OMAP3
1909 /* save the registers of bank 2-6 */
1910 void omap_gpio_save_context(void)
1911 {
1912 int i;
1913
1914 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1915 for (i = 1; i < gpio_bank_count; i++) {
1916 struct gpio_bank *bank = &gpio_bank[i];
1917 gpio_context[i].irqenable1 =
1918 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1919 gpio_context[i].irqenable2 =
1920 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1921 gpio_context[i].wake_en =
1922 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1923 gpio_context[i].ctrl =
1924 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1925 gpio_context[i].oe =
1926 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1927 gpio_context[i].leveldetect0 =
1928 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1929 gpio_context[i].leveldetect1 =
1930 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1931 gpio_context[i].risingdetect =
1932 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1933 gpio_context[i].fallingdetect =
1934 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1935 gpio_context[i].dataout =
1936 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
1937 }
1938 }
1939
1940 /* restore the required registers of bank 2-6 */
1941 void omap_gpio_restore_context(void)
1942 {
1943 int i;
1944
1945 for (i = 1; i < gpio_bank_count; i++) {
1946 struct gpio_bank *bank = &gpio_bank[i];
1947 __raw_writel(gpio_context[i].irqenable1,
1948 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1949 __raw_writel(gpio_context[i].irqenable2,
1950 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1951 __raw_writel(gpio_context[i].wake_en,
1952 bank->base + OMAP24XX_GPIO_WAKE_EN);
1953 __raw_writel(gpio_context[i].ctrl,
1954 bank->base + OMAP24XX_GPIO_CTRL);
1955 __raw_writel(gpio_context[i].oe,
1956 bank->base + OMAP24XX_GPIO_OE);
1957 __raw_writel(gpio_context[i].leveldetect0,
1958 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1959 __raw_writel(gpio_context[i].leveldetect1,
1960 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1961 __raw_writel(gpio_context[i].risingdetect,
1962 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1963 __raw_writel(gpio_context[i].fallingdetect,
1964 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1965 __raw_writel(gpio_context[i].dataout,
1966 bank->base + OMAP24XX_GPIO_DATAOUT);
1967 }
1968 }
1969 #endif
1970
1971 static struct platform_driver omap_gpio_driver = {
1972 .probe = omap_gpio_probe,
1973 .driver = {
1974 .name = "omap_gpio",
1975 },
1976 };
1977
1978 /*
1979 * gpio driver register needs to be done before
1980 * machine_init functions access gpio APIs.
1981 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1982 */
1983 static int __init omap_gpio_drv_reg(void)
1984 {
1985 return platform_driver_register(&omap_gpio_driver);
1986 }
1987 postcore_initcall(omap_gpio_drv_reg);
1988
1989 static int __init omap_gpio_sysinit(void)
1990 {
1991 mpuio_init();
1992
1993 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1994 if (cpu_is_omap16xx() || cpu_class_is_omap2())
1995 register_syscore_ops(&omap_gpio_syscore_ops);
1996 #endif
1997
1998 return 0;
1999 }
2000
2001 arch_initcall(omap_gpio_sysinit);
Linux kernel - Deliverables
This page took 0.166004 seconds and 6 git commands to generate.