2 * Support functions for OMAP GPIO
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
26 #include <linux/of_device.h>
27 #include <linux/gpio.h>
28 #include <linux/bitops.h>
29 #include <linux/platform_data/gpio-omap.h>
32 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
34 static LIST_HEAD(omap_gpio_list
);
52 struct list_head node
;
56 u32 enabled_non_wakeup_gpios
;
57 struct gpio_regs context
;
62 struct gpio_chip chip
;
75 int context_loss_count
;
77 bool workaround_enabled
;
79 void (*set_dataout
)(struct gpio_bank
*bank
, unsigned gpio
, int enable
);
80 int (*get_context_loss_count
)(struct device
*dev
);
82 struct omap_gpio_reg_offs
*regs
;
85 #define GPIO_MOD_CTRL_BIT BIT(0)
87 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
88 #define LINE_USED(line, offset) (line & (BIT(offset)))
90 static void omap_gpio_unmask_irq(struct irq_data
*d
);
92 static inline struct gpio_bank
*omap_irq_data_get_bank(struct irq_data
*d
)
94 struct gpio_chip
*chip
= irq_data_get_irq_chip_data(d
);
95 return container_of(chip
, struct gpio_bank
, chip
);
98 static void omap_set_gpio_direction(struct gpio_bank
*bank
, int gpio
,
101 void __iomem
*reg
= bank
->base
;
104 reg
+= bank
->regs
->direction
;
105 l
= readl_relaxed(reg
);
110 writel_relaxed(l
, reg
);
111 bank
->context
.oe
= l
;
115 /* set data out value using dedicate set/clear register */
116 static void omap_set_gpio_dataout_reg(struct gpio_bank
*bank
, unsigned offset
,
119 void __iomem
*reg
= bank
->base
;
123 reg
+= bank
->regs
->set_dataout
;
124 bank
->context
.dataout
|= l
;
126 reg
+= bank
->regs
->clr_dataout
;
127 bank
->context
.dataout
&= ~l
;
130 writel_relaxed(l
, reg
);
133 /* set data out value using mask register */
134 static void omap_set_gpio_dataout_mask(struct gpio_bank
*bank
, unsigned offset
,
137 void __iomem
*reg
= bank
->base
+ bank
->regs
->dataout
;
138 u32 gpio_bit
= BIT(offset
);
141 l
= readl_relaxed(reg
);
146 writel_relaxed(l
, reg
);
147 bank
->context
.dataout
= l
;
150 static int omap_get_gpio_datain(struct gpio_bank
*bank
, int offset
)
152 void __iomem
*reg
= bank
->base
+ bank
->regs
->datain
;
154 return (readl_relaxed(reg
) & (BIT(offset
))) != 0;
157 static int omap_get_gpio_dataout(struct gpio_bank
*bank
, int offset
)
159 void __iomem
*reg
= bank
->base
+ bank
->regs
->dataout
;
161 return (readl_relaxed(reg
) & (BIT(offset
))) != 0;
164 static inline void omap_gpio_rmw(void __iomem
*base
, u32 reg
, u32 mask
, bool set
)
166 int l
= readl_relaxed(base
+ reg
);
173 writel_relaxed(l
, base
+ reg
);
176 static inline void omap_gpio_dbck_enable(struct gpio_bank
*bank
)
178 if (bank
->dbck_enable_mask
&& !bank
->dbck_enabled
) {
179 clk_prepare_enable(bank
->dbck
);
180 bank
->dbck_enabled
= true;
182 writel_relaxed(bank
->dbck_enable_mask
,
183 bank
->base
+ bank
->regs
->debounce_en
);
187 static inline void omap_gpio_dbck_disable(struct gpio_bank
*bank
)
189 if (bank
->dbck_enable_mask
&& bank
->dbck_enabled
) {
191 * Disable debounce before cutting it's clock. If debounce is
192 * enabled but the clock is not, GPIO module seems to be unable
193 * to detect events and generate interrupts at least on OMAP3.
195 writel_relaxed(0, bank
->base
+ bank
->regs
->debounce_en
);
197 clk_disable_unprepare(bank
->dbck
);
198 bank
->dbck_enabled
= false;
203 * omap2_set_gpio_debounce - low level gpio debounce time
204 * @bank: the gpio bank we're acting upon
205 * @offset: the gpio number on this @bank
206 * @debounce: debounce time to use
208 * OMAP's debounce time is in 31us steps
209 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
210 * so we need to convert and round up to the closest unit.
212 static void omap2_set_gpio_debounce(struct gpio_bank
*bank
, unsigned offset
,
218 bool enable
= !!debounce
;
220 if (!bank
->dbck_flag
)
224 debounce
= DIV_ROUND_UP(debounce
, 31) - 1;
225 debounce
&= OMAP4_GPIO_DEBOUNCINGTIME_MASK
;
230 clk_prepare_enable(bank
->dbck
);
231 reg
= bank
->base
+ bank
->regs
->debounce
;
232 writel_relaxed(debounce
, reg
);
234 reg
= bank
->base
+ bank
->regs
->debounce_en
;
235 val
= readl_relaxed(reg
);
241 bank
->dbck_enable_mask
= val
;
243 writel_relaxed(val
, reg
);
244 clk_disable_unprepare(bank
->dbck
);
246 * Enable debounce clock per module.
247 * This call is mandatory because in omap_gpio_request() when
248 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
249 * runtime callbck fails to turn on dbck because dbck_enable_mask
250 * used within _gpio_dbck_enable() is still not initialized at
251 * that point. Therefore we have to enable dbck here.
253 omap_gpio_dbck_enable(bank
);
254 if (bank
->dbck_enable_mask
) {
255 bank
->context
.debounce
= debounce
;
256 bank
->context
.debounce_en
= val
;
261 * omap_clear_gpio_debounce - clear debounce settings for a gpio
262 * @bank: the gpio bank we're acting upon
263 * @offset: the gpio number on this @bank
265 * If a gpio is using debounce, then clear the debounce enable bit and if
266 * this is the only gpio in this bank using debounce, then clear the debounce
267 * time too. The debounce clock will also be disabled when calling this function
268 * if this is the only gpio in the bank using debounce.
270 static void omap_clear_gpio_debounce(struct gpio_bank
*bank
, unsigned offset
)
272 u32 gpio_bit
= BIT(offset
);
274 if (!bank
->dbck_flag
)
277 if (!(bank
->dbck_enable_mask
& gpio_bit
))
280 bank
->dbck_enable_mask
&= ~gpio_bit
;
281 bank
->context
.debounce_en
&= ~gpio_bit
;
282 writel_relaxed(bank
->context
.debounce_en
,
283 bank
->base
+ bank
->regs
->debounce_en
);
285 if (!bank
->dbck_enable_mask
) {
286 bank
->context
.debounce
= 0;
287 writel_relaxed(bank
->context
.debounce
, bank
->base
+
288 bank
->regs
->debounce
);
289 clk_disable_unprepare(bank
->dbck
);
290 bank
->dbck_enabled
= false;
294 static inline void omap_set_gpio_trigger(struct gpio_bank
*bank
, int gpio
,
297 void __iomem
*base
= bank
->base
;
298 u32 gpio_bit
= BIT(gpio
);
300 omap_gpio_rmw(base
, bank
->regs
->leveldetect0
, gpio_bit
,
301 trigger
& IRQ_TYPE_LEVEL_LOW
);
302 omap_gpio_rmw(base
, bank
->regs
->leveldetect1
, gpio_bit
,
303 trigger
& IRQ_TYPE_LEVEL_HIGH
);
304 omap_gpio_rmw(base
, bank
->regs
->risingdetect
, gpio_bit
,
305 trigger
& IRQ_TYPE_EDGE_RISING
);
306 omap_gpio_rmw(base
, bank
->regs
->fallingdetect
, gpio_bit
,
307 trigger
& IRQ_TYPE_EDGE_FALLING
);
309 bank
->context
.leveldetect0
=
310 readl_relaxed(bank
->base
+ bank
->regs
->leveldetect0
);
311 bank
->context
.leveldetect1
=
312 readl_relaxed(bank
->base
+ bank
->regs
->leveldetect1
);
313 bank
->context
.risingdetect
=
314 readl_relaxed(bank
->base
+ bank
->regs
->risingdetect
);
315 bank
->context
.fallingdetect
=
316 readl_relaxed(bank
->base
+ bank
->regs
->fallingdetect
);
318 if (likely(!(bank
->non_wakeup_gpios
& gpio_bit
))) {
319 omap_gpio_rmw(base
, bank
->regs
->wkup_en
, gpio_bit
, trigger
!= 0);
320 bank
->context
.wake_en
=
321 readl_relaxed(bank
->base
+ bank
->regs
->wkup_en
);
324 /* This part needs to be executed always for OMAP{34xx, 44xx} */
325 if (!bank
->regs
->irqctrl
) {
326 /* On omap24xx proceed only when valid GPIO bit is set */
327 if (bank
->non_wakeup_gpios
) {
328 if (!(bank
->non_wakeup_gpios
& gpio_bit
))
333 * Log the edge gpio and manually trigger the IRQ
334 * after resume if the input level changes
335 * to avoid irq lost during PER RET/OFF mode
336 * Applies for omap2 non-wakeup gpio and all omap3 gpios
338 if (trigger
& IRQ_TYPE_EDGE_BOTH
)
339 bank
->enabled_non_wakeup_gpios
|= gpio_bit
;
341 bank
->enabled_non_wakeup_gpios
&= ~gpio_bit
;
346 readl_relaxed(bank
->base
+ bank
->regs
->leveldetect0
) |
347 readl_relaxed(bank
->base
+ bank
->regs
->leveldetect1
);
350 #ifdef CONFIG_ARCH_OMAP1
352 * This only applies to chips that can't do both rising and falling edge
353 * detection at once. For all other chips, this function is a noop.
355 static void omap_toggle_gpio_edge_triggering(struct gpio_bank
*bank
, int gpio
)
357 void __iomem
*reg
= bank
->base
;
360 if (!bank
->regs
->irqctrl
)
363 reg
+= bank
->regs
->irqctrl
;
365 l
= readl_relaxed(reg
);
371 writel_relaxed(l
, reg
);
374 static void omap_toggle_gpio_edge_triggering(struct gpio_bank
*bank
, int gpio
) {}
377 static int omap_set_gpio_triggering(struct gpio_bank
*bank
, int gpio
,
380 void __iomem
*reg
= bank
->base
;
381 void __iomem
*base
= bank
->base
;
384 if (bank
->regs
->leveldetect0
&& bank
->regs
->wkup_en
) {
385 omap_set_gpio_trigger(bank
, gpio
, trigger
);
386 } else if (bank
->regs
->irqctrl
) {
387 reg
+= bank
->regs
->irqctrl
;
389 l
= readl_relaxed(reg
);
390 if ((trigger
& IRQ_TYPE_SENSE_MASK
) == IRQ_TYPE_EDGE_BOTH
)
391 bank
->toggle_mask
|= BIT(gpio
);
392 if (trigger
& IRQ_TYPE_EDGE_RISING
)
394 else if (trigger
& IRQ_TYPE_EDGE_FALLING
)
399 writel_relaxed(l
, reg
);
400 } else if (bank
->regs
->edgectrl1
) {
402 reg
+= bank
->regs
->edgectrl2
;
404 reg
+= bank
->regs
->edgectrl1
;
407 l
= readl_relaxed(reg
);
408 l
&= ~(3 << (gpio
<< 1));
409 if (trigger
& IRQ_TYPE_EDGE_RISING
)
410 l
|= 2 << (gpio
<< 1);
411 if (trigger
& IRQ_TYPE_EDGE_FALLING
)
414 /* Enable wake-up during idle for dynamic tick */
415 omap_gpio_rmw(base
, bank
->regs
->wkup_en
, BIT(gpio
), trigger
);
416 bank
->context
.wake_en
=
417 readl_relaxed(bank
->base
+ bank
->regs
->wkup_en
);
418 writel_relaxed(l
, reg
);
423 static void omap_enable_gpio_module(struct gpio_bank
*bank
, unsigned offset
)
425 if (bank
->regs
->pinctrl
) {
426 void __iomem
*reg
= bank
->base
+ bank
->regs
->pinctrl
;
428 /* Claim the pin for MPU */
429 writel_relaxed(readl_relaxed(reg
) | (BIT(offset
)), reg
);
432 if (bank
->regs
->ctrl
&& !BANK_USED(bank
)) {
433 void __iomem
*reg
= bank
->base
+ bank
->regs
->ctrl
;
436 ctrl
= readl_relaxed(reg
);
437 /* Module is enabled, clocks are not gated */
438 ctrl
&= ~GPIO_MOD_CTRL_BIT
;
439 writel_relaxed(ctrl
, reg
);
440 bank
->context
.ctrl
= ctrl
;
444 static void omap_disable_gpio_module(struct gpio_bank
*bank
, unsigned offset
)
446 void __iomem
*base
= bank
->base
;
448 if (bank
->regs
->wkup_en
&&
449 !LINE_USED(bank
->mod_usage
, offset
) &&
450 !LINE_USED(bank
->irq_usage
, offset
)) {
451 /* Disable wake-up during idle for dynamic tick */
452 omap_gpio_rmw(base
, bank
->regs
->wkup_en
, BIT(offset
), 0);
453 bank
->context
.wake_en
=
454 readl_relaxed(bank
->base
+ bank
->regs
->wkup_en
);
457 if (bank
->regs
->ctrl
&& !BANK_USED(bank
)) {
458 void __iomem
*reg
= bank
->base
+ bank
->regs
->ctrl
;
461 ctrl
= readl_relaxed(reg
);
462 /* Module is disabled, clocks are gated */
463 ctrl
|= GPIO_MOD_CTRL_BIT
;
464 writel_relaxed(ctrl
, reg
);
465 bank
->context
.ctrl
= ctrl
;
469 static int omap_gpio_is_input(struct gpio_bank
*bank
, unsigned offset
)
471 void __iomem
*reg
= bank
->base
+ bank
->regs
->direction
;
473 return readl_relaxed(reg
) & BIT(offset
);
476 static void omap_gpio_init_irq(struct gpio_bank
*bank
, unsigned offset
)
478 if (!LINE_USED(bank
->mod_usage
, offset
)) {
479 omap_enable_gpio_module(bank
, offset
);
480 omap_set_gpio_direction(bank
, offset
, 1);
482 bank
->irq_usage
|= BIT(offset
);
485 static int omap_gpio_irq_type(struct irq_data
*d
, unsigned type
)
487 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
490 unsigned offset
= d
->hwirq
;
492 if (type
& ~IRQ_TYPE_SENSE_MASK
)
495 if (!bank
->regs
->leveldetect0
&&
496 (type
& (IRQ_TYPE_LEVEL_LOW
|IRQ_TYPE_LEVEL_HIGH
)))
499 if (!BANK_USED(bank
))
500 pm_runtime_get_sync(bank
->dev
);
502 raw_spin_lock_irqsave(&bank
->lock
, flags
);
503 retval
= omap_set_gpio_triggering(bank
, offset
, type
);
505 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
508 omap_gpio_init_irq(bank
, offset
);
509 if (!omap_gpio_is_input(bank
, offset
)) {
510 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
514 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
516 if (type
& (IRQ_TYPE_LEVEL_LOW
| IRQ_TYPE_LEVEL_HIGH
))
517 irq_set_handler_locked(d
, handle_level_irq
);
518 else if (type
& (IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
519 irq_set_handler_locked(d
, handle_edge_irq
);
524 if (!BANK_USED(bank
))
525 pm_runtime_put(bank
->dev
);
529 static void omap_clear_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
)
531 void __iomem
*reg
= bank
->base
;
533 reg
+= bank
->regs
->irqstatus
;
534 writel_relaxed(gpio_mask
, reg
);
536 /* Workaround for clearing DSP GPIO interrupts to allow retention */
537 if (bank
->regs
->irqstatus2
) {
538 reg
= bank
->base
+ bank
->regs
->irqstatus2
;
539 writel_relaxed(gpio_mask
, reg
);
542 /* Flush posted write for the irq status to avoid spurious interrupts */
546 static inline void omap_clear_gpio_irqstatus(struct gpio_bank
*bank
,
549 omap_clear_gpio_irqbank(bank
, BIT(offset
));
552 static u32
omap_get_gpio_irqbank_mask(struct gpio_bank
*bank
)
554 void __iomem
*reg
= bank
->base
;
556 u32 mask
= (BIT(bank
->width
)) - 1;
558 reg
+= bank
->regs
->irqenable
;
559 l
= readl_relaxed(reg
);
560 if (bank
->regs
->irqenable_inv
)
566 static void omap_enable_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
)
568 void __iomem
*reg
= bank
->base
;
571 if (bank
->regs
->set_irqenable
) {
572 reg
+= bank
->regs
->set_irqenable
;
574 bank
->context
.irqenable1
|= gpio_mask
;
576 reg
+= bank
->regs
->irqenable
;
577 l
= readl_relaxed(reg
);
578 if (bank
->regs
->irqenable_inv
)
582 bank
->context
.irqenable1
= l
;
585 writel_relaxed(l
, reg
);
588 static void omap_disable_gpio_irqbank(struct gpio_bank
*bank
, int gpio_mask
)
590 void __iomem
*reg
= bank
->base
;
593 if (bank
->regs
->clr_irqenable
) {
594 reg
+= bank
->regs
->clr_irqenable
;
596 bank
->context
.irqenable1
&= ~gpio_mask
;
598 reg
+= bank
->regs
->irqenable
;
599 l
= readl_relaxed(reg
);
600 if (bank
->regs
->irqenable_inv
)
604 bank
->context
.irqenable1
= l
;
607 writel_relaxed(l
, reg
);
610 static inline void omap_set_gpio_irqenable(struct gpio_bank
*bank
,
611 unsigned offset
, int enable
)
614 omap_enable_gpio_irqbank(bank
, BIT(offset
));
616 omap_disable_gpio_irqbank(bank
, BIT(offset
));
620 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
621 * 1510 does not seem to have a wake-up register. If JTAG is connected
622 * to the target, system will wake up always on GPIO events. While
623 * system is running all registered GPIO interrupts need to have wake-up
624 * enabled. When system is suspended, only selected GPIO interrupts need
625 * to have wake-up enabled.
627 static int omap_set_gpio_wakeup(struct gpio_bank
*bank
, unsigned offset
,
630 u32 gpio_bit
= BIT(offset
);
633 if (bank
->non_wakeup_gpios
& gpio_bit
) {
635 "Unable to modify wakeup on non-wakeup GPIO%d\n",
640 raw_spin_lock_irqsave(&bank
->lock
, flags
);
642 bank
->context
.wake_en
|= gpio_bit
;
644 bank
->context
.wake_en
&= ~gpio_bit
;
646 writel_relaxed(bank
->context
.wake_en
, bank
->base
+ bank
->regs
->wkup_en
);
647 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
652 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
653 static int omap_gpio_wake_enable(struct irq_data
*d
, unsigned int enable
)
655 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
656 unsigned offset
= d
->hwirq
;
658 return omap_set_gpio_wakeup(bank
, offset
, enable
);
661 static int omap_gpio_request(struct gpio_chip
*chip
, unsigned offset
)
663 struct gpio_bank
*bank
= container_of(chip
, struct gpio_bank
, chip
);
667 * If this is the first gpio_request for the bank,
668 * enable the bank module.
670 if (!BANK_USED(bank
))
671 pm_runtime_get_sync(bank
->dev
);
673 raw_spin_lock_irqsave(&bank
->lock
, flags
);
674 omap_enable_gpio_module(bank
, offset
);
675 bank
->mod_usage
|= BIT(offset
);
676 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
681 static void omap_gpio_free(struct gpio_chip
*chip
, unsigned offset
)
683 struct gpio_bank
*bank
= container_of(chip
, struct gpio_bank
, chip
);
686 raw_spin_lock_irqsave(&bank
->lock
, flags
);
687 bank
->mod_usage
&= ~(BIT(offset
));
688 if (!LINE_USED(bank
->irq_usage
, offset
)) {
689 omap_set_gpio_direction(bank
, offset
, 1);
690 omap_clear_gpio_debounce(bank
, offset
);
692 omap_disable_gpio_module(bank
, offset
);
693 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
696 * If this is the last gpio to be freed in the bank,
697 * disable the bank module.
699 if (!BANK_USED(bank
))
700 pm_runtime_put(bank
->dev
);
704 * We need to unmask the GPIO bank interrupt as soon as possible to
705 * avoid missing GPIO interrupts for other lines in the bank.
706 * Then we need to mask-read-clear-unmask the triggered GPIO lines
707 * in the bank to avoid missing nested interrupts for a GPIO line.
708 * If we wait to unmask individual GPIO lines in the bank after the
709 * line's interrupt handler has been run, we may miss some nested
712 static void omap_gpio_irq_handler(unsigned int irq
, struct irq_desc
*desc
)
714 void __iomem
*isr_reg
= NULL
;
717 struct gpio_bank
*bank
;
719 struct irq_chip
*irqchip
= irq_desc_get_chip(desc
);
720 struct gpio_chip
*chip
= irq_desc_get_handler_data(desc
);
722 chained_irq_enter(irqchip
, desc
);
724 bank
= container_of(chip
, struct gpio_bank
, chip
);
725 isr_reg
= bank
->base
+ bank
->regs
->irqstatus
;
726 pm_runtime_get_sync(bank
->dev
);
728 if (WARN_ON(!isr_reg
))
732 u32 isr_saved
, level_mask
= 0;
735 enabled
= omap_get_gpio_irqbank_mask(bank
);
736 isr_saved
= isr
= readl_relaxed(isr_reg
) & enabled
;
738 if (bank
->level_mask
)
739 level_mask
= bank
->level_mask
& enabled
;
741 /* clear edge sensitive interrupts before handler(s) are
742 called so that we don't miss any interrupt occurred while
744 omap_disable_gpio_irqbank(bank
, isr_saved
& ~level_mask
);
745 omap_clear_gpio_irqbank(bank
, isr_saved
& ~level_mask
);
746 omap_enable_gpio_irqbank(bank
, isr_saved
& ~level_mask
);
748 /* if there is only edge sensitive GPIO pin interrupts
749 configured, we could unmask GPIO bank interrupt immediately */
750 if (!level_mask
&& !unmasked
) {
752 chained_irq_exit(irqchip
, desc
);
763 * Some chips can't respond to both rising and falling
764 * at the same time. If this irq was requested with
765 * both flags, we need to flip the ICR data for the IRQ
766 * to respond to the IRQ for the opposite direction.
767 * This will be indicated in the bank toggle_mask.
769 if (bank
->toggle_mask
& (BIT(bit
)))
770 omap_toggle_gpio_edge_triggering(bank
, bit
);
772 generic_handle_irq(irq_find_mapping(bank
->chip
.irqdomain
,
776 /* if bank has any level sensitive GPIO pin interrupt
777 configured, we must unmask the bank interrupt only after
778 handler(s) are executed in order to avoid spurious bank
782 chained_irq_exit(irqchip
, desc
);
783 pm_runtime_put(bank
->dev
);
786 static unsigned int omap_gpio_irq_startup(struct irq_data
*d
)
788 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
790 unsigned offset
= d
->hwirq
;
792 if (!BANK_USED(bank
))
793 pm_runtime_get_sync(bank
->dev
);
795 raw_spin_lock_irqsave(&bank
->lock
, flags
);
797 if (!LINE_USED(bank
->mod_usage
, offset
))
798 omap_set_gpio_direction(bank
, offset
, 1);
799 else if (!omap_gpio_is_input(bank
, offset
))
801 omap_enable_gpio_module(bank
, offset
);
802 bank
->irq_usage
|= BIT(offset
);
804 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
805 omap_gpio_unmask_irq(d
);
809 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
810 if (!BANK_USED(bank
))
811 pm_runtime_put(bank
->dev
);
815 static void omap_gpio_irq_shutdown(struct irq_data
*d
)
817 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
819 unsigned offset
= d
->hwirq
;
821 raw_spin_lock_irqsave(&bank
->lock
, flags
);
822 bank
->irq_usage
&= ~(BIT(offset
));
823 omap_set_gpio_irqenable(bank
, offset
, 0);
824 omap_clear_gpio_irqstatus(bank
, offset
);
825 omap_set_gpio_triggering(bank
, offset
, IRQ_TYPE_NONE
);
826 if (!LINE_USED(bank
->mod_usage
, offset
))
827 omap_clear_gpio_debounce(bank
, offset
);
828 omap_disable_gpio_module(bank
, offset
);
829 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
832 * If this is the last IRQ to be freed in the bank,
833 * disable the bank module.
835 if (!BANK_USED(bank
))
836 pm_runtime_put(bank
->dev
);
839 static void omap_gpio_ack_irq(struct irq_data
*d
)
841 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
842 unsigned offset
= d
->hwirq
;
844 omap_clear_gpio_irqstatus(bank
, offset
);
847 static void omap_gpio_mask_irq(struct irq_data
*d
)
849 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
850 unsigned offset
= d
->hwirq
;
853 raw_spin_lock_irqsave(&bank
->lock
, flags
);
854 omap_set_gpio_irqenable(bank
, offset
, 0);
855 omap_set_gpio_triggering(bank
, offset
, IRQ_TYPE_NONE
);
856 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
859 static void omap_gpio_unmask_irq(struct irq_data
*d
)
861 struct gpio_bank
*bank
= omap_irq_data_get_bank(d
);
862 unsigned offset
= d
->hwirq
;
863 u32 trigger
= irqd_get_trigger_type(d
);
866 raw_spin_lock_irqsave(&bank
->lock
, flags
);
868 omap_set_gpio_triggering(bank
, offset
, trigger
);
870 /* For level-triggered GPIOs, the clearing must be done after
871 * the HW source is cleared, thus after the handler has run */
872 if (bank
->level_mask
& BIT(offset
)) {
873 omap_set_gpio_irqenable(bank
, offset
, 0);
874 omap_clear_gpio_irqstatus(bank
, offset
);
877 omap_set_gpio_irqenable(bank
, offset
, 1);
878 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
881 /*---------------------------------------------------------------------*/
883 static int omap_mpuio_suspend_noirq(struct device
*dev
)
885 struct platform_device
*pdev
= to_platform_device(dev
);
886 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
887 void __iomem
*mask_reg
= bank
->base
+
888 OMAP_MPUIO_GPIO_MASKIT
/ bank
->stride
;
891 raw_spin_lock_irqsave(&bank
->lock
, flags
);
892 writel_relaxed(0xffff & ~bank
->context
.wake_en
, mask_reg
);
893 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
898 static int omap_mpuio_resume_noirq(struct device
*dev
)
900 struct platform_device
*pdev
= to_platform_device(dev
);
901 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
902 void __iomem
*mask_reg
= bank
->base
+
903 OMAP_MPUIO_GPIO_MASKIT
/ bank
->stride
;
906 raw_spin_lock_irqsave(&bank
->lock
, flags
);
907 writel_relaxed(bank
->context
.wake_en
, mask_reg
);
908 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
913 static const struct dev_pm_ops omap_mpuio_dev_pm_ops
= {
914 .suspend_noirq
= omap_mpuio_suspend_noirq
,
915 .resume_noirq
= omap_mpuio_resume_noirq
,
918 /* use platform_driver for this. */
919 static struct platform_driver omap_mpuio_driver
= {
922 .pm
= &omap_mpuio_dev_pm_ops
,
926 static struct platform_device omap_mpuio_device
= {
930 .driver
= &omap_mpuio_driver
.driver
,
932 /* could list the /proc/iomem resources */
935 static inline void omap_mpuio_init(struct gpio_bank
*bank
)
937 platform_set_drvdata(&omap_mpuio_device
, bank
);
939 if (platform_driver_register(&omap_mpuio_driver
) == 0)
940 (void) platform_device_register(&omap_mpuio_device
);
943 /*---------------------------------------------------------------------*/
945 static int omap_gpio_get_direction(struct gpio_chip
*chip
, unsigned offset
)
947 struct gpio_bank
*bank
;
952 bank
= container_of(chip
, struct gpio_bank
, chip
);
953 reg
= bank
->base
+ bank
->regs
->direction
;
954 raw_spin_lock_irqsave(&bank
->lock
, flags
);
955 dir
= !!(readl_relaxed(reg
) & BIT(offset
));
956 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
960 static int omap_gpio_input(struct gpio_chip
*chip
, unsigned offset
)
962 struct gpio_bank
*bank
;
965 bank
= container_of(chip
, struct gpio_bank
, chip
);
966 raw_spin_lock_irqsave(&bank
->lock
, flags
);
967 omap_set_gpio_direction(bank
, offset
, 1);
968 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
972 static int omap_gpio_get(struct gpio_chip
*chip
, unsigned offset
)
974 struct gpio_bank
*bank
;
976 bank
= container_of(chip
, struct gpio_bank
, chip
);
978 if (omap_gpio_is_input(bank
, offset
))
979 return omap_get_gpio_datain(bank
, offset
);
981 return omap_get_gpio_dataout(bank
, offset
);
984 static int omap_gpio_output(struct gpio_chip
*chip
, unsigned offset
, int value
)
986 struct gpio_bank
*bank
;
989 bank
= container_of(chip
, struct gpio_bank
, chip
);
990 raw_spin_lock_irqsave(&bank
->lock
, flags
);
991 bank
->set_dataout(bank
, offset
, value
);
992 omap_set_gpio_direction(bank
, offset
, 0);
993 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
997 static int omap_gpio_debounce(struct gpio_chip
*chip
, unsigned offset
,
1000 struct gpio_bank
*bank
;
1001 unsigned long flags
;
1003 bank
= container_of(chip
, struct gpio_bank
, chip
);
1005 raw_spin_lock_irqsave(&bank
->lock
, flags
);
1006 omap2_set_gpio_debounce(bank
, offset
, debounce
);
1007 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
1012 static void omap_gpio_set(struct gpio_chip
*chip
, unsigned offset
, int value
)
1014 struct gpio_bank
*bank
;
1015 unsigned long flags
;
1017 bank
= container_of(chip
, struct gpio_bank
, chip
);
1018 raw_spin_lock_irqsave(&bank
->lock
, flags
);
1019 bank
->set_dataout(bank
, offset
, value
);
1020 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
1023 /*---------------------------------------------------------------------*/
1025 static void __init
omap_gpio_show_rev(struct gpio_bank
*bank
)
1030 if (called
|| bank
->regs
->revision
== USHRT_MAX
)
1033 rev
= readw_relaxed(bank
->base
+ bank
->regs
->revision
);
1034 pr_info("OMAP GPIO hardware version %d.%d\n",
1035 (rev
>> 4) & 0x0f, rev
& 0x0f);
1040 static void omap_gpio_mod_init(struct gpio_bank
*bank
)
1042 void __iomem
*base
= bank
->base
;
1045 if (bank
->width
== 16)
1048 if (bank
->is_mpuio
) {
1049 writel_relaxed(l
, bank
->base
+ bank
->regs
->irqenable
);
1053 omap_gpio_rmw(base
, bank
->regs
->irqenable
, l
,
1054 bank
->regs
->irqenable_inv
);
1055 omap_gpio_rmw(base
, bank
->regs
->irqstatus
, l
,
1056 !bank
->regs
->irqenable_inv
);
1057 if (bank
->regs
->debounce_en
)
1058 writel_relaxed(0, base
+ bank
->regs
->debounce_en
);
1060 /* Save OE default value (0xffffffff) in the context */
1061 bank
->context
.oe
= readl_relaxed(bank
->base
+ bank
->regs
->direction
);
1062 /* Initialize interface clk ungated, module enabled */
1063 if (bank
->regs
->ctrl
)
1064 writel_relaxed(0, base
+ bank
->regs
->ctrl
);
1066 bank
->dbck
= clk_get(bank
->dev
, "dbclk");
1067 if (IS_ERR(bank
->dbck
))
1068 dev_err(bank
->dev
, "Could not get gpio dbck\n");
1071 static int omap_gpio_chip_init(struct gpio_bank
*bank
, struct irq_chip
*irqc
)
1078 * REVISIT eventually switch from OMAP-specific gpio structs
1079 * over to the generic ones
1081 bank
->chip
.request
= omap_gpio_request
;
1082 bank
->chip
.free
= omap_gpio_free
;
1083 bank
->chip
.get_direction
= omap_gpio_get_direction
;
1084 bank
->chip
.direction_input
= omap_gpio_input
;
1085 bank
->chip
.get
= omap_gpio_get
;
1086 bank
->chip
.direction_output
= omap_gpio_output
;
1087 bank
->chip
.set_debounce
= omap_gpio_debounce
;
1088 bank
->chip
.set
= omap_gpio_set
;
1089 if (bank
->is_mpuio
) {
1090 bank
->chip
.label
= "mpuio";
1091 if (bank
->regs
->wkup_en
)
1092 bank
->chip
.dev
= &omap_mpuio_device
.dev
;
1093 bank
->chip
.base
= OMAP_MPUIO(0);
1095 bank
->chip
.label
= "gpio";
1096 bank
->chip
.base
= gpio
;
1097 gpio
+= bank
->width
;
1099 bank
->chip
.ngpio
= bank
->width
;
1101 ret
= gpiochip_add(&bank
->chip
);
1103 dev_err(bank
->dev
, "Could not register gpio chip %d\n", ret
);
1107 #ifdef CONFIG_ARCH_OMAP1
1109 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1110 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1112 irq_base
= irq_alloc_descs(-1, 0, bank
->width
, 0);
1114 dev_err(bank
->dev
, "Couldn't allocate IRQ numbers\n");
1119 /* MPUIO is a bit different, reading IRQ status clears it */
1120 if (bank
->is_mpuio
) {
1121 irqc
->irq_ack
= dummy_irq_chip
.irq_ack
;
1122 irqc
->irq_mask
= irq_gc_mask_set_bit
;
1123 irqc
->irq_unmask
= irq_gc_mask_clr_bit
;
1124 if (!bank
->regs
->wkup_en
)
1125 irqc
->irq_set_wake
= NULL
;
1128 ret
= gpiochip_irqchip_add(&bank
->chip
, irqc
,
1129 irq_base
, omap_gpio_irq_handler
,
1133 dev_err(bank
->dev
, "Couldn't add irqchip to gpiochip %d\n", ret
);
1134 gpiochip_remove(&bank
->chip
);
1138 gpiochip_set_chained_irqchip(&bank
->chip
, irqc
,
1139 bank
->irq
, omap_gpio_irq_handler
);
1144 static const struct of_device_id omap_gpio_match
[];
1146 static int omap_gpio_probe(struct platform_device
*pdev
)
1148 struct device
*dev
= &pdev
->dev
;
1149 struct device_node
*node
= dev
->of_node
;
1150 const struct of_device_id
*match
;
1151 const struct omap_gpio_platform_data
*pdata
;
1152 struct resource
*res
;
1153 struct gpio_bank
*bank
;
1154 struct irq_chip
*irqc
;
1157 match
= of_match_device(of_match_ptr(omap_gpio_match
), dev
);
1159 pdata
= match
? match
->data
: dev_get_platdata(dev
);
1163 bank
= devm_kzalloc(dev
, sizeof(struct gpio_bank
), GFP_KERNEL
);
1165 dev_err(dev
, "Memory alloc failed\n");
1169 irqc
= devm_kzalloc(dev
, sizeof(*irqc
), GFP_KERNEL
);
1173 irqc
->irq_startup
= omap_gpio_irq_startup
,
1174 irqc
->irq_shutdown
= omap_gpio_irq_shutdown
,
1175 irqc
->irq_ack
= omap_gpio_ack_irq
,
1176 irqc
->irq_mask
= omap_gpio_mask_irq
,
1177 irqc
->irq_unmask
= omap_gpio_unmask_irq
,
1178 irqc
->irq_set_type
= omap_gpio_irq_type
,
1179 irqc
->irq_set_wake
= omap_gpio_wake_enable
,
1180 irqc
->name
= dev_name(&pdev
->dev
);
1182 bank
->irq
= platform_get_irq(pdev
, 0);
1183 if (bank
->irq
<= 0) {
1186 if (bank
->irq
!= -EPROBE_DEFER
)
1188 "can't get irq resource ret=%d\n", bank
->irq
);
1193 bank
->chip
.dev
= dev
;
1194 bank
->chip
.owner
= THIS_MODULE
;
1195 bank
->dbck_flag
= pdata
->dbck_flag
;
1196 bank
->stride
= pdata
->bank_stride
;
1197 bank
->width
= pdata
->bank_width
;
1198 bank
->is_mpuio
= pdata
->is_mpuio
;
1199 bank
->non_wakeup_gpios
= pdata
->non_wakeup_gpios
;
1200 bank
->regs
= pdata
->regs
;
1201 #ifdef CONFIG_OF_GPIO
1202 bank
->chip
.of_node
= of_node_get(node
);
1205 if (!of_property_read_bool(node
, "ti,gpio-always-on"))
1206 bank
->loses_context
= true;
1208 bank
->loses_context
= pdata
->loses_context
;
1210 if (bank
->loses_context
)
1211 bank
->get_context_loss_count
=
1212 pdata
->get_context_loss_count
;
1215 if (bank
->regs
->set_dataout
&& bank
->regs
->clr_dataout
)
1216 bank
->set_dataout
= omap_set_gpio_dataout_reg
;
1218 bank
->set_dataout
= omap_set_gpio_dataout_mask
;
1220 raw_spin_lock_init(&bank
->lock
);
1222 /* Static mapping, never released */
1223 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1224 bank
->base
= devm_ioremap_resource(dev
, res
);
1225 if (IS_ERR(bank
->base
)) {
1226 return PTR_ERR(bank
->base
);
1229 platform_set_drvdata(pdev
, bank
);
1231 pm_runtime_enable(bank
->dev
);
1232 pm_runtime_irq_safe(bank
->dev
);
1233 pm_runtime_get_sync(bank
->dev
);
1236 omap_mpuio_init(bank
);
1238 omap_gpio_mod_init(bank
);
1240 ret
= omap_gpio_chip_init(bank
, irqc
);
1244 omap_gpio_show_rev(bank
);
1246 pm_runtime_put(bank
->dev
);
1248 list_add_tail(&bank
->node
, &omap_gpio_list
);
1253 static int omap_gpio_remove(struct platform_device
*pdev
)
1255 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1257 list_del(&bank
->node
);
1258 gpiochip_remove(&bank
->chip
);
1259 pm_runtime_disable(bank
->dev
);
1264 #ifdef CONFIG_ARCH_OMAP2PLUS
1266 #if defined(CONFIG_PM)
1267 static void omap_gpio_restore_context(struct gpio_bank
*bank
);
1269 static int omap_gpio_runtime_suspend(struct device
*dev
)
1271 struct platform_device
*pdev
= to_platform_device(dev
);
1272 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1274 unsigned long flags
;
1275 u32 wake_low
, wake_hi
;
1277 raw_spin_lock_irqsave(&bank
->lock
, flags
);
1280 * Only edges can generate a wakeup event to the PRCM.
1282 * Therefore, ensure any wake-up capable GPIOs have
1283 * edge-detection enabled before going idle to ensure a wakeup
1284 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1287 * The normal values will be restored upon ->runtime_resume()
1288 * by writing back the values saved in bank->context.
1290 wake_low
= bank
->context
.leveldetect0
& bank
->context
.wake_en
;
1292 writel_relaxed(wake_low
| bank
->context
.fallingdetect
,
1293 bank
->base
+ bank
->regs
->fallingdetect
);
1294 wake_hi
= bank
->context
.leveldetect1
& bank
->context
.wake_en
;
1296 writel_relaxed(wake_hi
| bank
->context
.risingdetect
,
1297 bank
->base
+ bank
->regs
->risingdetect
);
1299 if (!bank
->enabled_non_wakeup_gpios
)
1300 goto update_gpio_context_count
;
1302 if (bank
->power_mode
!= OFF_MODE
) {
1303 bank
->power_mode
= 0;
1304 goto update_gpio_context_count
;
1307 * If going to OFF, remove triggering for all
1308 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1309 * generated. See OMAP2420 Errata item 1.101.
1311 bank
->saved_datain
= readl_relaxed(bank
->base
+
1312 bank
->regs
->datain
);
1313 l1
= bank
->context
.fallingdetect
;
1314 l2
= bank
->context
.risingdetect
;
1316 l1
&= ~bank
->enabled_non_wakeup_gpios
;
1317 l2
&= ~bank
->enabled_non_wakeup_gpios
;
1319 writel_relaxed(l1
, bank
->base
+ bank
->regs
->fallingdetect
);
1320 writel_relaxed(l2
, bank
->base
+ bank
->regs
->risingdetect
);
1322 bank
->workaround_enabled
= true;
1324 update_gpio_context_count
:
1325 if (bank
->get_context_loss_count
)
1326 bank
->context_loss_count
=
1327 bank
->get_context_loss_count(bank
->dev
);
1329 omap_gpio_dbck_disable(bank
);
1330 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
1335 static void omap_gpio_init_context(struct gpio_bank
*p
);
1337 static int omap_gpio_runtime_resume(struct device
*dev
)
1339 struct platform_device
*pdev
= to_platform_device(dev
);
1340 struct gpio_bank
*bank
= platform_get_drvdata(pdev
);
1341 u32 l
= 0, gen
, gen0
, gen1
;
1342 unsigned long flags
;
1345 raw_spin_lock_irqsave(&bank
->lock
, flags
);
1348 * On the first resume during the probe, the context has not
1349 * been initialised and so initialise it now. Also initialise
1350 * the context loss count.
1352 if (bank
->loses_context
&& !bank
->context_valid
) {
1353 omap_gpio_init_context(bank
);
1355 if (bank
->get_context_loss_count
)
1356 bank
->context_loss_count
=
1357 bank
->get_context_loss_count(bank
->dev
);
1360 omap_gpio_dbck_enable(bank
);
1363 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1364 * GPIOs were set to edge trigger also in order to be able to
1365 * generate a PRCM wakeup. Here we restore the
1366 * pre-runtime_suspend() values for edge triggering.
1368 writel_relaxed(bank
->context
.fallingdetect
,
1369 bank
->base
+ bank
->regs
->fallingdetect
);
1370 writel_relaxed(bank
->context
.risingdetect
,
1371 bank
->base
+ bank
->regs
->risingdetect
);
1373 if (bank
->loses_context
) {
1374 if (!bank
->get_context_loss_count
) {
1375 omap_gpio_restore_context(bank
);
1377 c
= bank
->get_context_loss_count(bank
->dev
);
1378 if (c
!= bank
->context_loss_count
) {
1379 omap_gpio_restore_context(bank
);
1381 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
1387 if (!bank
->workaround_enabled
) {
1388 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
1392 l
= readl_relaxed(bank
->base
+ bank
->regs
->datain
);
1395 * Check if any of the non-wakeup interrupt GPIOs have changed
1396 * state. If so, generate an IRQ by software. This is
1397 * horribly racy, but it's the best we can do to work around
1400 l
^= bank
->saved_datain
;
1401 l
&= bank
->enabled_non_wakeup_gpios
;
1404 * No need to generate IRQs for the rising edge for gpio IRQs
1405 * configured with falling edge only; and vice versa.
1407 gen0
= l
& bank
->context
.fallingdetect
;
1408 gen0
&= bank
->saved_datain
;
1410 gen1
= l
& bank
->context
.risingdetect
;
1411 gen1
&= ~(bank
->saved_datain
);
1413 /* FIXME: Consider GPIO IRQs with level detections properly! */
1414 gen
= l
& (~(bank
->context
.fallingdetect
) &
1415 ~(bank
->context
.risingdetect
));
1416 /* Consider all GPIO IRQs needed to be updated */
1422 old0
= readl_relaxed(bank
->base
+ bank
->regs
->leveldetect0
);
1423 old1
= readl_relaxed(bank
->base
+ bank
->regs
->leveldetect1
);
1425 if (!bank
->regs
->irqstatus_raw0
) {
1426 writel_relaxed(old0
| gen
, bank
->base
+
1427 bank
->regs
->leveldetect0
);
1428 writel_relaxed(old1
| gen
, bank
->base
+
1429 bank
->regs
->leveldetect1
);
1432 if (bank
->regs
->irqstatus_raw0
) {
1433 writel_relaxed(old0
| l
, bank
->base
+
1434 bank
->regs
->leveldetect0
);
1435 writel_relaxed(old1
| l
, bank
->base
+
1436 bank
->regs
->leveldetect1
);
1438 writel_relaxed(old0
, bank
->base
+ bank
->regs
->leveldetect0
);
1439 writel_relaxed(old1
, bank
->base
+ bank
->regs
->leveldetect1
);
1442 bank
->workaround_enabled
= false;
1443 raw_spin_unlock_irqrestore(&bank
->lock
, flags
);
1447 #endif /* CONFIG_PM */
1449 #if IS_BUILTIN(CONFIG_GPIO_OMAP)
1450 void omap2_gpio_prepare_for_idle(int pwr_mode
)
1452 struct gpio_bank
*bank
;
1454 list_for_each_entry(bank
, &omap_gpio_list
, node
) {
1455 if (!BANK_USED(bank
) || !bank
->loses_context
)
1458 bank
->power_mode
= pwr_mode
;
1460 pm_runtime_put_sync_suspend(bank
->dev
);
1464 void omap2_gpio_resume_after_idle(void)
1466 struct gpio_bank
*bank
;
1468 list_for_each_entry(bank
, &omap_gpio_list
, node
) {
1469 if (!BANK_USED(bank
) || !bank
->loses_context
)
1472 pm_runtime_get_sync(bank
->dev
);
1477 #if defined(CONFIG_PM)
1478 static void omap_gpio_init_context(struct gpio_bank
*p
)
1480 struct omap_gpio_reg_offs
*regs
= p
->regs
;
1481 void __iomem
*base
= p
->base
;
1483 p
->context
.ctrl
= readl_relaxed(base
+ regs
->ctrl
);
1484 p
->context
.oe
= readl_relaxed(base
+ regs
->direction
);
1485 p
->context
.wake_en
= readl_relaxed(base
+ regs
->wkup_en
);
1486 p
->context
.leveldetect0
= readl_relaxed(base
+ regs
->leveldetect0
);
1487 p
->context
.leveldetect1
= readl_relaxed(base
+ regs
->leveldetect1
);
1488 p
->context
.risingdetect
= readl_relaxed(base
+ regs
->risingdetect
);
1489 p
->context
.fallingdetect
= readl_relaxed(base
+ regs
->fallingdetect
);
1490 p
->context
.irqenable1
= readl_relaxed(base
+ regs
->irqenable
);
1491 p
->context
.irqenable2
= readl_relaxed(base
+ regs
->irqenable2
);
1493 if (regs
->set_dataout
&& p
->regs
->clr_dataout
)
1494 p
->context
.dataout
= readl_relaxed(base
+ regs
->set_dataout
);
1496 p
->context
.dataout
= readl_relaxed(base
+ regs
->dataout
);
1498 p
->context_valid
= true;
1501 static void omap_gpio_restore_context(struct gpio_bank
*bank
)
1503 writel_relaxed(bank
->context
.wake_en
,
1504 bank
->base
+ bank
->regs
->wkup_en
);
1505 writel_relaxed(bank
->context
.ctrl
, bank
->base
+ bank
->regs
->ctrl
);
1506 writel_relaxed(bank
->context
.leveldetect0
,
1507 bank
->base
+ bank
->regs
->leveldetect0
);
1508 writel_relaxed(bank
->context
.leveldetect1
,
1509 bank
->base
+ bank
->regs
->leveldetect1
);
1510 writel_relaxed(bank
->context
.risingdetect
,
1511 bank
->base
+ bank
->regs
->risingdetect
);
1512 writel_relaxed(bank
->context
.fallingdetect
,
1513 bank
->base
+ bank
->regs
->fallingdetect
);
1514 if (bank
->regs
->set_dataout
&& bank
->regs
->clr_dataout
)
1515 writel_relaxed(bank
->context
.dataout
,
1516 bank
->base
+ bank
->regs
->set_dataout
);
1518 writel_relaxed(bank
->context
.dataout
,
1519 bank
->base
+ bank
->regs
->dataout
);
1520 writel_relaxed(bank
->context
.oe
, bank
->base
+ bank
->regs
->direction
);
1522 if (bank
->dbck_enable_mask
) {
1523 writel_relaxed(bank
->context
.debounce
, bank
->base
+
1524 bank
->regs
->debounce
);
1525 writel_relaxed(bank
->context
.debounce_en
,
1526 bank
->base
+ bank
->regs
->debounce_en
);
1529 writel_relaxed(bank
->context
.irqenable1
,
1530 bank
->base
+ bank
->regs
->irqenable
);
1531 writel_relaxed(bank
->context
.irqenable2
,
1532 bank
->base
+ bank
->regs
->irqenable2
);
1534 #endif /* CONFIG_PM */
1536 #define omap_gpio_runtime_suspend NULL
1537 #define omap_gpio_runtime_resume NULL
1538 static inline void omap_gpio_init_context(struct gpio_bank
*p
) {}
1541 static const struct dev_pm_ops gpio_pm_ops
= {
1542 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend
, omap_gpio_runtime_resume
,
1546 #if defined(CONFIG_OF)
1547 static struct omap_gpio_reg_offs omap2_gpio_regs
= {
1548 .revision
= OMAP24XX_GPIO_REVISION
,
1549 .direction
= OMAP24XX_GPIO_OE
,
1550 .datain
= OMAP24XX_GPIO_DATAIN
,
1551 .dataout
= OMAP24XX_GPIO_DATAOUT
,
1552 .set_dataout
= OMAP24XX_GPIO_SETDATAOUT
,
1553 .clr_dataout
= OMAP24XX_GPIO_CLEARDATAOUT
,
1554 .irqstatus
= OMAP24XX_GPIO_IRQSTATUS1
,
1555 .irqstatus2
= OMAP24XX_GPIO_IRQSTATUS2
,
1556 .irqenable
= OMAP24XX_GPIO_IRQENABLE1
,
1557 .irqenable2
= OMAP24XX_GPIO_IRQENABLE2
,
1558 .set_irqenable
= OMAP24XX_GPIO_SETIRQENABLE1
,
1559 .clr_irqenable
= OMAP24XX_GPIO_CLEARIRQENABLE1
,
1560 .debounce
= OMAP24XX_GPIO_DEBOUNCE_VAL
,
1561 .debounce_en
= OMAP24XX_GPIO_DEBOUNCE_EN
,
1562 .ctrl
= OMAP24XX_GPIO_CTRL
,
1563 .wkup_en
= OMAP24XX_GPIO_WAKE_EN
,
1564 .leveldetect0
= OMAP24XX_GPIO_LEVELDETECT0
,
1565 .leveldetect1
= OMAP24XX_GPIO_LEVELDETECT1
,
1566 .risingdetect
= OMAP24XX_GPIO_RISINGDETECT
,
1567 .fallingdetect
= OMAP24XX_GPIO_FALLINGDETECT
,
1570 static struct omap_gpio_reg_offs omap4_gpio_regs
= {
1571 .revision
= OMAP4_GPIO_REVISION
,
1572 .direction
= OMAP4_GPIO_OE
,
1573 .datain
= OMAP4_GPIO_DATAIN
,
1574 .dataout
= OMAP4_GPIO_DATAOUT
,
1575 .set_dataout
= OMAP4_GPIO_SETDATAOUT
,
1576 .clr_dataout
= OMAP4_GPIO_CLEARDATAOUT
,
1577 .irqstatus
= OMAP4_GPIO_IRQSTATUS0
,
1578 .irqstatus2
= OMAP4_GPIO_IRQSTATUS1
,
1579 .irqenable
= OMAP4_GPIO_IRQSTATUSSET0
,
1580 .irqenable2
= OMAP4_GPIO_IRQSTATUSSET1
,
1581 .set_irqenable
= OMAP4_GPIO_IRQSTATUSSET0
,
1582 .clr_irqenable
= OMAP4_GPIO_IRQSTATUSCLR0
,
1583 .debounce
= OMAP4_GPIO_DEBOUNCINGTIME
,
1584 .debounce_en
= OMAP4_GPIO_DEBOUNCENABLE
,
1585 .ctrl
= OMAP4_GPIO_CTRL
,
1586 .wkup_en
= OMAP4_GPIO_IRQWAKEN0
,
1587 .leveldetect0
= OMAP4_GPIO_LEVELDETECT0
,
1588 .leveldetect1
= OMAP4_GPIO_LEVELDETECT1
,
1589 .risingdetect
= OMAP4_GPIO_RISINGDETECT
,
1590 .fallingdetect
= OMAP4_GPIO_FALLINGDETECT
,
1593 static const struct omap_gpio_platform_data omap2_pdata
= {
1594 .regs
= &omap2_gpio_regs
,
1599 static const struct omap_gpio_platform_data omap3_pdata
= {
1600 .regs
= &omap2_gpio_regs
,
1605 static const struct omap_gpio_platform_data omap4_pdata
= {
1606 .regs
= &omap4_gpio_regs
,
1611 static const struct of_device_id omap_gpio_match
[] = {
1613 .compatible
= "ti,omap4-gpio",
1614 .data
= &omap4_pdata
,
1617 .compatible
= "ti,omap3-gpio",
1618 .data
= &omap3_pdata
,
1621 .compatible
= "ti,omap2-gpio",
1622 .data
= &omap2_pdata
,
1626 MODULE_DEVICE_TABLE(of
, omap_gpio_match
);
1629 static struct platform_driver omap_gpio_driver
= {
1630 .probe
= omap_gpio_probe
,
1631 .remove
= omap_gpio_remove
,
1633 .name
= "omap_gpio",
1635 .of_match_table
= of_match_ptr(omap_gpio_match
),
1640 * gpio driver register needs to be done before
1641 * machine_init functions access gpio APIs.
1642 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1644 static int __init
omap_gpio_drv_reg(void)
1646 return platform_driver_register(&omap_gpio_driver
);
1648 postcore_initcall(omap_gpio_drv_reg
);
1650 static void __exit
omap_gpio_exit(void)
1652 platform_driver_unregister(&omap_gpio_driver
);
1654 module_exit(omap_gpio_exit
);
1656 MODULE_DESCRIPTION("omap gpio driver");
1657 MODULE_ALIAS("platform:gpio-omap");
1658 MODULE_LICENSE("GPL v2");